JPS56105537A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS56105537A
JPS56105537A JP749980A JP749980A JPS56105537A JP S56105537 A JPS56105537 A JP S56105537A JP 749980 A JP749980 A JP 749980A JP 749980 A JP749980 A JP 749980A JP S56105537 A JPS56105537 A JP S56105537A
Authority
JP
Japan
Prior art keywords
data
conversiondata
ram6
converted
controlling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP749980A
Other languages
Japanese (ja)
Inventor
Yasuyuki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP749980A priority Critical patent/JPS56105537A/en
Publication of JPS56105537A publication Critical patent/JPS56105537A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To convert RM data at high speeds by reading out the data to be converted from an RAM by controlling of a direct memory access DMA controller and writing the conversiondata from an ROM into the RAM. CONSTITUTION:When the holding signal 11 of a DMA controller CT2 is inputted to a CPU1, and the answer signal 12 from the CPU1 is inputted to the CT2, the initiative of system control shifts to the CT2. The data to be converted are read out from an RAM6 by controlling of the CT2, and these are held in an input register 5. An ROM4 storing the conversiondata is accessed by the address information of the register 5 and the conversiondata are read out from the ROM4 by the control signal of a control register 3 and are outputted to a data bus 8. The conversion data outputted to the bus 8 are written into the RAM6 by controlling of the CT2 and the data of the RAM6 are converted at high speeds without the intervention of the CPU.
JP749980A 1980-01-25 1980-01-25 Data processing device Pending JPS56105537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP749980A JPS56105537A (en) 1980-01-25 1980-01-25 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP749980A JPS56105537A (en) 1980-01-25 1980-01-25 Data processing device

Publications (1)

Publication Number Publication Date
JPS56105537A true JPS56105537A (en) 1981-08-22

Family

ID=11667464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP749980A Pending JPS56105537A (en) 1980-01-25 1980-01-25 Data processing device

Country Status (1)

Country Link
JP (1) JPS56105537A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59109929A (en) * 1982-12-15 1984-06-25 Nec Corp Input and output controller
JPS59110811A (en) * 1982-12-15 1984-06-26 Toshiba Corp Steam turbine plant

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59109929A (en) * 1982-12-15 1984-06-25 Nec Corp Input and output controller
JPS59110811A (en) * 1982-12-15 1984-06-26 Toshiba Corp Steam turbine plant

Similar Documents

Publication Publication Date Title
JPS5725069A (en) Vector data processing equipment
JPS57138079A (en) Information processor
ES485179A1 (en) Virtual memory computer system.
JPS5786959A (en) Data transfer control system
JPS56105537A (en) Data processing device
JPS55108027A (en) Processor system
JPS56157520A (en) Dma system without cycle steal
JPS5563453A (en) Memory system
JPS57103547A (en) Bit word access circuit
JPS56118165A (en) Processor of video information
JPS55154623A (en) Input and output control system
JPS5622157A (en) Process system multiplexing system
JPS5759222A (en) Dma data transfer system
JPS56105538A (en) Data processing device
JPS57207942A (en) Unpacking circuit
JPS56118164A (en) Processor of video information
JPS57130278A (en) Storage device
JPS6422141A (en) Transmission control system
JPS5578324A (en) Direct memory access system
JPS57211656A (en) Memory device
JPS5563454A (en) Memory system
JPS54128635A (en) Control system for cash memory
JPS5463640A (en) Information processing system
JPS559278A (en) Constitution system of bus line for information processor
JPS5567985A (en) Information processor