JPS57211656A - Memory device - Google Patents

Memory device

Info

Publication number
JPS57211656A
JPS57211656A JP9661781A JP9661781A JPS57211656A JP S57211656 A JPS57211656 A JP S57211656A JP 9661781 A JP9661781 A JP 9661781A JP 9661781 A JP9661781 A JP 9661781A JP S57211656 A JPS57211656 A JP S57211656A
Authority
JP
Japan
Prior art keywords
bus
cpu1
memory
data
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9661781A
Other languages
Japanese (ja)
Inventor
Hiroaki Takechi
Hideji Yamashita
Toshio Kunigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9661781A priority Critical patent/JPS57211656A/en
Publication of JPS57211656A publication Critical patent/JPS57211656A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize a very high-speed and large-capacity memory device, by accessing an extension memory by address data generated by adding contents of a base address pointer and input address data. CONSTITUTION:A basic memory 9 and an extension memory 10 are connected to a data bus 3 connected to a CPU1, and write data from the CPU1 and read data from these memories 9 and 10 are transferred through the bus 3. A memory controlling part 11 is connected to an address bus 2 and the bus 3, and, for example, 16-bit address data inputted from the CPU1 is extended to generate 20-bit address data and is inputted to memories 9 and 10 through a memory address bus 12. Consequently, the bus 2 connected to the CPU1 is used to transfer address data from the CPU1 to the controlling part 11, each input/ output interface 5, etc.
JP9661781A 1981-06-24 1981-06-24 Memory device Pending JPS57211656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9661781A JPS57211656A (en) 1981-06-24 1981-06-24 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9661781A JPS57211656A (en) 1981-06-24 1981-06-24 Memory device

Publications (1)

Publication Number Publication Date
JPS57211656A true JPS57211656A (en) 1982-12-25

Family

ID=14169805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9661781A Pending JPS57211656A (en) 1981-06-24 1981-06-24 Memory device

Country Status (1)

Country Link
JP (1) JPS57211656A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03160543A (en) * 1989-11-13 1991-07-10 Internatl Business Mach Corp <Ibm> Circuit for specifying extended address

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03160543A (en) * 1989-11-13 1991-07-10 Internatl Business Mach Corp <Ibm> Circuit for specifying extended address

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