JPS56118148A - Control system for input and output - Google Patents

Control system for input and output

Info

Publication number
JPS56118148A
JPS56118148A JP2259580A JP2259580A JPS56118148A JP S56118148 A JPS56118148 A JP S56118148A JP 2259580 A JP2259580 A JP 2259580A JP 2259580 A JP2259580 A JP 2259580A JP S56118148 A JPS56118148 A JP S56118148A
Authority
JP
Japan
Prior art keywords
data
output
input
conversion
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2259580A
Other languages
Japanese (ja)
Other versions
JPS6235151B2 (en
Inventor
Hisao Nakajo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2259580A priority Critical patent/JPS56118148A/en
Publication of JPS56118148A publication Critical patent/JPS56118148A/en
Publication of JPS6235151B2 publication Critical patent/JPS6235151B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE:To enable the data conversion at input and output of data, by giving conversion table directly accessible, as to the data conversion with high usage frequency. CONSTITUTION:The output of an output register 101 is fed to I/O via the I/O bus 100, at the output without translation. The input data from the I/O bus 100 is received at an input register 102. The conversion table of data is written in the SPM memory 106 via a buffer 103. At data conversion, the converted data is set to an address register 104, and the conversion data corresponding to this data is read out from a memory 106. The gate 105 constitutes the address circuit to the memory 106.
JP2259580A 1980-02-25 1980-02-25 Control system for input and output Granted JPS56118148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2259580A JPS56118148A (en) 1980-02-25 1980-02-25 Control system for input and output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2259580A JPS56118148A (en) 1980-02-25 1980-02-25 Control system for input and output

Publications (2)

Publication Number Publication Date
JPS56118148A true JPS56118148A (en) 1981-09-17
JPS6235151B2 JPS6235151B2 (en) 1987-07-30

Family

ID=12087187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2259580A Granted JPS56118148A (en) 1980-02-25 1980-02-25 Control system for input and output

Country Status (1)

Country Link
JP (1) JPS56118148A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318452A (en) * 1986-07-10 1988-01-26 Nec Corp Dma controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318452A (en) * 1986-07-10 1988-01-26 Nec Corp Dma controller

Also Published As

Publication number Publication date
JPS6235151B2 (en) 1987-07-30

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