JPS55103663A - Micro computer composite unit - Google Patents

Micro computer composite unit

Info

Publication number
JPS55103663A
JPS55103663A JP1077079A JP1077079A JPS55103663A JP S55103663 A JPS55103663 A JP S55103663A JP 1077079 A JP1077079 A JP 1077079A JP 1077079 A JP1077079 A JP 1077079A JP S55103663 A JPS55103663 A JP S55103663A
Authority
JP
Japan
Prior art keywords
memory
micro computer
outputted
occupation
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1077079A
Other languages
Japanese (ja)
Inventor
Toshiaki Fujie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP1077079A priority Critical patent/JPS55103663A/en
Publication of JPS55103663A publication Critical patent/JPS55103663A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To make generation of an occupying instruction needless by utilizing the input of an address decoder as a memory request signal to occupy the memory provided commonly for plural micro computers.
CONSTITUTION: The address signal outputted when micro computer A requires occupation of memory M is inputted to decoder 11. When micro computer B does not occupy memory M at this time, a high level is outputted from inverter 14 of micro computer A, and a high level is outputted from AND gate 13, and gates 6W8 are opened to transmit and receive data between micro computer A and memory M. When an occupation request of memory M is issued from micro computer B at this time, a high-level queuing signal is issued from AND gate 12 to set central processing unit 1 of micro computer B to a queuing state. Thus, memory M can be occupied without an occupying instruction decoder and an occupation memory.
COPYRIGHT: (C)1980,JPO&Japio
JP1077079A 1979-01-31 1979-01-31 Micro computer composite unit Pending JPS55103663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1077079A JPS55103663A (en) 1979-01-31 1979-01-31 Micro computer composite unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1077079A JPS55103663A (en) 1979-01-31 1979-01-31 Micro computer composite unit

Publications (1)

Publication Number Publication Date
JPS55103663A true JPS55103663A (en) 1980-08-08

Family

ID=11759560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1077079A Pending JPS55103663A (en) 1979-01-31 1979-01-31 Micro computer composite unit

Country Status (1)

Country Link
JP (1) JPS55103663A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178553A (en) * 1981-04-27 1982-11-02 Nec Corp Multiprocessor system
JPS58129565A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device
JPS58129567A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128731A (en) * 1974-09-04 1976-03-11 Tokyo Shibaura Electric Co
JPS5372532A (en) * 1976-12-10 1978-06-28 Hitachi Ltd Access system for memory unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128731A (en) * 1974-09-04 1976-03-11 Tokyo Shibaura Electric Co
JPS5372532A (en) * 1976-12-10 1978-06-28 Hitachi Ltd Access system for memory unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178553A (en) * 1981-04-27 1982-11-02 Nec Corp Multiprocessor system
JPS58129565A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device
JPS58129567A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device

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