JPS54104247A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS54104247A
JPS54104247A JP1092278A JP1092278A JPS54104247A JP S54104247 A JPS54104247 A JP S54104247A JP 1092278 A JP1092278 A JP 1092278A JP 1092278 A JP1092278 A JP 1092278A JP S54104247 A JPS54104247 A JP S54104247A
Authority
JP
Japan
Prior art keywords
module
common
use area
area
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1092278A
Other languages
Japanese (ja)
Inventor
Mitsuo Terajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1092278A priority Critical patent/JPS54104247A/en
Publication of JPS54104247A publication Critical patent/JPS54104247A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the fixed-address area of a main memory by providing a common-use area into the memory of each module.
CONSTITUTION: Modules 2b and 2d, equipped with a priority logic circuit, receive and transmit data via bus 1 mutually. Then, respective memories 4 are incorporated in each module and contents of each module are written into common-use area 4a. This common-use area 4a is for transmission and reception of data to and from any other module via bus 1. In addition, each module is able to give a register reference instruction to common-use area 4a of any other module and also to read out data from module 2d reversely by setting results to common-use area 4a at the time of an insterruption from module 2d. Providing the common-use area like this eliminates the need of the conventional fixed-address area of the main memory.
COPYRIGHT: (C)1979,JPO&Japio
JP1092278A 1978-02-02 1978-02-02 Information processing system Pending JPS54104247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1092278A JPS54104247A (en) 1978-02-02 1978-02-02 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1092278A JPS54104247A (en) 1978-02-02 1978-02-02 Information processing system

Publications (1)

Publication Number Publication Date
JPS54104247A true JPS54104247A (en) 1979-08-16

Family

ID=11763726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1092278A Pending JPS54104247A (en) 1978-02-02 1978-02-02 Information processing system

Country Status (1)

Country Link
JP (1) JPS54104247A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603773A (en) * 1983-06-22 1985-01-10 Fuji Electric Co Ltd Information processing system
JPH01287768A (en) * 1988-05-13 1989-11-20 Fujitsu Ltd Multiprocessor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603773A (en) * 1983-06-22 1985-01-10 Fuji Electric Co Ltd Information processing system
JPH01287768A (en) * 1988-05-13 1989-11-20 Fujitsu Ltd Multiprocessor system

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