JPS55147745A - Data transfer unit between memory units - Google Patents

Data transfer unit between memory units

Info

Publication number
JPS55147745A
JPS55147745A JP5543479A JP5543479A JPS55147745A JP S55147745 A JPS55147745 A JP S55147745A JP 5543479 A JP5543479 A JP 5543479A JP 5543479 A JP5543479 A JP 5543479A JP S55147745 A JPS55147745 A JP S55147745A
Authority
JP
Japan
Prior art keywords
unit
register
address
data
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5543479A
Other languages
Japanese (ja)
Inventor
Takumi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5543479A priority Critical patent/JPS55147745A/en
Publication of JPS55147745A publication Critical patent/JPS55147745A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To send the information quickly in independent transfer mode, by performing the address write-in and data read-out from the processing unit to the memory unit by the first transmission systems, and performing them from the processor to the memory unit with the second transmission system.
CONSTITUTION: The transmission system 31 transmits the address information representing the write-in address from the address register 21 of the processor 2 to the address register 11 of the unit 31 when the address information is written in the memory unit 1. Further, the write-in data is fed to the write-in data register 13 of the unit 1 from the write-in data register 23 of the unit 2 via the transmission system 32. On the other hand, when the data is read out from the unit 1, after the address information representing the read-out address is fed from the register 12 of the unit 1 to the register 22 of the unit 2, the read-out data is transmitted from the register 12 of the unit 1 to the register 22 of the unit 2 via the transmission system 31. Thus, the transmission system is not expanded between the units 1 and 2, allowing to transfer the information quickly in the independent transfer mode.
COPYRIGHT: (C)1980,JPO&Japio
JP5543479A 1979-05-07 1979-05-07 Data transfer unit between memory units Pending JPS55147745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5543479A JPS55147745A (en) 1979-05-07 1979-05-07 Data transfer unit between memory units

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5543479A JPS55147745A (en) 1979-05-07 1979-05-07 Data transfer unit between memory units

Publications (1)

Publication Number Publication Date
JPS55147745A true JPS55147745A (en) 1980-11-17

Family

ID=12998476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5543479A Pending JPS55147745A (en) 1979-05-07 1979-05-07 Data transfer unit between memory units

Country Status (1)

Country Link
JP (1) JPS55147745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6352245A (en) * 1986-08-21 1988-03-05 Ascii Corp Memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6352245A (en) * 1986-08-21 1988-03-05 Ascii Corp Memory device

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