JPS56118133A - Direct memory access circuit - Google Patents

Direct memory access circuit

Info

Publication number
JPS56118133A
JPS56118133A JP2252680A JP2252680A JPS56118133A JP S56118133 A JPS56118133 A JP S56118133A JP 2252680 A JP2252680 A JP 2252680A JP 2252680 A JP2252680 A JP 2252680A JP S56118133 A JPS56118133 A JP S56118133A
Authority
JP
Japan
Prior art keywords
transmission
circuit
reception section
address
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2252680A
Other languages
Japanese (ja)
Inventor
Etsuo Masuda
Hideou Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2252680A priority Critical patent/JPS56118133A/en
Publication of JPS56118133A publication Critical patent/JPS56118133A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To realize the DMA circuit which makes high speed transfer through the use of address correction circuit based on the location information and size information assigned to the transmission and reception section, in the data processor providing a plurality of transmission and reception sections of a plurality in different speed. CONSTITUTION:In making the data transfer between the buffer memory 3 and the transmission/reception section 4 with DMA transfer, the location information on the buffer memory 3 of the buffer area assigned to the transmission/reception section 4 via the signal line 11 from the control section 2 is set to the register 6 and the size information of the buffer area is to the register 7 and the location information of the buffer area making data transfer is set to the address register 8. Next, when a starting signal is fed from the signal line 25, the access request is outputted to the request circuit 5 from the transmission reception section 4, and the bus occupancy request is given from the circuit 5 to the control section 2, and when ACK signal is returned, thed address corrrection circuit 10 is operated, and data transfer is made between the buffer memory 3 and the transmission/reception section 4 while being address correction based on the information of the registers 6, 7, 8.
JP2252680A 1980-02-25 1980-02-25 Direct memory access circuit Pending JPS56118133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2252680A JPS56118133A (en) 1980-02-25 1980-02-25 Direct memory access circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2252680A JPS56118133A (en) 1980-02-25 1980-02-25 Direct memory access circuit

Publications (1)

Publication Number Publication Date
JPS56118133A true JPS56118133A (en) 1981-09-17

Family

ID=12085225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2252680A Pending JPS56118133A (en) 1980-02-25 1980-02-25 Direct memory access circuit

Country Status (1)

Country Link
JP (1) JPS56118133A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193230A (en) * 1985-02-20 1986-08-27 Hitachi Ltd Magnetic disk controller
JPS6448158A (en) * 1987-08-19 1989-02-22 Oki Electric Ind Co Ltd Direct memory access control circuit
JPH0276053A (en) * 1988-09-13 1990-03-15 Fujitsu Ltd Dma transfer control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193230A (en) * 1985-02-20 1986-08-27 Hitachi Ltd Magnetic disk controller
JPS6448158A (en) * 1987-08-19 1989-02-22 Oki Electric Ind Co Ltd Direct memory access control circuit
JPH0276053A (en) * 1988-09-13 1990-03-15 Fujitsu Ltd Dma transfer control circuit

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