JPS5478635A - Data transfer control circuit - Google Patents

Data transfer control circuit

Info

Publication number
JPS5478635A
JPS5478635A JP14572277A JP14572277A JPS5478635A JP S5478635 A JPS5478635 A JP S5478635A JP 14572277 A JP14572277 A JP 14572277A JP 14572277 A JP14572277 A JP 14572277A JP S5478635 A JPS5478635 A JP S5478635A
Authority
JP
Japan
Prior art keywords
data
control circuit
register
control
cpu22
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14572277A
Other languages
Japanese (ja)
Inventor
Tsuneki Mori
Hideo Asano
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14572277A priority Critical patent/JPS5478635A/en
Publication of JPS5478635A publication Critical patent/JPS5478635A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To give control to the input/output device which is not set previously by the specifications without havng any program alteration, by providing the simple- structure additional circuits to the LSI-formed data tranfer control circuit.
CONSTITUTION: The data process system comprises CPU22, data transfer control circuit 21 and input/output device 26. Then command register 24 to store part of the command given from CPU22 is installed to the data process system, along with control circuit 25 to control device 26 by the contents of register 24. Furthermore, the following units are provided: control FF27 and 28; register 29 to store the lower bits of the read-out data; status register 23; FF30 to produce the busy signal within the status; and buffer circuit 36 to take in the data at all times and to deliver the data only when AND gate 34 is in logic 1. With these additional circuits, the signals to indicate the state of circuit 21 and device 26 plus the signal to indicate the writing or the data request sent from CPU22 are produced to control device 26.
COPYRIGHT: (C)1979,JPO&Japio
JP14572277A 1977-12-06 1977-12-06 Data transfer control circuit Pending JPS5478635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14572277A JPS5478635A (en) 1977-12-06 1977-12-06 Data transfer control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14572277A JPS5478635A (en) 1977-12-06 1977-12-06 Data transfer control circuit

Publications (1)

Publication Number Publication Date
JPS5478635A true JPS5478635A (en) 1979-06-22

Family

ID=15391608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14572277A Pending JPS5478635A (en) 1977-12-06 1977-12-06 Data transfer control circuit

Country Status (1)

Country Link
JP (1) JPS5478635A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123032A (en) * 1982-12-29 1984-07-16 Fujitsu Ltd Input and output control system
JPS6226561A (en) * 1985-07-26 1987-02-04 Toshiba Corp Personal computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123032A (en) * 1982-12-29 1984-07-16 Fujitsu Ltd Input and output control system
JPS6226561A (en) * 1985-07-26 1987-02-04 Toshiba Corp Personal computer

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