JPS5669931A - Tristate buffer circuit - Google Patents

Tristate buffer circuit

Info

Publication number
JPS5669931A
JPS5669931A JP14572279A JP14572279A JPS5669931A JP S5669931 A JPS5669931 A JP S5669931A JP 14572279 A JP14572279 A JP 14572279A JP 14572279 A JP14572279 A JP 14572279A JP S5669931 A JPS5669931 A JP S5669931A
Authority
JP
Japan
Prior art keywords
circuit
potential
output
tristate buffer
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14572279A
Other languages
Japanese (ja)
Inventor
Masayuki Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14572279A priority Critical patent/JPS5669931A/en
Publication of JPS5669931A publication Critical patent/JPS5669931A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To enable more rapid signal transmission than a normal tristate buffer circuit by tens %, by outputting an input signal by way of one gate circuit and one transistor. CONSTITUTION:When a data input control signal is at potential L and synchronizing signal CL at potential H, clock pulse phi is at potential H, NAND circuit 11 and NOR circuit 12 are ready to operate, and inverter circuits 19 and 21 are disabled to operate. At this time, if input data D is at potential L, the output of circuit 11 is held at potential H to turn off MOS trnansistor TR16 and the output of circuit 12 is at potential H to turn on MOSTR17, so that output OUT15 will be at potential L. Those signals DA, CL and D are combined and input D passes through one gote and one TR, which are equivalent to circuit 11 and TR16 or circuit 12 and TR17, to obtain output OUT, so that the signal transmission can be made faster than a normal tristate buffer circuit by tens %.
JP14572279A 1979-11-10 1979-11-10 Tristate buffer circuit Pending JPS5669931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14572279A JPS5669931A (en) 1979-11-10 1979-11-10 Tristate buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14572279A JPS5669931A (en) 1979-11-10 1979-11-10 Tristate buffer circuit

Publications (1)

Publication Number Publication Date
JPS5669931A true JPS5669931A (en) 1981-06-11

Family

ID=15391610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14572279A Pending JPS5669931A (en) 1979-11-10 1979-11-10 Tristate buffer circuit

Country Status (1)

Country Link
JP (1) JPS5669931A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200326A (en) * 1983-04-26 1984-11-13 Nec Corp Data processing system
JPS62277692A (en) * 1986-05-27 1987-12-02 Fujitsu Ltd Output buffer circuit for semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200326A (en) * 1983-04-26 1984-11-13 Nec Corp Data processing system
JPH0157378B2 (en) * 1983-04-26 1989-12-05 Nippon Electric Co
JPS62277692A (en) * 1986-05-27 1987-12-02 Fujitsu Ltd Output buffer circuit for semiconductor memory device

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