JPS6442720A - Clock generating circuit - Google Patents
Clock generating circuitInfo
- Publication number
- JPS6442720A JPS6442720A JP62200187A JP20018787A JPS6442720A JP S6442720 A JPS6442720 A JP S6442720A JP 62200187 A JP62200187 A JP 62200187A JP 20018787 A JP20018787 A JP 20018787A JP S6442720 A JPS6442720 A JP S6442720A
- Authority
- JP
- Japan
- Prior art keywords
- nand gate
- circuit
- input
- becomes
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To contrive the reduction of the number of transistors by providing a first NAND gate circuit in which a single phase clock becomes a first input and the output of a second NAND gate circuit becomes a second input, and a second NAND gate circuit in which the output of a first inverter circuit becomes a first input and the output of a first NAND circuit becomes the second input. CONSTITUTION:The titled circuit contains NAND gate circuits 1, 2 of two inputs and inverter circuits 3, 4 and 5. These NAND gate circuits 1, 2 are not a complete CMOS constitution, but constituted as a pseudo NAND gate circuit. The NAND gate circuit 1 is constituted so that a single phase clock becomes the first input, and the output of the NAND gate circuit 2 becomes the second input, and the NAND gate circuit 2 is constituted so that an output of the inverter circuit 5 becomes the first input, and an output of the NAND gate circuit 1 becomes the second input. This clock generating circuit does not necessitate an inverter circuit for delaying a signal, and accordingly, the number of transistors can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62200187A JPS6442720A (en) | 1987-08-10 | 1987-08-10 | Clock generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62200187A JPS6442720A (en) | 1987-08-10 | 1987-08-10 | Clock generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6442720A true JPS6442720A (en) | 1989-02-15 |
Family
ID=16420242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62200187A Pending JPS6442720A (en) | 1987-08-10 | 1987-08-10 | Clock generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6442720A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04162292A (en) * | 1990-10-25 | 1992-06-05 | Nec Ic Microcomput Syst Ltd | Semiconductor memory |
JPH0526100U (en) * | 1991-09-13 | 1993-04-06 | 吉村精機株式会社 | Clothes wrinkle remover |
JP2006245828A (en) * | 2005-03-01 | 2006-09-14 | Nec Electronics Corp | Low amplitude differential output circuit and serial transmission interface |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53121556A (en) * | 1977-03-31 | 1978-10-24 | Toshiba Corp | 2-phase clock pulse generator circuit |
-
1987
- 1987-08-10 JP JP62200187A patent/JPS6442720A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53121556A (en) * | 1977-03-31 | 1978-10-24 | Toshiba Corp | 2-phase clock pulse generator circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04162292A (en) * | 1990-10-25 | 1992-06-05 | Nec Ic Microcomput Syst Ltd | Semiconductor memory |
JPH0526100U (en) * | 1991-09-13 | 1993-04-06 | 吉村精機株式会社 | Clothes wrinkle remover |
JP2006245828A (en) * | 2005-03-01 | 2006-09-14 | Nec Electronics Corp | Low amplitude differential output circuit and serial transmission interface |
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