FR2433263A1 - Control circuit for flip=flop - has inverter with two NOR circuits, OR circuits and flip=flop using time signal (BE 8.2.80) - Google Patents
Control circuit for flip=flop - has inverter with two NOR circuits, OR circuits and flip=flop using time signal (BE 8.2.80)Info
- Publication number
- FR2433263A1 FR2433263A1 FR7919673A FR7919673A FR2433263A1 FR 2433263 A1 FR2433263 A1 FR 2433263A1 FR 7919673 A FR7919673 A FR 7919673A FR 7919673 A FR7919673 A FR 7919673A FR 2433263 A1 FR2433263 A1 FR 2433263A1
- Authority
- FR
- France
- Prior art keywords
- flip
- flop
- circuits
- inverter
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
Landscapes
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Abstract
The flip-flop derives from its input basic timing signal a clock signal applied to the timing input of a following component tripping it. The basic timing signal (T) is applied to the input of an inverter (1) and also to one of two inputs of a first NOR gate. (3). The inverter (1) output is connected to an input of a second NOR gate (2). The other inputs of the two NOR gates (2, 3) are connected to the direct (Q) and inverted (Q) outputs of the flip-flop (4) respectively. The outputs of the NOR gates (2, 3) are connected to the inputs of an Or gate (5) whose output applies the clock signal (T') to the flip-flop timing input.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19782834798 DE2834798C3 (en) | 1978-08-09 | 1978-08-09 | Circuit arrangement for controlling single-edge-controlled components |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2433263A1 true FR2433263A1 (en) | 1980-03-07 |
Family
ID=6046537
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7919673A Withdrawn FR2433263A1 (en) | 1978-08-09 | 1979-07-31 | Control circuit for flip=flop - has inverter with two NOR circuits, OR circuits and flip=flop using time signal (BE 8.2.80) |
Country Status (3)
Country | Link |
---|---|
BE (1) | BE878141A (en) |
DE (1) | DE2834798C3 (en) |
FR (1) | FR2433263A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0330971A2 (en) * | 1988-02-29 | 1989-09-06 | Oki Electric Industry Company, Limited | Flip-flop circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3171037A (en) * | 1960-01-11 | 1965-02-23 | Wolfgang J Poppelbaum | Semiconductor bistable circuit with integral gate |
US4041403A (en) * | 1975-07-28 | 1977-08-09 | Bell Telephone Laboratories, Incorporated | Divide-by-N/2 frequency division arrangement |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5040656B2 (en) * | 1971-11-12 | 1975-12-25 |
-
1978
- 1978-08-09 DE DE19782834798 patent/DE2834798C3/en not_active Expired
-
1979
- 1979-07-31 FR FR7919673A patent/FR2433263A1/en not_active Withdrawn
- 1979-08-08 BE BE2/58004A patent/BE878141A/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3171037A (en) * | 1960-01-11 | 1965-02-23 | Wolfgang J Poppelbaum | Semiconductor bistable circuit with integral gate |
US4041403A (en) * | 1975-07-28 | 1977-08-09 | Bell Telephone Laboratories, Incorporated | Divide-by-N/2 frequency division arrangement |
Non-Patent Citations (2)
Title |
---|
EXBK/72 * |
EXBK/77 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0330971A2 (en) * | 1988-02-29 | 1989-09-06 | Oki Electric Industry Company, Limited | Flip-flop circuit |
EP0330971A3 (en) * | 1988-02-29 | 1991-04-24 | Oki Electric Industry Company, Limited | Flip-flop circuit |
Also Published As
Publication number | Publication date |
---|---|
DE2834798B2 (en) | 1980-09-18 |
BE878141A (en) | 1980-02-08 |
DE2834798C3 (en) | 1981-07-16 |
DE2834798A1 (en) | 1980-02-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |