JPS57112129A - Latch circuit - Google Patents

Latch circuit

Info

Publication number
JPS57112129A
JPS57112129A JP55188596A JP18859680A JPS57112129A JP S57112129 A JPS57112129 A JP S57112129A JP 55188596 A JP55188596 A JP 55188596A JP 18859680 A JP18859680 A JP 18859680A JP S57112129 A JPS57112129 A JP S57112129A
Authority
JP
Japan
Prior art keywords
signal
input signal
latch
gate
delayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188596A
Other languages
Japanese (ja)
Inventor
Yuji Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP55188596A priority Critical patent/JPS57112129A/en
Publication of JPS57112129A publication Critical patent/JPS57112129A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Abstract

PURPOSE:To detect the extiction of an input signal after generation, by operating AND between the input signal and a signal, which is obtained by delaying and inverting the input signal, and by setting a latch by the AND signal. CONSTITUTION:When an input signal S becomes low, this signal is delayed by a delay circuit 1 and is inverted by an inverter 3 to supply a high signal delayed by a constant time to an AND gate 2. If the input signal S becomes high at this time, a signal is outputted to the AND gate 2 to set a latch 4. That is, the latch 4 is not set unless the input signal S becomes high again after becoming low temporarily.
JP55188596A 1980-12-27 1980-12-27 Latch circuit Pending JPS57112129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188596A JPS57112129A (en) 1980-12-27 1980-12-27 Latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188596A JPS57112129A (en) 1980-12-27 1980-12-27 Latch circuit

Publications (1)

Publication Number Publication Date
JPS57112129A true JPS57112129A (en) 1982-07-13

Family

ID=16226418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188596A Pending JPS57112129A (en) 1980-12-27 1980-12-27 Latch circuit

Country Status (1)

Country Link
JP (1) JPS57112129A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63132522A (en) * 1986-11-25 1988-06-04 Toshiba Corp Semiconductor integrated circuit
JPS63132521A (en) * 1986-11-25 1988-06-04 Toshiba Corp Semiconductor integrated circuit
JPH0326104A (en) * 1989-06-09 1991-02-04 Digital Equip Corp <Dec> Correlation sliver latch

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4948269A (en) * 1972-09-14 1974-05-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4948269A (en) * 1972-09-14 1974-05-10

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63132522A (en) * 1986-11-25 1988-06-04 Toshiba Corp Semiconductor integrated circuit
JPS63132521A (en) * 1986-11-25 1988-06-04 Toshiba Corp Semiconductor integrated circuit
JPH0326104A (en) * 1989-06-09 1991-02-04 Digital Equip Corp <Dec> Correlation sliver latch

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