JPS5679524A - Conversion circuit for duty cycle - Google Patents

Conversion circuit for duty cycle

Info

Publication number
JPS5679524A
JPS5679524A JP15938979A JP15938979A JPS5679524A JP S5679524 A JPS5679524 A JP S5679524A JP 15938979 A JP15938979 A JP 15938979A JP 15938979 A JP15938979 A JP 15938979A JP S5679524 A JPS5679524 A JP S5679524A
Authority
JP
Japan
Prior art keywords
signal
duty cycle
conversion circuit
hand
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15938979A
Other languages
Japanese (ja)
Inventor
Hideo Shiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15938979A priority Critical patent/JPS5679524A/en
Publication of JPS5679524A publication Critical patent/JPS5679524A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

Abstract

PURPOSE:To form the signal with an arbitrary duty cycle simply, by adding the original signal to one input of an exclusive logical sum and the signal delaying the original signal to another input. CONSTITUTION:An incoming clock pulse (a) is frequency-divided at a 1/2 frequency divider 1 to be the signal with duty 50%. This signal is fed, on one hand to an exclusive logic 3 as it is and on the other hand, via a delay line 2 to the logic 3. When the delay time of the delay line 2 is taken a half the period of the incoming clock pulse (a), the signal with 50% duty cycle can be obtained from the exclusive logical sum 3.
JP15938979A 1979-12-03 1979-12-03 Conversion circuit for duty cycle Pending JPS5679524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15938979A JPS5679524A (en) 1979-12-03 1979-12-03 Conversion circuit for duty cycle

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15938979A JPS5679524A (en) 1979-12-03 1979-12-03 Conversion circuit for duty cycle

Publications (1)

Publication Number Publication Date
JPS5679524A true JPS5679524A (en) 1981-06-30

Family

ID=15692711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15938979A Pending JPS5679524A (en) 1979-12-03 1979-12-03 Conversion circuit for duty cycle

Country Status (1)

Country Link
JP (1) JPS5679524A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594317A (en) * 1982-06-30 1984-01-11 Toshiba Corp Pulse generating circuit
JPH04365219A (en) * 1991-06-13 1992-12-17 Nec Ic Microcomput Syst Ltd Clock pulse shaping circuit
JPH0675907A (en) * 1992-06-01 1994-03-18 Internatl Business Mach Corp <Ibm> Data transmission system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594317A (en) * 1982-06-30 1984-01-11 Toshiba Corp Pulse generating circuit
JPH04365219A (en) * 1991-06-13 1992-12-17 Nec Ic Microcomput Syst Ltd Clock pulse shaping circuit
JPH0675907A (en) * 1992-06-01 1994-03-18 Internatl Business Mach Corp <Ibm> Data transmission system

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