JPS5227250A - Oscillating circuit - Google Patents

Oscillating circuit

Info

Publication number
JPS5227250A
JPS5227250A JP50102723A JP10272375A JPS5227250A JP S5227250 A JPS5227250 A JP S5227250A JP 50102723 A JP50102723 A JP 50102723A JP 10272375 A JP10272375 A JP 10272375A JP S5227250 A JPS5227250 A JP S5227250A
Authority
JP
Japan
Prior art keywords
terminal
output
counter
flipflop
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50102723A
Other languages
Japanese (ja)
Inventor
Kunihiro Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Aerojet Rocketdyne Holdings Inc
Original Assignee
Fujitsu General Ltd
Gencorp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gencorp Inc filed Critical Fujitsu General Ltd
Priority to JP50102723A priority Critical patent/JPS5227250A/en
Publication of JPS5227250A publication Critical patent/JPS5227250A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: Clock pulse C is always input at one input terminal of counter 1. The counter 1 generates output when it counts clock pulse C, and decoder 2, two outputs d, e, at appropriate time receiving output of the counter 1. One output terminal M1 of decoder 2 is connected to set terminal of flipflop 3, and the other output terminal N1, to reset terminal of flipflop 3 and reset terminal of counter 1. Set pulse d to flipflop 3 is output from terminal M1 of decoder 2, and reset pulse e, from terminal N1. Contents of counter 1 are returned to 0 by reset pulse 3. Thus, period T and duty of output f of flipflop 3 can be set differently by changing output of decoder 2.
COPYRIGHT: (C)1977,JPO&Japio
JP50102723A 1975-08-25 1975-08-25 Oscillating circuit Pending JPS5227250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50102723A JPS5227250A (en) 1975-08-25 1975-08-25 Oscillating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50102723A JPS5227250A (en) 1975-08-25 1975-08-25 Oscillating circuit

Publications (1)

Publication Number Publication Date
JPS5227250A true JPS5227250A (en) 1977-03-01

Family

ID=14335176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50102723A Pending JPS5227250A (en) 1975-08-25 1975-08-25 Oscillating circuit

Country Status (1)

Country Link
JP (1) JPS5227250A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5466060A (en) * 1977-11-04 1979-05-28 Sanyo Electric Co Ltd Pulse generating circuit
JPS54174360U (en) * 1978-05-29 1979-12-08
JPH06228828A (en) * 1993-01-29 1994-08-16 Kanai Hiroyuki Method for continuously mixing small lot of fiber raw material

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5466060A (en) * 1977-11-04 1979-05-28 Sanyo Electric Co Ltd Pulse generating circuit
JPS54174360U (en) * 1978-05-29 1979-12-08
JPH06228828A (en) * 1993-01-29 1994-08-16 Kanai Hiroyuki Method for continuously mixing small lot of fiber raw material

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