JPS57208723A - Double-multiplication circuit - Google Patents

Double-multiplication circuit

Info

Publication number
JPS57208723A
JPS57208723A JP9431181A JP9431181A JPS57208723A JP S57208723 A JPS57208723 A JP S57208723A JP 9431181 A JP9431181 A JP 9431181A JP 9431181 A JP9431181 A JP 9431181A JP S57208723 A JPS57208723 A JP S57208723A
Authority
JP
Japan
Prior art keywords
logical sum
exclusive logical
output
double
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9431181A
Other languages
Japanese (ja)
Inventor
Masayuki Yoshizawa
Koji Ishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP9431181A priority Critical patent/JPS57208723A/en
Publication of JPS57208723A publication Critical patent/JPS57208723A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a stable circuit without being affected with temperature, by regarding an output of exclusive logical sum to which an input signal is applied, as another input to the exclusive logical sum via a 1/2-frequency divider. CONSTITUTION:An input signal phif is applied to one input of an exclusive logical sum 12, the output is applied to an external element 18 and a (1/2) frequency divider 19. The output of the divider 19 has the same frequency as that of the input signal phif, is delayed at inverters 21 and 22 and becomes another input to an exclusive logical sum 12. The pulse width of a double-multiplication wave applied to the external element 18 is almost equal to the operation delay time of the exclusive logical sum 12, a frequency divider 20 and inverters 21 and 22.
JP9431181A 1981-06-18 1981-06-18 Double-multiplication circuit Pending JPS57208723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9431181A JPS57208723A (en) 1981-06-18 1981-06-18 Double-multiplication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9431181A JPS57208723A (en) 1981-06-18 1981-06-18 Double-multiplication circuit

Publications (1)

Publication Number Publication Date
JPS57208723A true JPS57208723A (en) 1982-12-21

Family

ID=14106726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9431181A Pending JPS57208723A (en) 1981-06-18 1981-06-18 Double-multiplication circuit

Country Status (1)

Country Link
JP (1) JPS57208723A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223319A (en) * 1984-02-29 1985-11-07 アメリカン　マイクロシステムズ，インコ−ポレイテツド Frequency doubler having 50percent duty cycle output signal

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN=1974 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223319A (en) * 1984-02-29 1985-11-07 アメリカン　マイクロシステムズ，インコ−ポレイテツド Frequency doubler having 50percent duty cycle output signal

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