JPS57135526A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To securely remove unnecessary pulses which appear in a frequency division output, by empolying connected stages of frequency dividers, a delay circuit which generates an output by delaying the output phase of an initial- stage frequency divider by 90 deg., and a gate circuit. CONSTITUTION:A frequency dividing circuit is provided with frequency dividers 31-3N connected in series, and a delay circuit 40 which generates an output by delaying the output phase of the initial-stage frequency divider 31 by 90 deg.; the output of the circuit 40 and the outputs of the frequency dividers 32-3N are inputted to an AND circuit 42. The circuit 40 uses a D-FF44 and while an input signal common to the frequency divider 31 is inverted by an inverter 48 and inputted to the terminal T of the FF44, the output of the frequency divider 31 is supplied to the terminal D. Therefore, the output of the FF44 is ANDed with the outputs of the frequency dividers 32-3N to open the gate 42, so that a frequency division output appears at an output terminal 50. Consequently, the generation of unnecessary pulses due to the propagation delay time of a circuit element is eliminated securely within the range where the delay time of the frequency divider 3N is shorter than the delay time due to a 90 deg. phase difference.