JPS5755628A - Phase comparing circuit and frequency synthesizer using it - Google Patents

Phase comparing circuit and frequency synthesizer using it

Info

Publication number
JPS5755628A
JPS5755628A JP55130723A JP13072380A JPS5755628A JP S5755628 A JPS5755628 A JP S5755628A JP 55130723 A JP55130723 A JP 55130723A JP 13072380 A JP13072380 A JP 13072380A JP S5755628 A JPS5755628 A JP S5755628A
Authority
JP
Japan
Prior art keywords
circuit
exclusive
comparing circuit
input
phase comparing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55130723A
Other languages
Japanese (ja)
Inventor
Toshito Habuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55130723A priority Critical patent/JPS5755628A/en
Publication of JPS5755628A publication Critical patent/JPS5755628A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To simplify a phase comparing circuit by providing either input of an exclusive OR circuit with a frequency divider for obtaining a frequency division output pulse synchronizing with the pulse edge of either input of the exclusive OR circuit. CONSTITUTION:To the inputs of an exclusive OR circuit, T type flip-flop circuits F1 and F2 are connected, respectively. The input terminals T of those T type flip- flops F1 and F2 are connected to the input terminals IN1 and IN2 of a comparing circuit, and their output terminals Q are connected to the input terminals of the exclusive OR circuit EX, whose output is further connected to a terminal OUT. Consequently, pulses obtained through the frequency division of the F1 and F2 are inputted to the inputs of the EX and at the terminal OUT of the EX, a signal appears which corresponds to a phase difference between the F1 and F2.
JP55130723A 1980-09-22 1980-09-22 Phase comparing circuit and frequency synthesizer using it Pending JPS5755628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55130723A JPS5755628A (en) 1980-09-22 1980-09-22 Phase comparing circuit and frequency synthesizer using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55130723A JPS5755628A (en) 1980-09-22 1980-09-22 Phase comparing circuit and frequency synthesizer using it

Publications (1)

Publication Number Publication Date
JPS5755628A true JPS5755628A (en) 1982-04-02

Family

ID=15041083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55130723A Pending JPS5755628A (en) 1980-09-22 1980-09-22 Phase comparing circuit and frequency synthesizer using it

Country Status (1)

Country Link
JP (1) JPS5755628A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0148525A2 (en) * 1983-12-23 1985-07-17 ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI s.p.a. Digital phase locked loop (DPLL)
JPS63309024A (en) * 1987-04-17 1988-12-16 サントル・ナシオナル・デチュド・スパシアル Time standard apparatus with substantially constant stability for short term and long term time measurement
JPH01268221A (en) * 1988-04-19 1989-10-25 Matsushita Electric Ind Co Ltd Phase comparator
JPH09171471A (en) * 1995-12-21 1997-06-30 Kofu Nippon Denki Kk Inter-lsi asynchronous data transfer circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0148525A2 (en) * 1983-12-23 1985-07-17 ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI s.p.a. Digital phase locked loop (DPLL)
JPS63309024A (en) * 1987-04-17 1988-12-16 サントル・ナシオナル・デチュド・スパシアル Time standard apparatus with substantially constant stability for short term and long term time measurement
JPH01268221A (en) * 1988-04-19 1989-10-25 Matsushita Electric Ind Co Ltd Phase comparator
JPH09171471A (en) * 1995-12-21 1997-06-30 Kofu Nippon Denki Kk Inter-lsi asynchronous data transfer circuit

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