SU780154A1 - Zero beating discriminator - Google Patents

Description

(54) DISCRIMINATOR OF ZERO BEATS The invention relates to radio engineering and can be used in automatic frequency detection devices, in particular, in the following Doppler frequency measuring devices. : Known discriminator of zero beats, in-phase and quadrature channels with a mixer connected in series, a low-pass filter and an amplifier-limiter, as well as a tunable generator and control unit tl common to both channels. However, the known discriminator has a relatively low accuracy and limited dynamic range. the invention is to improve the accuracy and widening the dynamic range of input signals. For this, a zero-beat discriminator containing in-phase and quadrature channels. With a mixer, a low-pass filter and an amplifier-limiter, included in each channel, and a tunable generator and 6L of control channels common to both channels. a shift register, two matching elements and an RS flip-flop are introduced, as well as a delay unit and a frequency divider common to both channels, the information inputs of the shift registers a being connected to the outputs of limiter amplifiers: direct and inverse Each output of the shift register is connected respectively to the inputs of the first and second coincidence elements, the outputs of which are connected to the RS-Trigger inputs, and the outputs of the RS-flip-flops of each channel are connected to the inputs of the control unit, the outputs of which are connected to the inputs of the tunable generator, while the output tunable oscillator is connected via a delay unit to the inputs of the matching elements and connected directly to the synchronization inputs of the shift registers and to the input of a frequency divider, the output of which is connected to the mix by a common-mode channel and a phase-gap channel phase shifter. The drawing shows a structural electrical circuit of the proposed discriminator. The zero beat discriminator contains an in-phase channel, which includes mixer 1, low-pass filter 2, limiter-amplifier 3, shift register 4, elements 5, 6, match, and RS-flip-flop 7, quadrature channel.

including a mixer 8, a lower filter 9 often, a limiting amplifier 10, a shift register 11, co-ownership elements 12, 13 and an RS flip-flop 14, as well as a phase shifter 15, a control block 16, a tunable oscillator, 17, a frequency divider 18 and a delay block 19 .

The discriminator works as follows.

The input signal is converted by mixers 1, 8 into a zero beat signal. Due to the fact that the heterodyne signal from divider 18 is fed to the mixtures. 1, the mixer 1 is transmitted through the phase shifter 15, to the mixer 8. the zero beat signal at the outputs of mixers 1, 8, as well as at the outputs of filters 2, .9, are mutually shifted by iSO- depending on the sign of the difference between the frequencies of the input signal and the heterodyne signal coming from the output of divider 18,,,.

Further, zero beat signals are extremely limited by amplifier limiters 3, 10 and simultaneously converted by level, for example, in such a way that the positive polarity at the inputs of limiter amplifiers 3, 10 corresponds to the level of a logical unit at their outputs, and negative - the level of logical zero

if the zero beat signal is greater than the other components, the second ones also take place at the inputs of limiters 3, 10 due to imperfect operation of mixers 1, 8, filters 2, 9 and interference, and if the limit is symmetrical, then the output signal of the amplifiers - limiters 3, 10 has the form of a meander (in the form of alternating levels of logical units and zero),

The occurrence of a level of logical units on; the output of the amplifier-limiter 3 is fixed with a delay Tj the appearance of a pulse at the output of element 5, whose inputs are connected to the direct outputs of register 4. The delay is directly proportional to the size of the register 4th pulse repetition period at the input of the synchronization register 4. The appearance of a logic zero at the output of the amplifier-limiter 3 is fixed with the same delay by the appearance of a pulse at the output of element 6j whose inputs are connected to the inverse output of register 4. To eliminate the possibility of the operation of elements 5, b at time c The information on the register 4 is exchanged, to the inputs of the elements 5, b, a signal is sent to the block 19, which shifts the output signal relative to the input signal by a time longer than the time for changing information on the register 4.

Elements 5 and b control the operation of the RS flip-flop 7. The output signal of the RS flip-flop 7 with a delay tj repeat 780154

The signal is output from the amplifier of limiter 3. The quadrature channel works in a similar way. The same delay in the channels does not change the mutual phase relation between the oscillations at the outputs of the RS flip-flops 7, 14, i.e. does not affect the accuracy of the discriminator.

If the zero beat signal is small enough, the effect of unwanted components at the input of the limiting amplifiers 3, 10 increases. For the most part, their frequency is much higher than the frequency of the zero beat components. The presence of undesirable constituents is manifested in the fact that the change of levels does not occur once, but by repeated alternation with a higher frequency.

If the frequency of the synchronization signal of registers 4, 11 is chosen to be no less than twice the frequency of the highest-frequency component at their information inputs, then the alternation of levels at the inputs of registers 4, 11 will cause progressing along them alternating levels of ones and zeros, eliminates the possibility of triggering elements 5, 6, 12, 13. The condition for triggering elements 5, 12 is the presence of all direct outputs of registers 4, 11 levels of units. Similarly, the condition for triggering the elements b, 13 is the presence of a level of units at all inverse outputs of registers 4, 11. This is equivalent to maintaining at the inputs of registers 4, 11 levels of one or zero. over a period of time equal to or more than 3, therefore, the highest frequency of beats, which can be distinguished by elements 5, b, 12, 13, does not exceed I / (2K). If there are multiple alternation of levels, this frequency is even lower. In the general case, the effective extraction of the low-frequency component occurs as long as during a period of beats, at least once, the time, both the unit level and the zero level, exceeds%.

Claims (1)

The fulfillment of this condition ensures the switching of the RS-flip-flops 7, 14 in the channels with exactly the frequency and mutual phase of the zero-beat oscillations. In the case of the absence of an input signal in general and in the case of a very small input signal, a logical zero level is present at one or several inputs of elements 5, b, 12, 13 due to the fast level alternation. Elements 5, b, 12, 13 as a result do not produce output pulses and RS-flip-flops 7, 14 do not switch. Since block 16 is sensitive to switching the input signal levels, the formation-pulse mismatch does not occur at its outputs. This property of the discriminator ensures that its accuracy characteristics are preserved not only when the input signal is low, but also when it disappears and fades. The proposed discriminator makes it possible to lower the power of the emitted signal and has improved precise characteristics. Claims of the Invention The zero-beat discriminator, in-phase and quadrature channels with a mixer, filter, low-pass and a limiting amplifier connected in series in each channel, as well as a tunable generator and control unit common to both channels, differing from C; Note that in order to improve the accuracy and expansion of the dynamic range of the input signals, a shift register, two coincidence elements and an RS-tritger, as well as a delay block and a frequency divider common to both channels, are entered into each discriminator channel, and the information inputs the shift registers are connected to the outputs of the limiting amplifiers, the forward and inverse outputs of each bit of the shift register are connected respectively to the inputs of the first and second coincidence elements, the outputs of which are connected to the RS-trigger inputs, and the RS-trigger outputs moat. each channel is connected to the inputs of the control unit, the outputs of which are connected to the inputs of a tunable generator, while the output of the tunable generator is connected via a delay unit to the inputs of the coincidence elements and connected directly to the synchronization inputs of the shift registers and to the input of a frequency divider which is connected to the common-channel mixer and phase shifter quadrature channel. Sources of information, take into account when the expert ize 1. USSR author's certificate number 403013, class, N 03 O 13/00, 1971 (ProTS1TS),