JPS5635588A - Equivalent pulse eliminating circuit - Google Patents
Equivalent pulse eliminating circuitInfo
- Publication number
- JPS5635588A JPS5635588A JP11107579A JP11107579A JPS5635588A JP S5635588 A JPS5635588 A JP S5635588A JP 11107579 A JP11107579 A JP 11107579A JP 11107579 A JP11107579 A JP 11107579A JP S5635588 A JPS5635588 A JP S5635588A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input terminal
- signal
- output terminal
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/82—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback the individual colour picture signal components being recorded simultaneously only
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To reduce the variance to the elements and thus ensure a steady working, by forming with a digital circuit the equivalent pulse eliminating circuit which is used for the means to obtain the carrier signal in case the color signal receives the frequency conversion. CONSTITUTION:The composite synchronous signal input terminal 21 is connected to the NAND circuit 24. At the same time, the 1st output terminal of the circuit 24 is connected to the 1st input terminal of the NAND circuit 26 via the shift register 25; and the 2nd output terminal of the circuit 24 is connected to the 2nd input terminal of the circuit 26 each. And the 3rd output terminal of the circuit 24 is connected to the 2nd input terminal of the NAND circuit 28. Then the clock pulse input terminal 22 is connected to the clock pulse input terminal CP of the D type F-F circuit FF1 and FF2 each. Accordingly, in such circuit both the reversed signal and the output signal of the output terminal Q of the D type F-F circuit FF7 are applied to the circuit 28, thus obtaining the horizontal synchronous signal in the horizontal period.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11107579A JPS5635588A (en) | 1979-08-31 | 1979-08-31 | Equivalent pulse eliminating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11107579A JPS5635588A (en) | 1979-08-31 | 1979-08-31 | Equivalent pulse eliminating circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5635588A true JPS5635588A (en) | 1981-04-08 |
JPS6126871B2 JPS6126871B2 (en) | 1986-06-23 |
Family
ID=14551742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11107579A Granted JPS5635588A (en) | 1979-08-31 | 1979-08-31 | Equivalent pulse eliminating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5635588A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60116287A (en) * | 1983-11-28 | 1985-06-22 | Matsushita Electric Ind Co Ltd | Horizontal afc device |
-
1979
- 1979-08-31 JP JP11107579A patent/JPS5635588A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60116287A (en) * | 1983-11-28 | 1985-06-22 | Matsushita Electric Ind Co Ltd | Horizontal afc device |
Also Published As
Publication number | Publication date |
---|---|
JPS6126871B2 (en) | 1986-06-23 |
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