JPS6126871B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a video tape recorder (hereinafter referred to as VTR).
This invention relates to an effective equivalent pulse removal circuit that can be used as a means for obtaining a carrier signal when converting the frequency of a color signal (abbreviated as ).

Synchronization signals for color television signals include vertical synchronization pulses, horizontal synchronization pulses, equivalent pulses, color burst signals, and the like. There are cases in which continuous horizontal synchronization pulses are obtained by removing equivalent pulses from such a composite synchronization signal and pulse-shaping the vertical synchronization pulses. For example, in a VTR, a carrier signal for frequency conversion is required to perform low frequency conversion of a color signal, and this carrier signal is synchronized with a horizontal synchronizing signal.

Conventionally, as shown in FIG. 1, the method for obtaining the above-mentioned horizontal synchronizing signal has been to provide two stages of monostable multivibrator circuits 11 and 12 to remove the equivalent pulse and obtain only the horizontal synchronizing pulse.
The time constant of the monostable multivibrator circuit 11 is set to be more than 1/2 H (H: 63.5 μs periodicity of horizontal scanning period or horizontal synchronizing pulse) and less than 1 H. Further, the time constant of the monostable multivibrator circuit 12 is set to 0.075H. As a result, continuous horizontal synchronizing pulses can be obtained even during the vertical retrace period. That is, FIG. 2a shows the composite synchronous signal input to the monostable multivibrator circuit 11, and FIG. 2b shows the output of this circuit 11, the second
Figure c is the obtained horizontal sync pulse.

According to the conventional equivalent pulse removal circuit described above, since the pulse width is determined by a time constant determined by the capacitance and low resistance, there is a drawback that the pulse width is easily changed due to variations in the elements. Furthermore, if this is integrated into an integrated circuit, two time constants are required, so there is a drawback that a large number of external capacitance bins are required.

This invention was made in response to the situation in the first half of the year, and is suitable for integration because it does not require terminal pins, has a stable pulse width, and can provide stable operation to circuits that use its output. The purpose of the present invention is to provide an equivalent pulse removal circuit that can perform the following steps.

Embodiments of the present invention will be described below with reference to the drawings.

In Fig. 3, 21 is a double synchronization signal input terminal, 22
23 is a clock pulse input terminal, and 23 is a constant high level signal input terminal.

The composite sync signal input terminal 21 is connected to a NAND circuit 24 that inverts the composite sync signal.

The NAND circuit 24 has first, second, and third output terminals, and the first output terminal is connected to the first output terminal of the NAND circuit 26 via a shift register 25 that delays the composite synchronization signal.
The input terminal and the second output terminal are connected to this NAND circuit 26.
is connected to the second input terminal of. Further, the third output terminal of the NAND circuit 24 is connected to the second output terminal of the NAND circuit 28.
Connected to the input end.

Next, the clock pulse input terminal 22 is connected to D
Of type flip-flop circuits FF1 to FF6, D
It is connected to the clock pulse input terminals CP and CP of flip-flop circuits FF1 and FF2. FF2
The inverted output terminal of is connected to the input terminal D of FF1,
The non-inverting output terminal Q of FF1 is connected to the input terminal D of FF2. Therefore, FF1 and FF2 divide the clock pulse into four.

The non-inverting output terminal Q of FF2 is the clock pulse input terminal of D-type flip-flop circuits FF3 and FF4.
CP, connected to CP. The inverting output terminal of FF4 is connected to the input terminal D of FF3, and the non-inverting output terminal Q of this FF3 is connected to the input terminal D of FF4. Therefore, FF3 and FF4 divide the clock pulse by 16. Moreover, a pulse whose pulse width is smaller than 1/2H is derived from the inverted output terminal of FF3, and a pulse whose pulse width is smaller than 1/2H is derived from the D-type flip-flop circuit FF.
It is supplied to the clock pulse input terminal CP of 7.

Next, the non-inverting output terminal Q of the FF4 is connected to clock pulse input terminals CP and CP of D-type flip-flop circuits FF5 and FF6. And FF6
The inverted output terminal of is connected to the input terminal D of FF5,
The non-inverting output terminal Q of this FF5 is connected to the input terminal D of FF6. Therefore, FF5 and FF6 divide the clock pulse by 64.

Next, a pulse whose pulse width is larger than 1/2H and smaller than 1H is derived from the non-inverting output terminal Q of the FF 6, and is supplied to the third input terminal of the NAND circuit 26.

The output terminal of this NAND circuit 26 is connected to the NAND circuit 2
NAND circuit 2 forming a reset circuit with 6
It is connected to the input terminal of 7. This NAND circuit 2
A pulse having a pulse width sufficient to reset FF1 to FF7 is derived from the output terminal of FF7, and is supplied to each reset terminal R.

The high-level signal input terminal 23 is connected to the input terminal D of the FF7 that forms a gate pulse generation circuit, and the inverted output terminal of the FF7 is connected to the input terminal D of the NAND circuit 28 that forms a gate circuit for gating a composite synchronization signal. It is connected to the first input terminal. The output terminal of this NAND circuit 28 is derived as a horizontal synchronizing pulse output terminal.

An embodiment of the present invention is constructed as described above, and the clock pulse has a frequency higher than that of the horizontal synchronizing signal (44-1/4) _H = 175/4 _H ( _H : horizontal frequency). This is used because there is a color subcarrier. This signal is generated by a voltage controlled oscillator in order to generate a carrier signal for converting the frequency of the color signal in, for example, a β-type VTR.

The operating waveforms of the above circuit are shown in FIG. 4 and will be explained. FIG. 4a is the input composite synchronization signal and FIG. 4b is the clock pulse with a frequency of 175/ _4H .
4c is a signal applied to the high level signal input terminal.

The clock pulse is sent to FF1, which forms a frequency divider circuit.
~1/4 of FF6 by FF1 and FF2 x (44-1/4)
The frequency is divided into _H clock pulses. This clock pulse is further divided into 1/4 by FF3 and FF4, and further divided by 1/4 by FF5 and FF6, so the output of FF6 is (44-1/4) _H divided by 1/4. The signal is frequency-divided by /642. Therefore, the pulse width of the output of FF6 is 123/175H (FIG. 4f).

Here, since the clock pulse is not synchronized with the horizontal synchronizing pulse, it is necessary to synchronize the divided output with the clock. Therefore, in this example,
FF1 to FF6 forming the frequency dividing circuit are reset by a reset pulse synchronized with the horizontal synchronizing pulse.

In addition, the NAND circuit 26 receives a signal obtained by inverting the composite synchronization signal (see FIG. 4, 4e), and a signal delayed and inverted by the shift register 25 (see FIG. 4, 4b). From these signals, the NAND circuit 26 detects the edge of the horizontal synchronization pulse and the equivalent pulse included in the composite synchronization signal. If this continues, the reset pulses mentioned above will be obtained from the NAND circuit 27 at 1/2H intervals, so the pulses having a pulse width of 123/175H obtained at the output terminal Q of the FF6 (Fig. 4, 4f) are used as mask pulses. The signal is supplied to the NAND circuit 26, and edge detection corresponding to the equivalent pulse is prohibited. Therefore, a horizontally periodic reset pulse (FIG. 4g) can be obtained from the NAND circuit 27. Therefore, since FF1 to FF7 are reset at the falling timing of the horizontal synchronizing pulse in the input composite synchronizing signal, the frequency-divided output is synchronized with the horizontal synchronizing pulse.

Next, considering the output waveform of the inverted output terminal of FF3, in the reset operation by FF1, FF2, and FF3, the waveform changes from 12/175H to 16/17H after the overall reset.
High level for 175H, then 64/17 until next reset
5 This is the reset timing for the H cycle (see Figure 4).
h). Since this pulse is approximately equal in width to the horizontal synchronizing pulse, it can be used as a gate pulse for extracting the horizontal synchronizing pulse.

If the input terminal D of the D-type flip-flop circuit FF7 is always kept at a high level, the inverted output terminal will be at a high level for a period of 16/175H after a reset, and then a gate pulse can be obtained that will be at a roll level until the next reset. (Figure 4 4i). Therefore, a signal obtained by inverting the input composite synchronization signal and FF7
By applying the output signal of the output terminal of the horizontal synchronizing pulse (the fourth
Figure 4j) can be obtained.

In addition, during the cutting pulse period, FF1 to FF6 forming the frequency dividing circuit perform the same operation as in the equivalent pulse period, but the NAND circuit 28 forming the gate circuit receives the cutting pulse having a pulse width of 0.425H. is supplied. Therefore, during this period, a gate pulse appears in the NAND circuit 28 having approximately the same width as the horizontal synchronizing pulse.

According to the above-described equivalent pulse removal circuit of the present invention, since a digital circuit is used in contrast to the conventional two-stage monostable multivibrator circuit, variations among elements are small. Furthermore, stable operation is obtained even against temperature fluctuations. Furthermore, it is less likely to malfunction due to noise or induction. In other words, even if a synchronization disturbance occurs in the clock pulse, FF1 to FF always form a frequency dividing circuit using the reset pulse.
Since the operation of 6 is synchronized with the horizontal synchronization pulse, no malfunction will occur. Furthermore, since the reset pulse of the frequency dividing circuit is masked by the Q output of FF6, noise superimposed on the composite synchronization signal during that period is removed, resulting in stable operation. In other words, the closer the pulse width of this mask pulse is to 1H, the more effective the noise removal effect is. Furthermore, since the composite synchronization signal is gated by a gate pulse approximately equal to the width of the horizontal synchronization pulse, noise superimposed on the composite synchronization signal during periods other than the gate period can be removed. Further, during the cutting pulse period, this gate pulse is output as a horizontal synchronizing pulse. Furthermore, when creating an integrated circuit, the conventional method requires two time constants, so two or more pins are required, but according to the present invention, by using an oscillator within the integrated circuit, the number of pins becomes external. It has many advantages such as not requiring pins.

As explained above, it is an object of the present invention to provide an equivalent pulse removal circuit that does not require terminal pins, is suitable for integration, is not easily affected by element variations, temperature fluctuations, and noise, and can output an output with a stable pulse width. I can do it.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a conventional equivalent pulse removal circuit.
Figures 2 a to c are signal waveform diagrams of each part of the circuit in Figure 1;
FIG. 3 is a circuit configuration diagram of an equivalent pulse removal circuit according to an embodiment of the present invention, and FIGS. 4a to 4j are signal waveform diagrams of various parts of the circuit of FIG. 3. 24, 26, 27, 28... NAND circuit, FF
1 to FF7...D-type flip-flop circuit, 25
...Shift register.

Claims (1)

[Claims] 1. Edge detection means for detecting edges of horizontal synchronization pulses and equivalent pulses included in a composite synchronization signal and generating edge detection pulses; A first pulse including a gate pulse having a pulse width sufficient to gate the horizontal synchronizing pulse immediately after the reset is generated by dividing a high frequency clock pulse, and immediately after the reset, a first pulse including a gate pulse having a pulse width sufficient to gate the horizontal synchronizing pulse is generated. a frequency dividing means for generating a second pulse that exhibits a state change after a period longer than the horizontal scanning period; a reset means for prohibiting detection and resetting the frequency dividing means in synchronization with a horizontal synchronizing pulse; and a first pulse output of the frequency dividing means which is reset in synchronization with the frequency dividing means at the reset timing of the reset means. An equivalent pulse comprising: gate pulse generation means for extracting the gate pulse from the gate pulse; and gate means for extracting a horizontal synchronization pulse from the composite synchronization signal in response to the gate pulse output of the gate pulse generation means. removal circuit.