JPH0767144B2 - Image signal synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a television receiver, a CRT display, a V
The present invention relates to an image signal synchronizing circuit for electronic devices such as TRs and video printers that handle image signals.

[Prior Art] Originally, a synchronizing signal for an image signal was used for displaying an image in a television receiver and an extended CRT display, etc. For convenience, in many cases, a pulse having a half cycle of the horizontal cycle, which is called an equalization pulse, is added before or after the vertical synchronization signal period.

Figure 4 shows the standard commonly used for television signals.
It is a signal waveform in the vicinity of the vertical synchronizing signal portion of the synchronizing signal of the NTSC signal. In the figure, ▼ indicates a horizontal synchronizing signal and ▽ indicates an equalizing pulse.

When the equalizing pulse is viewed from the synchronous circuit, it is a partial and abrupt change in the input frequency, and follows the change in the input frequency according to the response speed and the pull-in range of the synchronous circuit.
At the end of the equalizing pulse, the original normal frequency is restored.

Further, since the synchronizing circuit is a feedback control system, it cannot instantaneously follow or recover from the rapid change in the input frequency as described above, and there is a time delay with respect to the change in the input frequency. Therefore, the horizontal sync is disturbed near the vertical sync signal.

As a countermeasure against this, in the conventional television receiver,
By reducing the pull-in range of the synchronization circuit and adjusting the response speed appropriately, the disturbance of horizontal synchronization is restored until the image signal appears after the vertical synchronization signal portion, that is, the equalization pulse is input. Various measures were taken.

On the other hand, with the development of inexpensive memory and LSI dedicated to image processing with the recent development of digital technology, high resolution image signals have come to be used. Such high resolution image signals do not comply with the standard NTSC signals mentioned above,
A wide variety of types are used, with horizontal frequencies ranging from 15 KHz to 30 KHz, and higher resolutions ranging up to 60 KHz.

In order to cope with the image signal having the synchronizing signal over these wide frequency ranges, the synchronizing circuit for the image signal needs to have a wide pull-in range.

For example, if a phase locked loop with an edge trigger type phase comparator is used, the pull-in range will be the same as the free-run oscillation range of the voltage controlled oscillator (VCO), and a wide pull-in range can be easily achieved. . Further, such a synchronizing circuit can be constructed so as to utilize the high phase accuracy to reproduce the dot frequency of the image signal from the horizontal synchronizing signal.

However, with respect to the sync signal having the above-mentioned equalizing pulse, such a sync circuit cannot be used because it causes a large disturbance in horizontal sync near the vertical sync signal.

FIG. 5 is a block diagram showing the structure of a conventional horizontal synchronizing circuit of a general-purpose CRT display that supports synchronizing signals over a wide frequency range. In FIG. 5, (10) is an input terminal of the synchronizing signal and (20) is an output terminal. , (1) is a frequency-voltage conversion circuit (hereinafter referred to as f / v circuit), (2) is a VCO, (3) is an edge trigger type phase comparator, and (4) is a low-pass filter (hereinafter, referred to as a loop filter). , LPF),
These form a phase-locked loop.

The operation itself of the synchronizing circuit having the above-mentioned configuration has a small pull-in range like the synchronizing circuit of the conventional television receiver, but a frequency / voltage conversion (f / v) circuit (1) provided separately is provided.
Thus, the horizontal free-run frequency, that is, the center frequency of the pull-in range is appropriately changed according to the input signal to realize a wide pull-in range in appearance.

However, because the pull-in range of the synchronization circuit itself is small, it is necessary to follow the change in the free-run frequency quite rigorously in response to the change in the input frequency.Because it is not feedback control, tracking adjustment, ambient temperature change, etc. Compensation is required and it is not easy to realize a sufficiently large pull-in range.

Further, in the case of the synchronizing circuit as described above, since the disturbance of the horizontal synchronization occurs near the vertical synchronizing signal, it is unsuitable for the purpose of reproducing the dot frequency of the image signal.

[Problems to be Solved by the Invention] Since the conventional image signal synchronizing circuit is configured as described above, it is difficult to secure horizontal synchronization with high phase accuracy for a synchronizing signal over a wide frequency range. In addition, there is a problem that a control circuit that requires adjustment and temperature compensation must be added. Further, the synchronization circuit using the edge trigger type phase comparator has a drawback that it is possible to perform synchronization with high accuracy and a wide range, but it is not possible to secure stable synchronization with a signal having an equalized pulse. .

The present invention has been made in order to solve the above-described problems, and it is possible to secure a wide pull-in range and a high phase accuracy while being unadjusted, and influence the equalization pulse on all signals within the pull-in range. It is an object of the present invention to provide a synchronizing circuit for an image signal, which can ensure stable synchronization without being affected.

[Means for Solving the Problems] An image signal synchronizing circuit according to the present invention is an equalizer inserted between a horizontal synchronizing signal, a vertical synchronizing signal, and a pulse of the horizontal synchronizing signal adjacent to each other within a predetermined period. The equalization pulse is removed from a composite synchronizing signal having a pulse. The image signal synchronizing circuit includes (a) first signal generating means for generating a removal permission signal that is activated only within the predetermined period based on the vertical synchronizing signal;
Extraction means for extracting and outputting the horizontal synchronizing signal and the equalized pulse from the composite synchronizing signal; and (c) an output terminal,
A gate having an input connected to the extraction means,
(D) a PLL circuit which is connected to the output terminal of the gate and which generates an original removal signal having the same frequency as that of the horizontal synchronization signal; and (e) the original removal signal is input, Second signal generating means for generating a removal signal having the same frequency as the original removal signal, a phase delayed by 90 degrees from the original removal signal, and a duty of 50%. Here, the gate shuts off the input terminal and the output terminal of the gate only when the removal enable signal is activated and the removal signal is active, and otherwise, the input terminal and the output terminal of the gate are provided. Connect. The second signal generation means compares (e-1) an integration circuit that generates a triangular wave from the original removal signal with (e-2) the triangular wave and an average value thereof, and outputs the removal signal. A waveform shaping circuit.

[Operation] According to the present invention, the equalization pulse can be removed from the output of the extraction means with the removal signal having the same frequency as the horizontal synchronization signal, the phase delayed by 90 degrees from the original removal signal, and the duty of 50%. It is possible to always remove the equalization pulse over a wide frequency range and ensure stable horizontal synchronization. In addition, the removal permission signal prohibits removal of the equalization pulse except in the vicinity of the vertical synchronization signal, and the signal is directly input to the synchronization circuit, so that horizontal synchronization is promptly performed against sudden changes in the input frequency. Can be followed.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an image signal synchronizing circuit according to an embodiment of the present invention. This synchronizing circuit is based on an edge trigger type phase lock loop in order to obtain a wide pull-in range without adjustment.

In FIG. 1, (10) is a synchronizing signal input terminal, and (2)
0) and (21) are horizontal sync output terminals.

(3) is an edge trigger type phase comparator, (4) is an LPF acting as a loop filter, (5) is a VCO, and these three form a phase lock loop.

(1) and (6) are first and second for waveform shaping
One-shot multi-vibrator (hereinafter referred to as MM1 and MM2). (7) is a 90 ° delay circuit that constantly delays the output of 50% duty by 90 °.
The 90 ° delay circuit section (7) is composed of resistors (13) and (14), capacitors (15) and (16), a reference voltage (17) and a comparator (18).

(2) and (8) are AND gates for opening and closing signals, (9) is a vertical synchronization branch circuit (hereinafter referred to as V-DET circuit) for separating the vertical synchronization signal from the input composite synchronization signal,
(10) and (1) are the third and fourth ones.
Multivibrator (hereinafter referred to as MM3 and MM4), which is used to create a pulse that starts after a certain time from a vertical sync signal and ends before the next vertical sync signal.

Note that (a) to (k) in FIG. 1 indicate measurement points of the signal waveforms referred to in FIGS. 2 and 3.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1. In FIG. 2, (a) to (i) and (k) are signal waveforms corresponding to the circuit parts shown in FIG. 1, respectively. On the same time axis. here,
A composite sync signal having an equalized pulse is given to (a).

Similar to FIG. 2, FIG. 3 is a signal waveform diagram for explaining the operation of the circuit of FIG. 1, which is shown at a larger time interval than in FIG. 2, and in FIG. (G) ~
(K) shows the signal waveform of each circuit part shown in FIG.
It is shown on the same time axis.

Next, the operation of the above configuration will be described with reference to FIGS. 2 and 3.

The composite sync signal (a) input from the input terminal (10) is MM
Trigger 1 (1). The output (b) of this MM1 (1) is
The pulse width (t1) becomes a horizontal synchronization signal unified with the oscillation pulse width of MM1 (1). However, in this horizontal synchronizing signal, an equalizing pulse (∇) having a half period (tH / 2) of the horizontal period (tH) exists before and after the vertical synchronizing signal part (tV).

Next, the equalization pulse removal signal (f) is input to the AND gate (2) via the AND gate (8). As will be described later, since the other input (i) of the AND gate (8) is always 0 near the vertical sync signal, the equalization pulse removal signal (f) is simply inverted and output as shown in (k). Becomes

As a result, from the rise of the horizontal sync signal (b), (1/4) tH
From the latter to (3/4) tH later, the above (k) is 0, the equalization pulse existing during this period is removed, and the equalization pulse does not appear in the output (c) of the AND gate (2).

Next, the signal (c) from which the equalized pulse has been removed is input to the phase comparator (3), and this phase comparator (3), LPF
The phase lock loop consisting of (4), VCO (5) and MM2 (6) is operated stably. The output (d) of 50% duty of the phase lock loop is always input to a 90 ° delay circuit section (7) which gives a delay of 90 °, that is, (1/4) tH. The circuit section (7) further includes an integrating circuit including a resistor (13) and a capacitor (15), a comparator (18),
It consists of a waveform shaping circuit consisting of a resistor (14), a capacitor (16) and a reference voltage (17), the constant of the integrating circuit is sufficiently large, and the output has a substantially triangular waveform as shown in FIG. 2 (e). . This waveform output (e) is connected to the + input of the comparator (18) via the capacitor (16), but the DC bias at this point is given from the reference voltage (17) via the resistor (14). Voltage. That is, the average value of the waveform of the output (e) is the same as the reference voltage (17).

Since this voltage is connected to the-input of the comparator (18), the comparator output has a high level "1" at a portion higher than the average value of (e) and has a low level "0" at other portions.

When the output (e) is a triangular wave, the output (f) has a duty of 50% like the input and always has a delay of 90 ° regardless of the frequency.

The signal thus obtained is input to the AND gate (2) via the AND gate (8) as the signal (f) for removing the equalized pulse.

In this way, the equalization pulse is reliably removed in the steady state, and the phase lock loop maintains stable operation.

However, in a transient state where the frequency of the input signal fluctuates rapidly, this equalized pulse removal has a bad effect,
It may take time to ensure proper synchronization, or malfunction may occur. For example, the frequency of the input signal (f
When the frequency of the input signal suddenly changes to double in the steady state in synchronization with H), every other horizontal pulse of the input synchronization signal is removed, and the phase-locked loop is still present. It remains synchronized with the frequency (fH) of the input signal.

To prevent such malfunction or increase in tracking time,
The following means are used to limit the removal of the equalization pulse only to the vertical sync signal and the vicinity (tVp).

That is, in FIG. 1 and FIG. 3, the input terminal (1
The composite synchronizing signal (a) input from 0) becomes the vertical synchronizing signal output (g) by the V-DET circuit (9). The rising edge of the vertical synchronizing signal output (g) triggers the MM3 (10) to generate the pulse (h) of the time width (t3). Here, the time width (t3) of the pulse (h) is set to be sufficiently larger than the region where the equalization pulse is considered to exist for all signals considered as the input. Also, the time width (t
Trigger MM4 (11) at the falling edge of 3),
Generate pulse (i) in 4).

The time width (t4) is a time from the end of the pulse (i) to the next vertical pulse, which is tv− (t4 + t3), which is sufficiently larger than the region where the equalization pulse exists for all possible signals. Has been selected. This pulse (i)
Is input to the AND gate (8), and when the pulse (i) is at the high level "1", the signal (f) for removing the equalized pulse
Does not appear in the output (k) of the AND gate (8). That is, the equalizing pulse is removed only near the vertical synchronizing signal.

Since the equalized pulse is not removed in this way and the input signal is directly input to the phase comparator (3), if the phase-locked loop has sufficient response intensity, this time Since synchronization is almost established within (t4), there is no malfunction or delay in tracking time.

As described above, stable synchronization can be ensured for a signal having an equalized pulse over a wide frequency range.

As described above, according to the present invention, the equalization pulse is removed by the removal signal, and the removal of the equalization pulse is performed only within the predetermined period when the removal permission signal is activated.
A phase lock loop with a wide pull-in range and high phase accuracy, such as an edge-triggered phase comparator, can also be used for signals with equalized pulses, and thus any signal within the pull-in range. On the other hand, high-performance synchronization can be ensured without adjustment without being affected by the equalization pulse.

[Brief description of drawings]

FIG. 1 is a block diagram showing the construction of an image signal synchronizing circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining the operation, respectively, showing signals corresponding to the circuit portion of FIG. Waveform diagram, Fig. 4 is a waveform diagram around the vertical sync signal in the sync signal part of the standard NTSC signal used in television signals, and Fig. 5 is the horizontal sync of a general-purpose CRT display that supports sync signals over a wide frequency range in the past. It is a block diagram which shows the structure of a circuit. (1), (6), (10), (11) ... MM1-4,
(2), (8) ... AND gate, (3) ... phase comparator, (4) ... LPF, (5) ... VCO, (7) ... 90 ° delay circuit, (9) ... V-DET circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An image for removing the equalizing pulse from a composite synchronizing signal having a horizontal synchronizing signal, a vertical synchronizing signal, and an equalizing pulse interposed between adjacent pulses of the horizontal synchronizing signal within a predetermined period. A signal synchronization circuit, comprising: (a) first signal generation means for generating a removal permission signal that is activated only within the predetermined period based on the vertical synchronization signal; and (b) the horizontal signal from the composite synchronization signal. Extraction means for extracting and outputting a synchronizing signal and the equalized pulse; (c) a gate having an output end and an input end connected to the extraction means; (d) connected to the output end of the gate And a PLL circuit that generates an original removal signal having the same frequency as the horizontal synchronization signal, and (e) inputs the original removal signal and has the same frequency as the original removal signal and the original removal signal. From the signal Second signal generating means for generating a removal signal having a phase delayed by 90 degrees and a duty of 50%, wherein the gate is provided only when the removal permission signal is active and when the removal signal is active. The input terminal and the output terminal of itself are blocked, and the input terminal and the output terminal of the other are connected except for the above, and the second signal generating means (e-1) generates a triangular wave from the original removal signal. And a waveform shaping circuit that outputs the removal signal by comparing the triangular wave with an average value thereof (e-2).