JPH05300470A - Clock signal generation circuit - Google Patents

Abstract

PURPOSE:To promptly synchronize with an input signal in a clock signal generation circuit using a PLL. CONSTITUTION:In a clock signal generation circuit generating a clock signal synchronized with an input signal in a PLL circuit provided with a phase comparator 2, an integration circuit 3, a VCO 4 and a 1/n counter 5, a skew is detected from an extracted horizontal signal a when the input signal is a VTR reproduced signal, a 1/n counter 5 is reset by the detected signal in a reset pulse e and the synchronization with the input signal is promptly performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generating circuit, and more particularly to a circuit for generating a stable clock signal synchronized with an input horizontal synchronizing signal.

[0002]

2. Description of the Related Art In digital processing of a video signal of a television receiver or the like, a clock signal which is synchronized with the horizontal synchronizing signal and has a frequency n times, for example, 910 times, the horizontal synchronizing frequency fH is required. An example of a conventional circuit for generating such a clock signal is shown in FIG. In the figure, a horizontal synchronizing signal a is extracted from the composite synchronizing signal separated from the video signal via the equalization pulse removing circuit 1 and input to the phase comparator 2. The signal output from the phase comparator is converted into a control voltage corresponding to the phase difference via the integrating circuit 3, and a voltage controlled oscillator (hereinafter,
(Abbreviated as VCO) 4 is input. The VCO 4 oscillates a signal having a frequency n times as high as the horizontal synchronizing frequency fH according to the voltage level of the input, and this output is used as a clock signal for digital processing of the device and is also input to the 1 / n counter 5. The 1 / n counter 5 outputs a comparison signal f whose input clock frequency is 1 / n, and is compared with the horizontal synchronizing signal a by the phase comparator 2. That is, a closed loop of the phase comparator 2, the integrating circuit 3, the VCO 4, and the 1 / n counter 5 causes a PLL (PhaseLoc) that maintains a predetermined phase relationship between the horizontal synchronizing signal a and the oscillation signal of the VCO 4.
A clock signal locked to the horizontal synchronizing signal a can be obtained by configuring a ked loop) circuit.

However, in the above circuit, when the input signal is the VTR reproduction signal, the horizontal synchronizing signal becomes discontinuous due to the skew generated when the head is switched, and as a result, the PLL is out of lock and the clock signal is synchronized. However, there was a problem that it took a long time to stabilize again. FIG. 4 is an explanatory diagram of the skew that occurs when the VTR head is switched. In FIG. 4, (A) shows the relationship of the head switching position with respect to the video signal, and (B) shows the timing of the horizontal synchronizing signal output when the head is switched. For example, in the VHS system VTR, the heads are switched at every vertical cycle as shown in FIG. 9A, and the head 1 to the head are overlapped at any point 5 to 8 horizontal cycles before the vertical synchronizing signal. Switch to 2. FIG. 2B shows the horizontal synchronizing signal output from the head 1,
(B) shows a horizontal synchronizing signal output from the head 2. Now, when the head 1 is switched to the head 2 at the timing 20, the horizontal synchronizing signal a as shown in (c) is obtained. In this case,
The skew shortens the cycle of the sync signal at the switching point, and the normal cycle starts from the next sync signal. Further, when the head is switched at the point of timing 21, a horizontal synchronizing signal a as shown in (d) is obtained. In this case, the cycle of the synchronizing signal at the switching point becomes long, and the next synchronizing signal becomes a normal cycle. Return. That is, if there is a phase difference between the horizontal synchronizing signals of the head 1 and the head 2 when the heads are switched, as a result, a phase difference with the comparison signal f of the output of the 1 / n counter 5 is produced, and the operation of the PLL circuit is The image will be disturbed until it becomes unstable and stable.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is a clock signal for quickly generating a stable clock signal in synchronization with a horizontal synchronizing signal with respect to a skew in a VTR reproduction signal. A generation circuit is provided.

[0005]

To solve the above problems, the present invention provides a clock signal synchronized with a horizontal synchronizing signal in a PLL circuit including a phase comparator, an integrating circuit, a voltage controlled oscillator and a frequency dividing counter. Is a clock signal generation circuit for generating a clock signal, the frequency division counter having a reset function, the skew detection circuit detects a skew from a horizontal synchronizing signal extracted from the VTR reproduction signal, and the frequency division is performed based on the detection signal. A clock signal generating circuit for resetting a counter is provided.

[0006]

With the above construction, in the clock signal generating circuit according to the present invention, the skew detecting pulse is generated based on the input horizontal synchronizing signal, and the skew is detected by the skew detecting pulse and the horizontal synchronizing signal. Detect and
The 1 / n counter is reset by the detection signal to quickly synchronize with the horizontal synchronizing signal of the head output for switching.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a clock signal generating circuit according to the present invention will be described in detail below with reference to the drawings. 1 is a block diagram of essential parts showing an embodiment of a clock signal generating circuit according to the present invention, and FIG. 2 is a time chart showing the operation of this circuit. In the figure, the same parts as those in FIG. In FIG. 1, reference numeral 6 denotes a reset pulse generation circuit, which generates a reset pulse b having a width of, for example, 1 clock at the substantially center of the synchronizing pulse of the horizontal synchronizing signal a based on the input horizontal synchronizing signal a. Reference numeral 7 denotes a delay circuit, which outputs a pulse c delayed by a predetermined time from the reset pulse b, for example, a pulse c delayed by 2 clocks. Reference numeral 8 denotes a skew detection pulse generation circuit, which is composed of a counter for counting approximately 2 horizontal cycles,
It is reset by the pulse c of the output of the delay circuit 7, and V
The clock signal of the CO4 output is counted to generate the skew detection pulse d having a predetermined width (L level). A gate circuit 9 receives the reset pulse b and the skew detection pulse d, outputs a reset pulse e when the pulses b and d match each other, and resets the 1 / n counter 5.

Next, the operation of the clock signal generating circuit according to the present invention will be described with reference to FIG. First, steady operation
In the stable state of 10, the center position of the synchronizing pulse of the horizontal synchronizing signal a and the falling position of the comparison signal f are input to the phase comparator 2 in a phase relationship in which they substantially coincide with each other. At this time, since the position of the reset pulse b is at the “H” level of the skew detection pulse and there is no output from the gate circuit 9, therefore,
The 1 / n counter 5 is not reset and the normal P
Continue LL operation. Next, in the case of the skew response 11, the horizontal synchronizing signal a appears as the synchronizing pulse 13 at a timing shorter than one horizontal period by switching the head. The reset pulse b is generated based on this synchronization pulse 13.
At this time, the skew detection pulse is at the “L” level for detecting the presence or absence of skew, and therefore the reset pulse b is output as the reset pulse e via the gate circuit 9 and the 1 / n counter 5 is reset. The 1 / n counter 5 starts counting time from the reset point, generates a comparison signal f which falls at the point when one horizontal cycle has elapsed, and outputs it to the phase comparator 2. That is, at the timing of the next sync pulse of the sync pulse 13, the comparison signal f substantially in phase is generated, and therefore, the synchronous pull-in of the switching head to the horizontal sync signal is quickly performed. Further, the skew detection pulse generation circuit is reset with a slight delay by the delay pulse c, and generates and outputs the skew detection pulse at the regular timing from the reset point. Next, in the case of the skew response 12, the horizontal synchronizing signal a causes the synchronizing pulse 14 to appear at a timing longer than one horizontal period by switching the head. At this time, since the skew detection pulse generation circuit is composed of a counter of approximately 2 horizontal periods, even if the period of the synchronization pulse becomes long, a predetermined pulse is generated and output up to 2 horizontal periods. Therefore, the skew detection pulse d is at the “L” level for skew detection, and the reset pulse b based on the synchronization pulse 14 is 1 / n via the gate circuit 9.
The counter 5 is reset, the 1 / n counter 5 starts counting time from the reset point, generates the comparison signal f falling at the point when one horizontal period has elapsed, and outputs it to the phase comparator 2. That is, at the timing of the next sync pulse of the sync pulse 13, the comparison signal f substantially in phase is generated, and therefore, the synchronous pull-in of the switching head to the horizontal sync signal is quickly performed. Further, the skew detection pulse generation circuit is reset to the normal timing by resetting with the pulse c. Further, when the phase difference of the horizontal synchronizing signal a at the time of head switching is small and the reset pulse b based on the horizontal synchronizing signal a matches the “H” level of the skew detection pulse d, the reset pulse e is not output. , Normal PL
It does not impair the L operation.

[0009]

As described above, in the clock signal generating circuit according to the present invention, the skew detecting pulse is generated based on the input horizontal synchronizing signal, and the skew is detected by the skew detecting pulse and the horizontal synchronizing signal. Since the 1 / n counter is reset by the detection signal, the skew generated when the head of the VTR reproduction signal is switched is quickly synchronized with the horizontal sync signal of the head output of the switching, and the influence of the skew is generated. Is obtained, and a stable clock signal can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock signal generation circuit according to the present invention.

FIG. 2 is a time chart showing the operation of the clock signal generation circuit according to the present invention.

FIG. 3 is a block diagram showing an example of a conventional clock signal generation circuit.

4A and 4B are explanatory diagrams of a skew occurring when a VTR head is switched, FIG. 4A is a relational diagram of a head switching position with respect to a video signal, and FIG. 4B is a diagram showing a timing of a horizontal synchronizing signal when the head is switched. Is.

[Explanation of symbols]

 1 Equalization pulse removal circuit 2 Phase comparator 3 Integration circuit 4 VCO 5 1 / n counter 6 Reset pulse generation circuit 7 Delay circuit 8 Skew detection pulse generation circuit 9 Gate circuit

Claims (3)

[Claims] 1. A clock signal generating circuit for generating a clock signal synchronized with a horizontal synchronizing signal in a PLL circuit comprising a phase comparator, an integrating circuit, a voltage controlled oscillator and a frequency dividing counter, said frequency dividing counter. Has a reset function, a skew detection circuit detects a skew from a horizontal synchronizing signal extracted from a VTR reproduction signal, and the frequency division counter is reset by the signal of the detection, thereby generating a clock signal. circuit. 2. The skew detection circuit includes a reset pulse generation circuit that generates a reset pulse from an input horizontal synchronizing signal, a delay circuit that delays the pulse from the reset pulse generation circuit for a predetermined time, and a delay circuit output of the delay circuit. A skew detection pulse generation circuit that resets with a pulse and generates a pulse for skew detection, an output of the reset pulse generation circuit and an output of the skew detection pulse generation circuit are input, respectively, and the skew is detected and reset. The clock signal generation circuit according to claim 1, comprising a gate circuit that outputs a pulse. 3. The clock signal generation circuit according to claim 2, wherein the skew detection pulse generation circuit is composed of a counter that generates and outputs a skew detection pulse having a predetermined horizontal period of about 2 horizontal periods by the clock signal output from the voltage controlled oscillator.