JPH05167439A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the synchronization locking time without use of a phase difference setting circuit and a phase comparator circuit by adding a half of the phase difference relating to a period of an internal clock to a phase of an internal clock. CONSTITUTION:An external synchronizing signal inputted from an input terminal 1 is fed to a phase difference detection circuit 2, the phase difference detection circuit 2 detects a phase difference between the inputted signal and an internal clock outputted from a clock generating circuit 5 and the result is fed to a frequency divider circuit 3. The phase difference is halved and fed to an adder circuit 4, in which the phase of the internal clock and the halved phase difference are added. Then the added internal block is fed back to a frequency divider ratio setting circuit 6. The frequency divider ratio setting circuit 6 changes the frequency divider ratio by the fed-back internal clock to change the period of the internal clock generated in the clock generating circuit 5. Moreover, the clock generating circuit 5 changes the period of the internal clock by changing the frequency divider ratio of the output of the crystal oscillator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop circuit of a system internal clock of a VTR, TV or the like for an external synchronizing signal such as a video signal in a VTR or TV.

[0002]

2. Description of the Related Art A conventional technique is disclosed in, for example, JP-A-62-12.
As described in Japanese Patent No. 2325, the phase difference setting circuit sets the phase range of the phase comparison circuit. The phase comparison circuit outputs 1 if the phase difference is within the set range and 0 otherwise. The frequency division ratio of the variable frequency dividing circuit is set by the outputs of the plurality of phase comparison circuits. As described above, since the frequency division ratio is changed by the phase difference, the phase difference setting circuit and the plurality of phase comparison circuits are used, and there is a problem that the circuit scale becomes large.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, to provide a phase locked loop circuit having a simplified circuit configuration and a reduced circuit scale.

[0004]

In order to solve this problem, according to the present invention, a phase difference detecting circuit, a frequency dividing circuit and an adding circuit are provided, and a phase locked loop circuit is constituted by a simple circuit. is there.

[0005]

The phase detection circuit detects the phase difference between the internal clock and the external synchronization signal. This phase difference is halved by the frequency dividing circuit. By adding the halved phase difference to the internal clock, the phase difference between the internal clock and the external synchronization signal is corrected. By thus halving the phase difference between the internal clock and the external synchronization signal and adding them to the internal clock, the phase difference between the external synchronization signal and the internal clock is halved each time the external synchronization signal is input. It becomes as small as 1/4, 1/8, and 1/16. Therefore, the larger the phase difference between the internal clock and the external synchronization signal, the larger the phase change amount of the internal clock, and the smaller the phase difference, the smaller the phase change amount of the internal clock. Therefore, it is possible to shorten the phase pull-in time of the external synchronizing signal and the internal clock and realize a highly stable phase locked loop circuit.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the present invention, in which an internal clock is synchronized with an external synchronizing signal such as a vertical synchronizing signal or a horizontal synchronizing signal in a VTR, TV or the like. This is the case. Reference numeral 1 is an external synchronization signal input terminal, 2 is a phase difference detection circuit, 3 is a frequency dividing circuit that reduces the phase difference detected by the phase difference detection circuit 2 to half, 4 is an addition circuit, 5 is a clock generation circuit, 6 Is a frequency division ratio setting circuit, and 7 is a reference clock input terminal.

The external synchronizing signal input from the input terminal 1 is supplied to the phase difference detecting circuit 2. Here, the phase difference from the internal clock output from the clock generation circuit 5 is detected and supplied to the frequency dividing circuit 3. Here, the phase difference is halved and supplied to the adder circuit 4. The adder circuit 4 adds the internal clock and the halved phase difference. The added internal clock is fed back to the frequency division ratio setting circuit 6. The frequency division ratio setting circuit 6 changes the frequency division ratio according to the fed back internal clock, and changes the cycle of the internal clock generated by the clock generation circuit 5. The clock generation circuit 5 changes the cycle of the internal clock by changing the frequency division ratio of the crystal oscillator output. When the frequency of the reference clock is higher than the frequency of the internal clock, the internal clock may be generated from the reference clock instead of the crystal oscillator output.

The reference clock input from the input terminal 7 is supplied with the phase difference detection circuit 2, the frequency dividing circuit 3, and the frequency dividing ratio setting circuit 6.
Is supplied to.

The phase difference detecting circuit 2 uses the reference clock as a timer to measure the rising or falling time of the internal clock, and similarly measures the rising or falling of the external synchronization signal to measure the respective times. The phase difference is calculated from

The frequency dividing circuit 3 uses the reference clock as a counter and divides the phase difference by half.

FIG. 2 is a timing chart showing the operation of FIG. 1, and shows the case of synchronizing at the rising edge of the pulse. The clock C1 is in synchronization with the external synchronization signal S1, and the clock C2 is in the phase-shifted state by a half cycle. As shown in this figure, the phase shift decreases by half.

[0013]

According to the present invention, it is possible to realize a shortened synchronization pull-in time and high stability without using a phase difference setting circuit and a phase comparison circuit, and to realize a phase locked loop having a simplified circuit configuration. Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

[Explanation of symbols]

 1 ... External synchronization signal input terminal, 2 ... Phase difference detection circuit, 3 ... Dividing circuit, 4 ... Adding circuit, 5 ... Clock generating circuit, 6 ... Division ratio setting circuit, 7 ... Reference clock input terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroaki Chikada 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Hitachi Image Information Systems Co., Ltd. (72) Inventor Takashi Takahashi 5-22-1, Kamimizumoto-cho, Kodaira-shi, Tokyo No. Shares In Hitachi Microcomputer System (72) Inventor Yoshio Narita 1410 Inada, Katsuta City, Ibaraki Pref., Inside the Tokai Plant, Hiritsu Manufacturing Co., Ltd.

Claims (1)

[Claims] 1. A means for detecting a phase difference between an external synchronization signal and an internal clock in a phase locked loop circuit for phase-locking an external clock signal and an internal clock (hereinafter, internal clock) generated by dividing an output of a crystal oscillator. A means for dividing the detected phase difference into halves is provided, and means for adding the halved phase difference to the cycle of the internal clock is provided, and ½ of the phase difference for the cycle of the internal clock is added. A phase-locked loop circuit characterized by: