JPS63234630A - Phase locking compensating circuit for phase locked loop - Google Patents

Abstract

PURPOSE:To obtain a stable phase locked output by supplying a free-run output of a count means to a phase comparator circuit in place of an input signal whose pulse width is widened if the pulse width of the input signal is partially wider than the pulse width of a signal in a normal frequency range. CONSTITUTION:If the pulse width of the input signal is wider than the range of the normal pulse width at which the phase locking is taken in the phase locked loop, on L level pulse signal is generated from a NAND circuit 20 and a counter 21 generates an output signal at its free-run frequency. In this case, since the free-run frequency of the counter 21 is set slightly lower than the normal frequency of the input signal, the phase locked loop can sufficiently continue the phase locking. Since the output signal with the free-ran frequency of the counter 21 is given to the phase comparator circuit 12 in place of the input signal, the phase locked loop keeps the phase lock state. Thus, a stable phase locked output is obtained.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a phase-locked loop, and particularly relates to a phase-locked loop that provides a synchronized output when the pulse width of an input signal becomes longer than the normal state. The present invention relates to a synchronous compensation circuit that performs compensation.

(Prior Art) As is well known, a phase locked loop (PLL) is normally configured as shown in FIG. That is, the input signal supplied to the input terminal 11 is compared in phase by a phase comparison circuit 12 with a signal obtained by dividing the output signal of a voltage controlled oscillator circuit (hereinafter referred to as VCO) 13 by a frequency dividing circuit 14, and the phase difference is calculated. A phase error signal corresponding to the component is output.

This phase error signal is converted to a voltage level by a low-pass filter (hereinafter referred to as LPF) 15, and is applied to V CO1
3, and the oscillation frequency of the VCO 13 is controlled so that there is no phase difference between the input signal and the output signal of the frequency divider circuit 14. Note that the output of this phase-locked loop is
It is taken out via the output terminal 16.

Incidentally, the phase-locked loop as described above can obtain an output signal with a frequency that follows the input signal only when the frequency of the input signal is within a certain range. However, as shown in Figure 4, for example, if an input signal whose pulse width is partially longer than the pulse width of the normal frequency range is supplied, synchronization will be lost and it will be impossible to obtain a stable synchronized output. The problem arises that it cannot be done.

(Problems to be Solved by the Invention) As described above, in the conventional phase-locked loop, when an input signal whose pulse width is partially longer than the pulse width in the normal frequency range is supplied, the synchronization occurs. The problem is that it becomes impossible to obtain a stable periodic output.

Therefore, this invention was made in consideration of the above circumstances, and it is possible to obtain a stable synchronized output even if an input signal whose pulse width is partially longer than the pulse width of the normal frequency range is supplied. An object of the present invention is to provide an extremely good phase-locked loop synchronization compensation circuit.

[Structure of the Invention] (Means for Solving the Problems) That is, the phase-locked loop synchronization compensation circuit according to the present invention includes a voltage-controlled oscillation circuit and a frequency division circuit that divides the output signal of the voltage-controlled oscillation circuit. circuit, a phase comparison circuit that generates a phase error signal corresponding to the phase difference between the output signal of this frequency dividing circuit and the input signal, and a phase comparison circuit that converts the phase error signal output from this phase comparison circuit into a voltage level and generates a voltage. The target is a phase-locked loop equipped with a low-pass filter that controls the oscillation output frequency of a controlled oscillation circuit.

The pulse generating means generates a pulse signal in synchronization with either the rising edge or the falling edge of the input signal, and the output signal frequency is higher than the frequency of the input signal by counting a reference clock signal of a constant period. and counting means that is set to a slightly low value and set to an initial state in accordance with the pulse signal output from the pulse generating means, and configured to supply the output signal of the counting means to the phase comparator circuit as an input signal. This is what I did.

(Function) According to the above configuration, when the pulse width of the input signal is partially longer than the pulse width in the normal frequency range, the free run output of the counting means is changed to the input signal with the longer pulse width. Since the signal is supplied to the phase comparator circuit instead of the signal, if the 7-rerun output frequency of the counting means is set within the range where the phase-locked loop can be synchronized, the phase-locked loop will maintain the synchronized lock state. Therefore, stable synchronous output can be obtained.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as in FIG. 3 are shown with the same symbols, and only the different parts will be explained here. That is, the second
The input signal shown in Figure (a) is supplied to an N-bit shift register 17. This shift register 17 performs a shift operation in synchronization with a constant cycle reference clock signal output from a reference oscillation circuit (hereinafter referred to as O8C) 18, and its output is as shown in FIG. 2(b). The signal is slightly delayed relative to the input signal.

Further, the input signal is supplied to the NOT circuit 19 and inverted as shown in FIG. Therefore, as shown in FIG. 2(d), the NAND circuit 20 generates an L (low) level pulse signal at the falling edge of the input signal.

This pulse signal is then supplied to the clear input terminal CL of the counter 21. This counter 21 has the above 080
The frequency dividing circuit 22 divides the frequency of a reference clock signal of a constant period outputted from the circuit 18 and counts the signal, and the count output signal is supplied to the phase comparison circuit 12 as an input signal.

Further, the free run frequency of the counter 21 is set to a slightly lower frequency than the frequency of the input signal. When the clear input terminal CL of the counter 21 is set to the L level, the count output of the counter 21 is cleared and set to the initial state.

Therefore, as shown in FIG. 2(e), the count output signal of the counter 21 is , is cleared every time an L-level pulse signal is generated from the NAND circuit 20, and eventually has a frequency equivalent to the frequency of the input signal, and a normal synchronous lock operation is performed in the phase locked loop.

On the other hand, when the pulse width of the input signal becomes longer than the normal pulse width range that can be synchronized with the phase-locked loop, the NAND circuit 20 no longer generates an L-level pulse signal, and the counter 21 An output signal is generated at the run frequency (middle period T in FIG. 2(e)). In this case, as described above, the free run frequency of the counter 21 is set slightly lower than the frequency of the input signal in the normal state, so that the phase-locked loop can sufficiently continue its phase-locked operation.

Then, when the frequency of the input signal returns to its original state, the NAND circuit 20 again generates an L-level pulse signal, and hereafter, the output signal frequency of the counter 21 is as follows.
It is made to be the same as the frequency of the input signal.

Therefore, according to the configuration of the above embodiment, when the pulse width of the input signal becomes longer than the normal pulse width range that can be synchronized with the phase-locked loop, the free run frequency of the counter 21 is changed. Since the output signal is supplied to the phase comparator circuit 12 instead of the input signal, the phase locked loop can maintain the synchronous lock state.
This makes it possible to obtain stable synchronous output.

Further, in the above embodiment, the counter 21 is cleared at the falling edge of the input signal, but it is of course possible to clear the counter 21 at the rising edge depending on the polarity of the input signal.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] Therefore, as detailed above, according to the present invention, even if an input signal whose pulse width is partially longer than the pulse width in the normal frequency range is supplied, stable synchronous output can be achieved. It is possible to provide an extremely good phase-locked loop synchronization compensation circuit that can obtain the following characteristics.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of a phase-locked loop synchronization compensation circuit according to the present invention, FIG. 2 is a timing diagram for explaining the operation of the same embodiment, and FIG. The block diagram shown in FIG. 4 is a timing diagram for explaining the problems of the phase-locked loop. 11... Input terminal, 12... Phase comparison circuit, 13.
... VCo, 14... Frequency divider circuit, 15... LPF,
16... Output terminal, 17... Shift register, 18
08C119... Not circuit, 20... NAND circuit, 21... Counter, 22... Frequency divider circuit. 1b Figure 1 Cause 2

Claims (1)

[Claims] A voltage controlled oscillation circuit, a frequency dividing circuit that divides the output signal of the voltage controlled oscillator circuit, and a phase comparison circuit that generates a phase error signal corresponding to the phase difference between the output signal of the frequency dividing circuit and the input signal. , and a low-pass filter that converts the phase error signal output from the phase comparison circuit into a voltage level and controls the oscillation output frequency of the voltage controlled oscillation circuit. or a pulse generating means that generates a pulse signal in synchronization with one of the falling points, and a pulse generating means that counts a reference clock signal of a constant period and sets an output signal frequency slightly lower than the frequency of the input signal. and counting means that is set to an initial state in response to a pulse signal output from the pulse generating means, and configured to supply an output signal of the counting means to the phase comparison circuit as an input signal. Features a phase-locked loop synchronous compensation circuit.