JPH0462616B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a toothless clock generation circuit, switching is generated using the output of an N-ary counter, a first master clock, and a second master clock having the same frequency as this clock and a phase difference of π. By controlling the switching means using a control pulse to replace two first master clocks with one second master clock and outputting the same, the frequency of the first master clock is lowered and jitter is reduced. It is ivy.

[Industrial application field]

The present invention relates to an improvement in a toothless clock generation circuit, for example, a toothless clock generation circuit included in a digital phase synchronization circuit portion of an LSI for a car telephone.

FIG. 4 shows a block diagram of a digital phase synchronization circuit. In the figure, the frequency LSI master clock is connected to a digital phase synchronization circuit (hereinafter referred to as D-
This master clock is input to the digital voltage controlled oscillator (hereinafter referred to as D-PLL).
Since the frequency of VCO 4 (abbreviated as VCO) is higher than the frequency used, the pulses are periodically removed by the toothless clock generation circuit 1 (hereinafter abbreviated as toothless) to lower the frequency to the normal frequency.

Then, the D-VCO master clock, which has lost its teeth, is applied to the D-VCO 4, frequency-divided by M, further divided by the frequency divider 5, and then output as an output signal, as well as being input to the phase comparator 2. The phase with the signal is compared, and the comparison result information of phase lag or phase lead is integrated by an integrator 3 to control the D-VCO 4.

Here, the D-VCO normally divides the D-VCO master clock by M and outputs it, but when the output of the integrator exceeds a predetermined threshold, the frequency is divided by (M+1) or ( M-1) Attempts to make the phase difference between the input signal and the output signal zero by sending out the frequency-divided output.

At this time, if a jittery D-VCO master clock is input from the toothless clock generation circuit 1,
Since a jittery output signal is sent from the D-PLL circuit and other circuits using this output signal may malfunction, it is necessary that the D-VCO master clock has less jitter.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a time chart of FIG. The operation shown in FIG. 5 will be explained below with reference to FIG. Note that the numbers on the left side of FIG. 6 indicate the waveforms of the portions with the same numbers in FIG.

First, when the LSI master clock with the frequency shown in Figure 6 is input, the N-ary counter 6 becomes 0.
Start counting from and the count value is (N-1)
Then, a ripple carry as shown in FIG. 6 is output to the OR circuit 7.

Therefore, as shown in FIG. 6, the portion of the LSI master clock where the count value is 0 is masked, and a D-VCO master clock whose frequency is reduced to .(N-1)/N is obtained. Here, is the frequency of the LSI master clock.

[Problem that the invention seeks to solve]

Here, since the next rising edge after the rising edge at point C in FIG. 6 is not at point A but at point B, the jitter at this time is as follows.

[T′/T]×360=360 degrees (1) T' is the time the rising edge moves from A to B.

T is the time of one cycle.

In other words, since one clock is removed, the D-VCO master clock with 360 degree jitter becomes the D-VCO master clock.
4, so D should originally absorb the jitter.
-The PLL circuit will send out a clock with added jitter.

Therefore, there is a problem in that the jitter of the D-VCO master clock must be reduced.

[Means for solving problems]

The above problem is solved by the toothless clock generation circuit shown in FIG. 6 is an N-ary counter that counts the first master clock, and 8 synchronizes the output of the N-ary counter with a second master clock that has the same frequency as the first master clock but has a phase different by 180 degrees, and then further , a flip-flop portion synchronized to the first master clock;
The logical sum of the output synchronized with the second master clock and the output synchronized with the first master clock outputted by the flip-flop section is taken, and it rises at the rising point of the second master clock. and a logical OR part for generating a switching control pulse having a pulse width that falls at the rising point of the first master clock that appears immediately after the master clock.

Further, reference numeral 9 denotes a switching means which selects and outputs the first master clock when the switching control pulse is at L level, and selects and outputs the second master clock when it is at H level.

[Effect]

The present invention is a switching control pulse generating means that uses a first master clock, an output from an N-ary counter 6 that counts this clock, and a second master clock that has the same frequency as the first master clock and a phase difference of 180 degrees. generating a switching control pulse having a pulse width that rises at the rising point of the first master clock and falls at the rising point of the first master clock appearing immediately after the next second master clock;
This pulse drives the switching means to replace two first master clocks with one second master clock.

Therefore, since the second master clock is inserted in the center of the first master clock, the jitter is reduced by half, and since one first master clock is removed, the frequency of this clock is lowered.

〔Example〕

Figure 2 is a block diagram of an embodiment of the present invention, Figure 3 is a time chart of Figure 2, and the numbers on the left indicate the second
The waveforms of the same numbered parts in the figure are shown. The same reference numerals indicate the same objects throughout the drawings; D-type flip-flops 81 and 82 and an OR circuit 83 are components of the switching control pulse generating means 8, and a switch 91 is a component of the switching means 9. .

Hereinafter, the operation of FIG. 2 will be explained with reference to FIG. 3, assuming that the first master clock is a 0-phase master clock and the second master clock is a π-phase master clock.

First, when the 0-phase and π-phase master clocks shown in FIG. 3, which are generated from the LSI master clock in a part other than the D-PLL circuit, are input to the toothless clock generation circuit, the former is input to the N-ary counter 6 and the switch 9.
1. D-type flip-flop (abbreviated as D-FF) 82, the latter is D-FF81 and switch 91
added to.

Therefore, the N-ary counter starts counting up from 0, and when the count value reaches (N-1), the ripple carry is D- as shown in Figure 3-.
Since it is sent to the FF 81, an output that changes to 1 at the rising edge of the π-phase master clock and returns to 0 at the next rising edge is sent to the OR circuit 83 and the D-FF 82 (Fig. 3).
reference).

Next, as shown in FIG. 3, the output of the D-FF 82 changes to 1 at the rising edge of the 0-phase master clock and returns to 0 at the falling edge, and is sent to the OR circuit 83. As shown in the figure, it rises at the rising point of the second master clock,
An output having a pulse width that falls at the rising point of the first master clock that appears immediately after the second master clock is applied to the switch 91, and only during this time, as shown in FIG. A π-phase master clock is output.

That is, when the count value of the N-ary counter is between 0 and 1, two 0-phase master clocks are replaced with one π-phase master clock. As a result, the frequency of the 0-phase master clock becomes (N-1)/N, and
Since T′ in equation (1) above becomes (1/2)T, the jitter is
The D-VCO master clock with reduced jitter is supplied to the D-VCO.

〔Effect of the invention〕

As explained in detail above, according to the present invention, D-
This has the effect of reducing jitter in the D-VCO master clock supplied to the VCO.

As a result, the output signal sent from the D-PLL has less jitter, and malfunctions of other circuits that utilize this signal are reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart of Fig. 2, Fig. 4 is a block diagram of a digital phase synchronization circuit, and Fig. 5 is a block diagram of the principle of the present invention. 6 is a block diagram of a conventional example, and FIG. 6 is a time chart of FIG. 5. In the figure, 6 is an N-ary counter, 8 is a switching control pulse generating means, and 9 is a switching means.

Claims (1)

[Scope of Claims] 1. An N-ary (N represents an integer) counter 6 that counts a first master clock; and an N-ary (N represents an integer) counter 6 that counts the output of the N-ary counter with the same frequency as the first master clock but with a 180 degree phase difference. After synchronizing with the second master clock, a flip-flop section is further synchronized with the first master clock, and an output synchronized with the second master clock and an output synchronized with the first master clock outputted by the flip-flop section. Take the logical sum of and rise at the rising point of the second master clock,
The first clock that appears immediately after the next second master clock
a switching control pulse generating means 8 comprising a logical sum part that generates a switching control pulse having a pulse width that falls at the rising point of the master clock; and when the switching control pulse is at L level, selects the first master clock; 1. A toothless clock generation circuit comprising a switching means 9 which selects and outputs a second master clock when the clock is at H level.