JPH10150361A - Frequency divider and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparison frequency divider and a PLL circuit that prevents malfunction of a prescaler by eliminating an input delay of a module control signal to the prescaler with respect to an output signal of the prescaler. SOLUTION: A control circuit 25 generates a module control signal MD3 based on a count signal of a main counter 22 and a swallow counter 23. The control circuit 25 generates a module control signal MD3 having a pulse width equal to a frequency division operation time of the swallow counter 23 based on a 2nd count signal MD outputted from the swallow counter 23 and an output signal Pout of a prescaler 24 and sets a time for at least one period of the output signal Pout of the prescaler 24 in advance as a delay margin of the 2nd count signal Pout by inputting the module control signal MD3 to the prescaler 24 as a trigger which is a start point of a period of the output signal Pout of the prescaler 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL which operates to match an output signal frequency to a set frequency.
The present invention relates to a comparison frequency divider used in a circuit.

In recent years, PLL circuits have been used in mobile communication devices such as mobile phones and mobile phones. Such PL
The operating frequency of the L circuit tends to be higher and more likely to cause a malfunction as the operating frequency increases. Therefore, it is necessary to prevent malfunction from occurring regardless of the increase in operating frequency.

[0003]

2. Description of the Related Art FIG. 6 shows an example of a conventional PLL circuit. The oscillator 1 outputs a reference clock signal CK having a natural frequency based on the oscillation of the crystal oscillator to the reference frequency divider 2. The reference frequency divider 2 is configured by a counter circuit, divides the frequency of the reference clock signal CK based on the frequency division ratio set by the shift register 3, and outputs the reference signal fr to the phase comparator 4.

[0006] A comparison signal fp is output from the comparison frequency divider 5 to the phase comparator 4. Then, the phase comparator 4 outputs pulse signals ΦR and ΦP corresponding to the frequency difference and the phase difference between the reference signal fr and the comparison signal fp to the charge pump 6.

[0005] The charge pump 6 outputs an output signal SCP to a low-pass filter (hereinafter referred to as LPF) 7 based on the pulse signals ΦR and ΦP output from the phase comparator 4.

The output signal SCP includes a direct current component including a pulse component, and the direct current component rises and falls with the frequency fluctuation of the pulse signals ΦR and ΦP. It changes based on the phase difference.

The LPF 7 smoothes the output signal SCP of the charge pump 6 and removes the high-frequency component from the output signal SCP.
The LPF is output to a voltage controlled oscillator (hereinafter referred to as VCO) 8.

The VCO 8 outputs an output signal fvco having a frequency corresponding to the voltage value of the output signal SLPF of the LPF 7 to an external circuit and to the comparison frequency divider 5. The comparison frequency divider 5 is of a pulse swallow type, and includes a prescaler 9, a main counter 10, a swallow counter 11, and a control circuit 12.

The output signal fvco of the VCO 8 is input to the prescaler 9 which divides the frequency of the input signal fvco by M or M + 1 and outputs the output signal Pout to the main counter 10 and the swallow counter 11. Output.

The swallow counter 11 frequency-divides the output signal Pout of the prescaler 9 by A and outputs the output signal to the control circuit 12. The control circuit 12 outputs, for example, an H-level module control signal MD to the prescaler 9 based on the frequency-divided signal of the swallow counter 11, and the prescaler 9 converts the input signal fvco to M based on the module control signal MD. Divided output signal Pout
Is output.

While the swallow counter 11 is counting A pulses, the control circuit 12 outputs an L level module control signal MD, for example, and the prescaler 9 outputs an input based on the module control signal MD. An output signal Pout obtained by dividing the signal fvco by M + 1 is output.

The frequency division ratio of the main counter 10 is set by the shift register 3 and the output signal Pout of the prescaler 9 is frequency-divided by N, and the comparison signal f is sent to the phase comparator 4.
Output as p. The frequency-divided signal of the main counter 10 is output to the control circuit 12, and the control circuit 12 outputs a start signal to the swallow counter 11 every time the main counter 10 divides the input signal Pout by N.

Therefore, in the PLL circuit, the swallow counter 11 operates every time the main counter 10 divides the output signal Pout of the prescaler 9 by N, and the prescaler 9
Is counted.

The specific structure of the prescaler 9 will be described with reference to FIG. The output signal fvco of the VCO 8 is supplied to the flip-flop circuits FF1 to FF1 through the buffer circuit 13.
The clock signal CK is input to the FF3.

The output signal XQ of the flip-flop circuit FF1 is input to the flip-flop circuit FF2 as data D, and the output signal Q of the flip-flop circuit FF2 is input to the flip-flop circuit FF3 as data D.

The flip-flop circuits FF2 and FF3
Is input to the OR circuit 14a, and the OR signal
The output signal of the circuit 14a is the flip-flop circuit F
The data D is input to F1.

The output signal XQ of the flip-flop circuit FF1 is input to the flip-flop circuit FFL1 as a clock signal CK. The output signal XQ of the flip-flop circuit FFL1 is input to the flip-flop circuit FFL1 as data D.

The output signal Q of the flip-flop circuit FFL1 is input to the flip-flop circuit FFL2 as a clock signal CK. The flip-flop circuit F
The output signal XQ of FL2 is supplied to the flip-flop circuit FF
L2 is input as data D, and output signal Q is input to flip-flop circuit FFL3 as clock signal CK.

The output signal XQ of the flip-flop circuit FFL3 is input to the flip-flop circuit FFL3 as data D, and the output signal Q is input to the flip-flop circuit FFL4 as a clock signal CK.

The output signal XQ of the flip-flop circuit FFL4 is input to the flip-flop circuit FFL4 as data D, and the output signal Q is output via the buffer circuit 15 as the output signal Pout.

The flip-flop circuits FFL1-FFL
The output signal Q of L4 is input to the OR circuit 14b. The OR circuit 14b has the module control signal M
D is input.

The output signal of the OR circuit 14b is input to the flip-flop circuit FF3 as a control signal M. When the control signal M becomes L level, the flip-flop circuit FF3 performs a normal operation and the control signal M
Becomes H level, the output signal Q of the flip-flop circuit FF3 is fixed at L level.

FIG. 8 shows the operation of the prescaler 9 configured as described above. When the output signal fvco of the VCO 8 is input, the operation of the flip-flop circuits FF1 and FF2 causes the input signal fvc to be input from the flip-flop circuit FF1.
An output signal XQ obtained by dividing o by 4 is output. Further, the phase of the output signal Q of the flip-flop circuit FF2 is delayed from the output signal XQ of the flip-flop circuit FF1 by 1/4 cycle, that is, by one cycle of the input signal fvco.

The output signal Q of the flip-flop circuit FFL1 is obtained by dividing the output signal XQ of the flip-flop circuit FF1 by 2
The signal is obtained by dividing the frequency of the input signal fvco by 8, and the output signal Q of the flip-flop circuit FFL2 is a signal obtained by dividing the input signal fvco by 16.

The output signal Q of the flip-flop circuit FFL3 is a signal obtained by dividing the input signal fvco by 32, and the output signal Q of the flip-flop circuit FFL4 is a signal obtained by dividing the input signal fvco by 64.

If the module control signal MD is at L level, the control signal M output from the OR circuit 14b is determined based on the output signals Q of the flip-flop circuits FFL1 to FFL4.

That is, after the prescaler 9 starts counting the input signal fvco, the input signal fvco
Until the 60 pulses of vco are counted, any one of the output signals Q of the flip-flop circuits FFL1 to FFL4 is at the H level, so that the control signal M is at the H level.

Then, the output signal Q of the flip-flop circuit FF3 is fixed at L level. Input signal fvc
When the 60 pulses o are counted, the output signals Q of the flip-flop circuits FFL1 to FFL4 all go to L level, so that the control signal M goes to L level.

Then, the flip-flop circuit FF3 is activated, and the flip-flop circuit FF3 outputs the output signal Q of the flip-flop circuit FF2 to the input signal fvco of the input signal fvco.
An output signal Q delayed by a period is output.

Then, the output signal XQ of the flip-flop circuit FF1 rises with a delay of one cycle of the input signal fvco from the fall of the output signal Q of the flip-flop circuit FF3.

Output signal X of flip-flop circuit FF1
Based on the rise of Q, flip-flop circuit FF
The output signals Q of L1 to FFL4 rise to H level,
The control signal M rises to the H level. Then, a new counting operation is started.

With such an operation, when the module control signal MD is at the L level, the prescaler 9 performs an M + 1 frequency division operation (M = 64). When the module control signal MD is at the H level, the control signal M output from the OR circuit 14b is fixed at the H level, so that the flip-flop circuit FF3 is inactivated, and the output signal Q becomes L
Fixed to level.

Therefore, if the module control signal MD is at the H level, the prescaler 9 performs the M frequency division operation (M = 64).
I do.

[0034]

In the above-described PLL circuit, the reference signal fr and the comparison signal fp may be used depending on the specifications.
And the frequency of the output signal frequency fvco of the VCO 8 must be increased.

However, the output signal fvco of the VCO 8
, The delay of the module control signal MD input from the control circuit 12 to the prescaler 9 becomes relatively large with respect to the count operation of the prescaler 9,
In some cases, the prescaler 9 cannot perform a normal counting operation.

That is, in FIG. 8, the prescaler 9
Starts the M frequency division operation, the module control signal M
If there is no delay at the input of D to the prescaler 9, the module control signal MD having no such delay
j rises at the flip-flop circuits FFL1 to FFL
This is the same as the rise of FL4.

However, in reality, the swallow counter 11,
Due to the operation delay time of the main counter 10 and the control circuit 12 and the delay time due to the wiring capacitance between the control circuit 12 and the prescaler 9, the rise of the module control signal MD is caused by the flip-flop circuits FF 1 and FFL 1 to FFL 1
Delay from the rising edge of the output signal of FL4.

This delay time becomes relatively large as the frequency of the input signal fvco becomes high. However, if the module control signal MD rises before the rise of the output signal Q of the flip-flop circuit FF3, there is a problem. There is no.

However, if the module control signal MD rises later than the rise of the output signal Q of the flip-flop circuit FF3 due to the delay time td due to the rise in the frequency of the input signal fvco, the M frequency division operation should be performed. There is a problem that the M + 1 frequency division operation is performed and the M frequency division operation is not performed normally.

An object of the present invention is to eliminate a delay in input of a module control signal to a prescaler with respect to an output signal of the prescaler, thereby preventing a malfunction of the prescaler and making it possible to easily increase an operating frequency. And a PLL circuit.

[0041]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, based on the module control signal MD3, the prescaler 24 outputs an output signal Pout obtained by dividing the input signal fvco by different division ratios. The main counter 22 outputs the output signal Pout of the prescaler 24.
Is output at a first frequency division ratio to output a first count signal fp. The swallow counter 23 is provided with the prescaler 2.
4 is output at a second frequency division ratio different from the first frequency division ratio to output a second count signal MD. The control circuit 25 generates the module control signal MD3 based on the count signals of the main counter 22 and the swallow counter 23. The control circuit 25
Is the second count signal MD output from the swallow counter 23 and the output signal Pout of the prescaler 24.
And generates a module control signal MD3 having a pulse width equal to the dividing operation time of the swallow counter 23, and outputs the module control signal MD3 to the prescaler 2.
4 is input to the prescaler 24 by using the start point of the cycle of the output signal Pout as a trigger, so that at least one cycle of the output signal Pout of the prescaler 24 is set in advance as a delay margin of the second count signal MD. .

According to a second aspect of the present invention, the control circuit includes a trigger generation circuit for generating a trigger signal obtained by dividing the output signal of the prescaler by two, the second count signal, and the trigger signal. A module control signal generation circuit that generates a module control signal having a time width equal to the count signal in synchronization with the start point of the cycle of the output signal of the prescaler and outputs the module control signal to the prescaler.

According to a third aspect of the present invention, the division ratio of the swallow counter is set based on division ratio setting data output from a shift register, and the lowest order of the division ratio setting data input to the swallow counter is set. Bit is "0"
Fixed, the swallow counter can set only the even division ratio, the module control signal generation circuit,
Based on the trigger signal input as a clock signal, a first flip-flop circuit that latches and outputs the second count signal input as input data, and the least significant bit of the frequency division ratio setting data is Entered,
Activated only when the least significant bit is “1”, and latches an output signal of the first flip-flop circuit input as input data based on an output signal of the prescaler input as a clock signal. A second flip-flop circuit that outputs the data and a logic circuit that outputs the logical sum of the output signals of the first and second flip-flop circuits as the module control signal.

According to a fourth aspect of the present invention, when the frequency division ratio of the swallow counter is set to "1", the control circuit outputs a pulse signal for one cycle of the prescaler to the logic circuit. Provided with a circuit.

In a fifth aspect, a reference frequency divider for dividing a reference clock signal to generate a reference signal, a phase comparator for comparing the phases of the reference signal and the comparison signal, and an output of the phase comparator A charge pump that converts a signal into a current signal,
A low-pass filter that smoothes the output current of the charge pump, a voltage-controlled oscillator that outputs a pulse signal having a frequency based on the output voltage of the low-pass filter, and a frequency-divided output signal of the voltage-controlled oscillator, which is used as the comparison signal. A PLL circuit comprising a comparison divider for outputting the signal is provided with the comparison divider of claim 1.

(Function) In the first and fifth aspects, a pulse equal to the frequency dividing operation time of the swallow counter 23 is based on the second count signal MD output from the swallow counter 23 and the output signal Pout of the prescaler 24. A module control signal MD3 having a width is generated, and the module control signal MD3 is input to the prescaler 24 with the start point of the cycle of the output signal Pout of the prescaler 24 as a trigger.

According to the second aspect, based on a trigger signal obtained by dividing the output signal of the prescaler by 2, a module control signal synchronized with the start point of the cycle of the output signal of the prescaler and having a time width equal to the count signal of the swallow counter is generated. Generated and input to the prescaler.

According to the third aspect, the division ratio setting data inputted from the shift register to the swallow counter is inputted except for the least significant bit. Therefore, when an odd division ratio is set by the shift register, the swallow counter is set. The input dividing ratio is an even number of the set value −1. The count signal of the swallow counter is latched by the first flip-flop circuit based on the trigger signal and output to the second flip-flop circuit and the logic circuit. The second flip-flop circuit is activated when the least significant bit of the shift register is 1, and latches and outputs the output signal of the first flip-flop circuit based on the output signal of the prescaler. By the logical sum of the output signals of the first and second flip-flop circuits, a module control signal having a time width equal to the time width of the second count signal when the frequency division operation is performed at the frequency division ratio set by the shift register is obtained. Generated.

In the fourth aspect, when the frequency division ratio setting data output from the shift register is set to 1, the frequency division operation of the swallow counter is stopped, but the second control circuit outputs one cycle of the output signal of the prescaler. A pulse signal having a time width is output to the logic circuit, and a module control signal is generated based on the pulse signal.

[0050]

FIG. 2 shows a comparative frequency divider according to an embodiment of the present invention. The comparison frequency divider of this embodiment includes a shift register 21, a main counter 22,
It comprises a swallow counter 23, a prescaler 24, and first and second control circuits 25 and 26.

The division ratios of the main counter 22 and the swallow counter 23 are set based on a plurality of bits of division ratio setting data output from the shift register 21 as in the conventional example. Note that the least significant bit data of the shift register 21 is not input to the swallow counter 23, and the least significant bit of the frequency division ratio setting data input to the swallow counter 23 is fixed to “0”.

The output signal Pout of the prescaler 24 is supplied to the main counter 22 and the swallow counter 23.
Is entered. The main counter 22 divides the output signal Pout of the prescaler 24 by the set division ratio, and converts the comparison signal fp into a phase comparator and a second control circuit 26.
Output to

The swallow counter 23 divides the output signal Pout of the prescaler 24 by a set dividing ratio,
At the time of the frequency division operation, a control signal MD which becomes H level is output to the first control circuit 25. The swallow counter 23 starts a counting operation based on the input of the comparison signal fp output from the main counter 22.

The comparison signal fp output from the main counter 22 and the division ratio setting data of the swallow counter 23 output from the shift register 21 are input to the second control circuit 26. Then, the second control circuit 26 calculates the inverted value of the least significant bit of the frequency division ratio setting data of the shift register 21, the logical value of the other bits of the frequency division ratio setting data of the swallow counter 23 and the main counter 22. The output signal CNT2 obtained by inverting the logical sum of the output comparison signal fp and the logical value is output to the first control circuit 25.
Output to

That is, when the frequency division ratio of the swallow counter 23 is set to "1", the second control circuit 26 divides the output signal Pout of the prescaler 24 by a predetermined frequency division ratio at every time. To the output signal Pout
An output signal CNT2 which is at H level for a period is output. When the division ratio of the swallow counter 23 is other than "1", the output signal CNT2 of the second control circuit 26 is fixed at the L level.

The prescaler 24 is composed of flip-flop circuits FF1 to FF6 and an OR circuit 27 in the same manner as in the prior art, and outputs an output signal Pout obtained by dividing the output signal fvco of the VCO by 32.

The output signal M of the OR circuit 27 is low, as in the conventional example.
When the level becomes the level, the input data D is output as the output signal Q based on the clock signal CK. When the output signal M of the OR circuit 27 becomes the H level, the output signal Q is fixed to the H level.

The first control circuit 25 includes flip-flop circuits FF7 to FF9, an AND circuit 28,
And a circuit 29. The output signal Pout of the prescaler 24 is input to the T flip-flop circuit FF7 as a clock signal CK. The T flip-flop circuit FF7 outputs to the AND circuit 28 an output signal Q obtained by dividing the output signal Pout of the prescaler 24 by two.

The output signal Q of the flip-flop circuits FF5 and FF6 of the prescaler 24 is input to the AND circuit 28, and the output signal CNT of the AND circuit 28 is input to the AND circuit 28.
1 is a clock signal C supplied to the flip-flop circuit FF8.
Input as K.

The control signal MD output from the swallow counter 23 is input to the flip-flop circuit FF8 as data D, and the data D is latched and output as an output signal Q based on the rise of the clock signal CK. .

The output signal Pout of the prescaler 24 is supplied to the flip-flop circuit FF9 by the clock signal C.
K, and the output signal Q of the flip-flop circuit FF8 is input as data D.

The flip-flop circuit FF9 has
An output signal of the least significant bit of the shift register 21 is input as an input signal M2. When the input signal M2 is at the L level, the flip-flop circuit FF9 outputs the output signal Q at the L level. When the input signal M2 is at the H level, the data D is latched based on the rising of the clock signal CK. And outputs it as an output signal Q.

The output signal Q of the flip-flop circuit FF8 is input to the NOR circuit 29 as a signal MD2.
The output signal of the flip-flop circuit FF9 is also NOR.
Input to the circuit 29. An output signal CNT2 of the second control circuit 26 is input to the NOR circuit 29.

The output signal MD3 of the NOR circuit 29 is
The signal is input to the OR circuit 27 of the prescaler 24. Next, the operation of the comparative frequency divider configured as described above will be described. (1) When the division ratio of the swallow counter 23 is set to “4”.

FIG. 3 shows the operation of the comparison frequency divider when the frequency division ratio of the swallow counter 23 is set to 4. Since the division ratio of the swallow counter 23 is an even number, the output signal of the least significant bit of the shift register 21 is “0”. Then, the input signal M of the flip-flop circuit FF9
2 is at the L level and its flip-flop circuit FF9
Is fixed to the L level. Further, the output signal CNT2 of the second control circuit 26 is also fixed at the L level.

In this state, when the output signal fvco of the VCO is input, the flip-flop circuit FF4 outputs an output signal Q obtained by dividing the input signal fvco by 8, and the flip-flop circuit FF5 outputs the input signal fvco by 16 times. The output signal Q obtained by dividing the frequency is output, and the flip-flop circuit FF6 converts the output signal Q obtained by dividing the input signal fvco by 32 into a prescaler
4 as an output signal Pout. The flip-flop circuit FF7 outputs an output signal Q obtained by dividing the input signal fvco by 64.

Then, each time the output signal Q of the flip-flop circuit FF7 rises, the AND circuit 28 of the first control circuit 25 outputs the output signal CNT1 which is in the same phase as the output signal Q of the flip-flop circuit FF5 and becomes H level. I do.

The swallow counter 23 starts a counting operation based on a start signal output from the main counter 22, outputs an H-level control signal MD until the output signal Pout of the prescaler 24 is divided by four, and After the rotation, the control signal MD at the L level is output until the next start signal is output.

Each time the output signal CNT1 of the AND circuit 28 rises, the flip-flop circuit FF8 outputs the control signal M
D is latched and output as an output signal MD2. The control signal MD is maintained at the H level for four cycles of the output signal Pout of the prescaler 24.

Then, due to the operation delay of the swallow counter 23, the prescaler 24, the wiring capacity between the first control circuit 25 and the swallow counter 23, etc., the control signal MD input to the first control circuit 25 Is delayed, the output signal MD2 of the flip-flop circuit FF8 rises to the H level based on the rise of the output signal CNT1 of the AND circuit 28 synchronized with the rise of the output signal Pout of the prescaler 24, and after four cycles of the output signal Pout A
The output signal MD2 falls to the L level based on the rise of the output signal CNT1 of the ND circuit 28.

Accordingly, the output signal MD2 of the flip-flop circuit FF8 is at the H level only for four cycles from the rise of the output signal Pout of the prescaler 24. When the output signal MD2 of the flip-flop circuit FF8 goes high, the module control signal MD3 output from the NOR circuit 29 goes low. That is, a signal having a phase opposite to that of the output signal MD2 of the flip-flop circuit FF8 is output as the module control signal MD3.

When the module control signal MD3 goes low, the flip-flop circuit FF3 of the prescaler 24
Input signal M of the flip-flop circuit FF4 immediately before the frequency division of the input signal fvco by 32 is completed.
To the L level in synchronization with.

Then, the prescaler 24 performs the +1 frequency dividing operation, that is, the input signal fvc by the same operation as that of the conventional example.
Performs the divide-by-33 operation of o. And such an operation 4
Repeat cycle.

At the point when the prescaler 24 repeats the 33-divided operation for four cycles, the module control signal MD3 returns to the H level based on the fall of the output signal MD2 of the flip-flop circuit FF8.

Then, the input signal M of the flip-flop circuit FF3 is fixed at the H level, and the prescaler 24 starts the operation of dividing the input signal fvco by 32. When the main counter 22 performs a predetermined frequency dividing operation, the above operation is repeated based on a start signal output from the main counter 22. (2) When the frequency division ratio of the swallow counter 23 is set to “3”.

FIG. 4 shows the operation of the comparison frequency divider when the frequency division ratio of the swallow counter 23 is set to 3. Since the division ratio of the swallow counter 23 is an odd number, the output signal of the least significant bit of the shift register 21 becomes "1", that is, the H level. Then, the flip-flop circuit FF
9, the input signal M2 attains the H level, so that the flip-flop circuit FF9 outputs the data D as the output signal Q based on the rise of the output signal Pout of the prescaler 24. Further, the output signal CNT2 of the second control circuit 26 is also fixed at the L level.

In this state, when the output signal fvco of the VCO is input, the flip-flop circuit FF4 outputs the output signal Q obtained by dividing the input signal fvco by 8, and the flip-flop circuit FF5 outputs the input signal fvco by 16 times. The output signal Q obtained by dividing the frequency is output, and the flip-flop circuit FF6 converts the output signal Q obtained by dividing the input signal fvco by 32 into the prescaler 2.
4 as an output signal Pout. The flip-flop circuit FF7 outputs an output signal Q obtained by dividing the input signal fvco by 64.

Then, every time the output signal Q of the flip-flop circuit FF7 rises, the AND circuit 28 of the first control circuit 25 outputs the output signal CNT1 which is in the same phase as the output signal Q of the flip-flop circuit FF5 and becomes H level. I do.

Since the data of the least significant bit of the shift register 21 is not input to the swallow counter 23, when the division ratio is set to "3", the shift register 2
The output data of the lower 2 bits of 1 is “11”, but the input data of the swallow counter 23 is “10”. Therefore, the division ratio of the swallow counter 23 is actually set to “2”.

The swallow counter 23 starts a counting operation based on a start signal output from the main counter 22, outputs an H-level control signal MD until the output signal Pout of the prescaler 24 is divided by two, and After the rotation, the control signal MD at the L level is output until the next start signal is output.

Each time the output signal CNT1 of the AND circuit 28 rises, the flip-flop circuit FF8 outputs the control signal M
D is latched and output as an output signal MD2. The control signal MD is maintained at the H level for two cycles of the output signal Pout of the prescaler 24.

Then, due to the operation delay of the swallow counter 23, the prescaler 24, the wiring capacity between the first control circuit 25 and the swallow counter 23, etc., the control signal MD input to the first control circuit 25 Is delayed, the output signal MD2 of the flip-flop circuit FF8 rises to the H level based on the rise of the output signal CNT1 of the AND circuit 28 in synchronization with the rise of the output signal Pout of the prescaler 24, and after two cycles of the output signal Pout A
The output signal MD2 falls to the L level based on the rise of the output signal CNT1 of the ND circuit 28.

Therefore, the output signal MD2 of the flip-flop circuit FF8 is at the H level only for two cycles from the rise of the output signal Pout of the prescaler 24. When the output signal MD2 of the flip-flop circuit FF8 goes high, the module control signal MD3 output from the NOR circuit 29 goes low.

Output signal M of flip-flop circuit FF8
When D2 becomes H level, the output signal Q of the flip-flop circuit FF9 rises to H level based on the next rise of the output signal Pout of the prescaler 24, and is maintained at H level for two cycles of the output signal Pout.

Then, it takes three cycles of the output signal Pout of the prescaler 24 from the rise of the output signal MD2 of the flip-flop circuit FF8 to the fall of the output signal Q of the flip-flop circuit FF9.

As a result, the module control signal MD3 output from the NOR circuit 29 becomes L level for three cycles from the rise of the output signal Pout of the prescaler 24. When the module control signal MD3 becomes L level, the input signal M of the flip-flop circuit FF3 of the prescaler 24 becomes L level in synchronization with the output signal Q of the flip-flop circuit FF4 immediately before completing the frequency division of the input signal fvco by 32. Become.

Then, the prescaler 24 performs the +1 frequency dividing operation, that is, the input signal fvc by the same operation as that of the conventional example.
Performs the divide-by-33 operation of o. And such an operation 3
Repeat cycle.

When the prescaler 24 repeats the 33-divided operation for three cycles, the module control signal MD3 returns to the H level in synchronization with the fall of the output signal Q of the flip-flop circuit FF9.

Then, the input signal M of the flip-flop circuit FF3 is fixed at the H level, and the prescaler 24 starts the operation of dividing the input signal fvco by 32. Then, when a predetermined frequency dividing operation is performed by the main counter 22, the above operation is repeated based on a start signal output from the main counter 22. (3) When the frequency division ratio of the swallow counter 23 is set to “1”.

FIG. 5 shows the operation of the comparison frequency divider when the frequency division ratio of the swallow counter 23 is set to 1 by the shift register 21. Since the division ratio setting data input to the swallow counter 23 is “0”, the control signal MD output from the swallow counter 23 is fixed at L level.

The output signal of the least significant bit of the shift register 21 becomes "1", that is, H level, and the input signal M2 of the flip-flop circuit FF9 becomes H level.
The data D is output as the output signal Q based on the rise of the output signal Pout.

However, since control signal MD is fixed at L level, output signal MD2 of flip-flop circuit FF8 is also fixed at L level, and flip-flop circuit F
The output signal Q of F9 is also fixed at the L level.

In this state, when the output signal fvco of the VCO is input, the flip-flop circuit FF4 outputs an output signal Q obtained by dividing the input signal fvco by 8, and the flip-flop circuit FF5 outputs the input signal fvco of 16 times. The output signal Q obtained by dividing the frequency is output, and the flip-flop circuit FF6 converts the output signal Q obtained by dividing the input signal fvco by 32 into a prescaler
4 as an output signal Pout. The flip-flop circuit FF7 outputs an output signal Q obtained by dividing the input signal fvco by 64.

The second control circuit 26 is a swallow counter 2
When the frequency division ratio of 3 is set to "1", every time the main counter 22 divides the output signal Pout of the prescaler 24 by a predetermined frequency division ratio, the output signal Pout becomes H level for one cycle of the output signal Pout. The output signal CNT2 is output.

When the output signal CNT2 of the second control circuit 26 goes high, the module control signal MD3 output from the NOR circuit 29 goes low. As a result, N
Module control signal MD3 output from OR circuit 29
Goes low for one cycle of the output signal Pout of the prescaler 24.

When the module control signal MD3 goes low, the flip-flop circuit FF3 of the prescaler 24
Input signal M of the flip-flop circuit FF4 immediately before the frequency division of the input signal fvco by 32 is completed.
To the L level in synchronization with.

Then, the prescaler 24 operates in the same manner as in the above-mentioned conventional example, by a +1 frequency division operation, that is, the input signal fvc
o is performed for one cycle. Prescaler 24 is 3
After performing the frequency dividing operation for one cycle, the module control signal MD
3 returns to the H level based on the fall of the output signal CNT2 of the second control circuit 26.

Then, the input signal M of the flip-flop circuit FF3 is fixed at the H level, and the prescaler 24 starts the operation of dividing the input signal fvco by 32. When a predetermined frequency division operation is performed by the main counter 22, the above operation is repeated based on the output signal CNT2 output from the second control circuit 26.

In the comparative frequency divider configured as described above,
The following operation and effect can be obtained. (A) When the frequency division ratio of the swallow counter 23 is set to “2” or more, the module control signal MD3 having the same time width as the control signal MD output from the swallow counter 23 is supplied to the rising edge of the output signal Pout of the prescaler 24. In synchronization with the prescaler 24. Then, the control signal M output from the swallow counter 23
Even if D is delayed, the module control signal MD3 input to the prescaler 24 becomes the output signal P of the prescaler 24.
The signal is input in synchronization with the rise of out, and is maintained at the L level for the same time as the time when the swallow counter 23 performs the predetermined frequency division operation. The input is stopped in synchronization with the rise of the output signal Pout of the prescaler 24.

Therefore, the output signal Pou of the prescaler 24
In synchronization with the rise of t, the prescaler 23
Since the 1-frequency division operation is started and the M + 1 frequency division operation is performed with the same time width as that during the time when the swallow counter 23 performs the predetermined frequency division operation, the miss counting operation of the prescaler 24 can be prevented. (B) As shown in FIGS. 3 and 4, the swallow counter 2
When the frequency division ratio of “3” is set to “2” or more, even if the rise of the control signal MD is delayed by the delay time t1 due to the operation of the swallow counter 23 and the wiring capacity, the next rise of the output signal CNT1 of the AND circuit 28. T2, that is, the time corresponding to two cycles of the output signal Pout of the prescaler 24 is a margin for the delay of the control signal MD. Therefore, it is possible to secure a sufficient margin for the delay of the control signal MD and prevent the miss counting operation of the prescaler 24. (C) The output data of the least significant bit of the shift register 21 for setting the frequency division ratio of the swallow counter 23 is input to the flip-flop circuit FF9. Then, as shown in FIG. 3, when the division ratio of the swallow counter 23 is set to an even number, the operation of the flip-flop circuit FF9 is invalidated, and the output signal CNT1 of the AND circuit 28 and the control signal M
Based on D, a module control signal MD3 having a time width equal to the frequency dividing operation time of the swallow counter 23 is generated.

When the division ratio of the swallow counter 23 is set to an odd number larger than 1, the swallow counter 23
Since the least significant bit of the shift register 21 is not input, the frequency division operation is performed at an even frequency division ratio of the set value -1. Also, the flip-flop circuit FF9 operates based on the output signal Pout of the prescaler 24, and the flip-flop circuits FF8 and FF9 perform a shift resist operation.

Then, as shown in FIG. 4, when the frequency division ratio is set to "3", for example, the swallow counter 23 performs an operation of dividing the output signal Pout of the prescaler 24 by 2, and the control signal MD outputs the output signal Pout. It becomes H level for two cycles of Pout. Based on the control signal MD, a module control signal MD3 for three cycles of the output signal Pout is generated by the operations of the flip-flop circuits FF8, FF9 and the NOR circuit 29.

Therefore, regardless of whether the division ratio of the swallow counter 23 is set to an even number or an odd number, the prescaler 2
4 can be prevented. (D) When the division ratio of the swallow counter 23 is set to “1” by the shift register 21, the swallow counter 2
3 performs no frequency division operation, but every time the main counter 22 performs a predetermined frequency division operation, the output signal CNT2 output from the second control circuit 26 delays the output signal CNT2 by a delay time t3. Thus, the module control signal MD3 for one cycle of the output signal Pout of the prescaler 24 is generated.

Then, in the prescaler 24, every time the main counter 22 performs a predetermined frequency dividing operation, a +1 frequency dividing operation is performed, which is substantially the same as the case where the frequency dividing ratio of the swallow counter 23 is set to "1". Is performed. Therefore, the frequency division ratio of the swallow counter 23 can be set to “1”.

[0105]

As described in detail above, the present invention eliminates the delay in inputting the module control signal to the prescaler with respect to the output signal of the prescaler, thereby preventing a malfunction of the prescaler and easily raising the operating frequency. A possible comparison divider and PLL circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a comparison frequency divider according to one embodiment.

FIG. 3 is a timing waveform chart showing an operation of one embodiment.

FIG. 4 is a timing waveform chart showing an operation of one embodiment.

FIG. 5 is a timing waveform chart showing an operation of one embodiment.

FIG. 6 is a block diagram illustrating a PLL circuit.

FIG. 7 is a circuit diagram showing a conventional prescaler.

FIG. 8 is a timing waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 22 Main counter 23 Swallow counter 24 Prescaler 25 Control circuit fvco input signal fp First count signal MD Second count signal MD3 Module control signal Pout Output signal of prescaler

Claims (5)

[Claims] 1. A prescaler for outputting an output signal obtained by dividing an input signal at a different dividing ratio based on a module control signal, and a first scaler dividing an output signal of the prescaler at a first dividing ratio. A main counter that outputs a count signal; a swallow counter that outputs a second count signal obtained by dividing the output signal of the prescaler by a second division ratio different from the first division ratio; and the main counter And a control circuit that generates the module control signal based on the count signal of the swallow counter, wherein the control circuit includes: a second count signal output from the swallow counter; and a prescaler. Generating a module control signal having a pulse width equal to the frequency dividing operation time of the swallow counter based on the output signal of By inputting the control signal to the prescaler with the start point of the cycle of the output signal of the prescaler as a trigger, the time for at least one cycle of the output signal of the prescaler is preset as a delay margin of the second count signal. A frequency divider characterized by the following. 2. A control circuit comprising: a trigger generation circuit for generating a trigger signal obtained by dividing the output signal of the prescaler by 2; an output of the prescaler based on the second count signal and the trigger signal. The module control signal generation circuit according to claim 1, further comprising: a module control signal generation circuit that generates a module control signal having a time width equal to the count signal in synchronization with a start point of a signal cycle and outputs the module control signal to the prescaler. Divider. 3. The division ratio of the swallow counter is set based on division ratio setting data output from a shift register, and the least significant bit of the division ratio setting data input to the swallow counter is “3”. 0 "
The swallow counter can set only an even division ratio, and the module control signal generation circuit latches the second count signal input as input data based on the trigger signal input as a clock signal. And a first flip-flop circuit for receiving and outputting the least significant bit of the frequency division ratio setting data, and activating only when the least significant bit is “1”, and inputting the clock as a clock signal. A second flip-flop circuit that latches and outputs an output signal of the first flip-flop circuit input as input data based on the output signal of the first and second flip-flop circuits; and an output signal of the first and second flip-flop circuits. 3. A logic circuit for outputting a logical sum of the above as the module control signal. Peripheral. 4. The control circuit includes a second control circuit that outputs a pulse signal for one cycle of the prescaler to the logic circuit when a division ratio of the swallow counter is set to “1”. The frequency divider according to claim 3, wherein 5. A reference frequency divider that divides a reference clock signal to generate a reference signal, a phase comparator that compares the phases of the reference signal and a comparison signal, and outputs an output signal of the phase comparator as a current. A charge pump that converts the signal into a signal; a low-pass filter that smoothes the output current of the charge pump; a voltage-controlled oscillator that outputs a pulse signal having a frequency based on the output voltage of the low-pass filter; And a comparison frequency divider that divides the input signal by a different frequency division ratio based on a module control signal. A prescaler that outputs a first count signal obtained by dividing an output signal of the prescaler at a first frequency division ratio; and a prescaler that outputs a first count signal. A swallow counter that outputs a second count signal obtained by dividing the output signal of the first division ratio at a second division ratio different from the first division ratio, based on count signals of the main counter and the swallow counter, A control circuit for generating a module control signal, wherein the control circuit, based on a second count signal output from the swallow counter, and an output signal of a prescaler, the dividing operation time of the swallow counter, A PLL circuit which generates a module control signal having an equal pulse width, and inputs the module control signal to the prescaler with a start point of a cycle of an output signal of the prescaler as a trigger.