JP2877185B2 - Clock generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a clock generator.
In particular, the present invention relates to a clock generator of a data interface circuit using a plurality of clock signals which are different from the clock frequency of input data and whose clock frequencies have an integer ratio.

[0002]

2. Description of the Related Art Conventionally, in a data interface circuit of this kind, a clock generator is provided with a one-stage PLL (P
(Hase Locked Loop) circuit. That is, as shown in FIG. 2, the data interface circuit includes a 1 / N3 frequency divider 7, a PLL circuit 8,
/ N2 frequency divider 9, frame counters 4 and 5, and link / reset circuit 6.

In the above data interface circuit, an input clock signal of frequency f0 is divided by a 1 / N3 divider 7 to generate a clock signal of frequency f4, and a PLL circuit 8
To enter. The PLL circuit 8 generates a clock signal having a frequency f2 (f4 <f2) from the frequency-divided output (frequency f4) of the 1 / N3 frequency divider 7. The clock signal of the frequency f2 generated by the PLL circuit 8 is divided by the 1 / N2 frequency divider 9 into the frequency f2.
3 (f3 <f2). Here, the PLL circuit 8 includes a phase comparator 81, a loop filter 82, a voltage controlled oscillator 83, and a 1 / N4 frequency divider 84.

The frame counter 4 operates on the basis of an input clock signal having a frequency f0, and the frame counter 5 operates on a 1 / N
It operates based on the clock signal of frequency f3 divided by the frequency divider 9. The clock signal of frequency f2 generated by the PLL circuit 8 and the clock signal of frequency f3 divided by the 1 / N2 frequency divider 9 are both used for conversion between parallel data and serial data, that is, for parallel-to-serial conversion. Can be

The link / reset circuit 6 is designed to completely match the phase of the input data frame with the phase of the output data frame at a certain point in the frame. And a frame pulse from the output data frame counter 5 to detect a phase shift of the frame. When the phase shift is detected, the reset pulse is output to the 1 / N2 frequency divider 9 and the 1 / N4 frequency divider. 84 and a reset pulse to the frame counter 5.

1 / N 2 divider 9 and 1 / N 4 divider 84
Are reset by a reset pulse from the link / reset circuit 6, respectively, so that a clock signal of frequency f3 input to the frame counter 5 from the 1 / N2 frequency divider 9 and an input clock signal of frequency f0 input to the frame counter 4 Is synchronized with Therefore, the phase of the frame of the input data coincides with the phase of the frame of the output data at a certain point in the frame.

[0007]

In the above-mentioned conventional data interface circuit, the frequency of the output clock signal is determined irrespective of the frequency of the input clock signal.
Therefore, the greatest common divisor between the frequency of the input clock signal and the frequency of the output clock signal of the PLL circuit is considerably smaller than the frequency of the input clock signal and the frequency of the output clock signal of the PLL circuit.

In a high-constant PLL circuit in which the ratio between the input frequency of the phase comparator and the oscillation frequency of the voltage-controlled oscillator becomes a large value, the sensitivity of the voltage-controlled oscillator that outputs a high-frequency clock signal becomes extremely high. The stability of the circuit with respect to changes in the surrounding environment (for example, the magnitude of noise) is significantly reduced.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to provide a clock generator capable of lowering the sensitivity of a voltage controlled oscillator and improving the stability of a circuit against changes in the surrounding environment. Is to do.

[0010]

SUMMARY OF THE INVENTION A clock generator according to the present invention differs from a clock frequency of input data and is different from each other.
The first and second clock frequencies of which have an integer ratio relationship
Parallel data and serial data are
Clock of the data interface circuit that
A clock frequency of the input data.
Based on the first clock for the low-frequency parallel data.
A first phase locked loop circuit for generating a lock signal;
The first clock generated by the first phase locked loop circuit.
A higher frequency than the first clock signal based on the clock signal.
Generating a second clock signal for the serial data
A second phase locked loop circuit .

[0011]

[0012]

First, a first-stage PLL circuit generates a clock signal for low-frequency parallel data from an input clock signal, and a second-stage PLL circuit generates a clock signal for high-frequency serial data from the output of the first-stage PLL circuit. A clock signal is generated.

Thus, the loop constant of the PLL circuit can be made smaller than before, so that the sensitivity of the voltage controlled oscillator can be lowered and the stability of the PLL circuit can be improved. When the stability of these PLL circuits increases, the PLL circuits are more resistant to external disturbance (noise) and the like, and the S / N ratio of the output clock signal is improved.

Further, by adopting the above circuit configuration, a method of resetting the phase synchronization in the frame cycle can be performed by resetting only the 1 / N1 frequency divider in one PLL circuit, and the circuit configuration is simplified. Is done.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a data interface circuit according to an embodiment of the present invention includes a 1 / N0 frequency divider 1 and a PLL.
It comprises circuits 2 and 3, frame counters 4 and 5, and a link / reset circuit 6.

The PLL circuit 2 includes a phase comparator 21, a loop filter 22, a power supply control oscillator 23, and a 1 / N1 frequency divider 24. Also, the PLL circuit 3
Similarly to the LL circuit 2, the phase comparator 31, the loop filter 32, the power supply control oscillator 33, and the 1 / N1 frequency divider 34
It is composed of

The PLL circuit 2 generates a clock signal of a frequency f3 from a clock signal of a frequency f1 obtained by dividing an input clock signal of a frequency f0 by a 1 / N0 divider 1, and converts the clock signal to the PLL circuit 2. The signals are output to the frame counter 5, the 1 / N1 frequency divider 24 and the outside, respectively. The PLL circuit 3 generates a clock signal of frequency f2 (f2> f3) from the clock signal of frequency f3 from the PLL circuit 2,
The clock signal is output to the outside.

The frame counter 4 operates based on an input clock signal having a frequency f0, and the frame counter 5 operates as a PLL.
It operates based on the clock signal of frequency f3 generated by the circuit 2. Also, the frequency f generated by the PLL circuits 2 and 3
The clock signals 3 and f2 are both used for conversion between parallel data and serial data, that is, for parallel-to-serial conversion.

The link / reset circuit 6 sets a frame pulse from the input data frame counter 4 in order to completely match the phase of the input data frame with the phase of the output data frame at a certain point in the frame. And a frame pulse from the output data frame counter 5 to detect a phase shift of the frame. When the phase shift is detected, a reset pulse is output to the 1 / N1 frequency divider 24 and the reset pulse is output. Is output to the frame counter 5.

Since the 1 / N 1 divider 24 is reset by the reset pulse from the link reset circuit 6, 1 / N 1
The clock signal of frequency f3 generated by the voltage controlled oscillator 23 and input to the frame counter 5 based on the output of the 1 frequency divider 24 is synchronized with the input clock signal of frequency f0 input to the frame counter 4. . Therefore, the phase of the frame of the input data coincides with the phase of the frame of the output data at a certain point in the frame.

The operation of the embodiment of the present invention will be described with reference to FIG. The PLL circuit 2 generates an output of a frequency f3 which is N1 times the frequency of the clock signal obtained by dividing the frequency of the input clock signal of the frequency f0 by the 1 / N0 frequency divider 1 and which is N1 times. The output of the PLL circuit 2 is used as a parallel data clock.

The PLL circuit 3 has a frequency f0 PLL.
An output having a frequency f2 N2 times the phase locked to the output of the circuit 2 is generated. The output of the PLL circuit 3 is used as a serial data clock.

The frequency division ratios N0 and P of these 1 / N0 frequency dividers 1
The dividing ratio N1 of the LL circuit 2 and the dividing ratio N of the PLL circuit 3
2 and the frequency division ratio N3 of the conventional 1 / N3 frequency divider and the frequency division ratio N4 of the PLL circuit, the following relationship holds: N0 * N4 = N1 * N2 * N3 (1) .

In order for the clock generator according to one embodiment of the present invention to be more stable than the conventional clock generator, the following condition is required: N1 <N4 (2).

[0026]

For example, the frequency f0 is 25 MHz, the frequency f2 is 136.5 MHZ, and the frequency f3 is 19.5 MHz.
If the frequency is Hz, the frequency f1 which is the greatest common divisor between the frequency f0 and the frequency f2 is 500 kHz.

Therefore, the frequency division ratio N0 of the 1 / N0 frequency divider 1 is 50, the frequency division ratio N1 of the PLL circuit 2 is 39, and the PLL circuit 3
Of the conventional 1 / N3 divider is N3.
Is 50, the division ratio N4 of the PLL circuit is 273,
Equations (1) and (2) are satisfied respectively.

As described above, the dividing ratio N 1 of the PLL circuit 2
(= 39) and the frequency dividing ratio N2 (= 7) of the PLL circuit 3 can be made much smaller than the frequency dividing ratio N4 (= 273) of the conventional PLL circuit.

Since the frame pulse is output only from the frame counter 4 at the time of starting, the link reset circuit 6 generates a reset pulse in response to the frame pulse output from the frame counter 4 first.
The 1 / N1 frequency divider 24 in the PLL circuit 2 is reset, and the frames of the frame counters 4 and 5 are completely matched at a certain point in the frame.

Thereafter, the link / reset circuit 6 detects the phase shift of the frame pulse of each of the frame counters 4 and 5, and when the phase shift is detected, outputs a reset pulse again to output the reset pulse in the PLL circuit 2. 1 / N1 divider 24
Reset.

As described above, the first-stage PLL circuit 2 first generates a low-frequency parallel data clock signal from the input clock signal having the frequency f0,
By generating a clock signal for high-frequency serial data from the output of the first-stage PLL circuit 2 in the circuit 3, the loop constants of the PLL circuits 2 and 3 can be made smaller than before.

Thus, the voltage controlled oscillators 23, 33
Can be reduced, and the stability of the PLL circuits 2 and 3 against changes in the surrounding environment can be improved.
When the stability of the PLL circuits 2 and 3 increases, the PLL circuits 2 and 3 become strong against external disturbance (noise) and the like, and the S / N ratio of the output clock signal can be improved.

Also, by adopting the circuit configuration as described above, a method of resetting the phase synchronization in the frame cycle can be performed by resetting only the 1 / N1 frequency divider 24 in the PLL circuit 2, and the circuit configuration can be reduced. It can be simplified.

[0035]

As described above, according to the clock generator of the present invention, the first clock is generated based on the clock frequency of the input data.
A first phase-locked loop circuit for generating a clock signal, and a second clock signal having a higher frequency than the first clock signal based on the first clock signal generated by the first phase-locked loop circuit. By providing the second phase-locked loop circuit to be generated, the sensitivity of the voltage controlled oscillator can be reduced, and the stability of the circuit against changes in the surrounding environment can be improved.

According to another clock generator of the present invention, in addition to the above configuration, the first phase-locked loop circuit divides the frequency of the first clock signal and uses the frequency of the input data clock signal as a basis. The first frame counter and the first
The frequency dividing means resets in response to the detection of the phase shift with the second frame counter operating based on the first clock signal generated by the phase locked loop circuit of Can be lowered,
It is possible to improve the stability of the circuit with respect to changes in the surrounding environment and to simplify the circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 / N0 frequency divider 2, 3 PLL circuit 4, 5 Frame counter 6 Link / reset circuit 21, 31 Phase comparator 22, 32 Loop filter 23, 33 Voltage controlled oscillator 24 1 / N1 frequency divider 34 1 / N2 Divider

Claims (2)

(57) [Claims] What is different from a clock frequency of input data?
The first and second clock frequencies are in an integer ratio relationship
Using the second clock signal, parallel data and serial
Data interface circuit that performs input / output processing of file data
The clock of the input data
A first frequency based low frequency parallel data
A first phase locked loop circuit for generating a clock signal;
The first phase locked loop circuit generated by the first phase locked loop circuit;
Higher frequency than the first clock signal based on the clock signal
Generating a second clock signal for the serial data having a wave number;
And a second phase-locked loop circuit to be formed.
And a clock generator. 2. The data interface circuit according to claim 1 , wherein
First frame operating based on clock signal of input data
And a counter generated by the first phase locked loop circuit.
A second frame operating based on the first clock signal thus obtained.
A first phase locked loop circuit, wherein the first clock is a first clock.
A signal is divided and the first frame counter and the second
2 in response to the detection of a phase shift with the frame counter 2
2. The apparatus according to claim 1, further comprising a frequency dividing means to be set.
A clock generator as described.