JPH03216025A - Parallel/serial converter - Google Patents

Abstract

PURPOSE:To save circuits unable to be integrated considerably by providing a circuit diciding a phase difference between an input clock and a retiming clock at a prescribed threshold level and inverting the phase of the retiming clock and a logic circuit comparing the state with the preceding retiming state of the decided signal. CONSTITUTION:This converter is provided with an n-multiple circuit 21 for an inputted clock, a frequency divider circuit 22 frequency-dividing an output of the circuit 21 into 1/n, an EX-OR state 23, and a multiplexing circuit 26 obtaining a multiplexing signal subjected to serial conversion. A parallel data signal inputted from a data input terminal 10 is subjected to retiming at a retiming circuit 24 and a phase difference detection circuit 25 detects that a timing margin of a phase difference between a clock signal 34 for retiming and the parallel data signal 31 is small, and the EX-OR gate 23 inverts the phase of the timing clock signal 34 when the timing margin is small. Thus, the retiming margin is increased more than that before the inversion and the production of an error due to the retiming is prevented.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to parallel-to-serial converters.

[Conventional technology]

Normally, a parallel-to-serial converter converts input n pieces of parallel data into serial data using a multiplexing circuit, but at this time, in order to switch to multiplexing, a 1ogzn switching signal is used to change the input clock. Each column of parallel data is sequentially selected at n times the cycle, rearranged into serial data, and output.

Here, since the order in which n pieces of parallel data are arranged into serial data must always be constant, the phase relationship between the input parallel data and the switching signal must always be constant. However, since this switching signal is created by multiplying the input clock of the parallel-to-serial converter by n and then dividing the frequency, phase uncertainty occurs when performing this frequency division.

The method to remove this phase uncertainty is to multiply the input clock by n and then divide the input clock by n.If you retiming the input data, the phase relationship between the retimed data and the switching signal of the multiplexing circuit will be corrected. It is always constant. However, there is uncertainty in the phase difference between the input data of the parallel-to-serial converter and the retiming clock due to multiplier circuits, frequency divider circuits, etc., and depending on the phase difference, errors may occur due to retiming. There is. In order to solve this uncertain phase difference, a phase-locked loop circuit has been used in the conventional example.

The conventional parallel-to-serial converter includes a phase comparator 61, a frequency divider 62, and a loop filter 63, as shown in the block diagram of FIG.
, a phase-locked loop (PLL) consisting of 64 VCOs.
, a retiming circuit 65 , and a multiplexing circuit 66 . In the figure, the PLL circuit uses a clock whose frequency is divided by n by a frequency divider circuit 62 from the output signals of VCOs 6 and 4, which generate a clock n times the input clock.
A phase difference between input clocks 72 is detected by a phase comparator 61. This detection signal is passed through the loop filter (LPF) 63
The voltage is converted into a direct current and fed back to the VCO 64, forming a control loop so that the phase difference is constant. The output signal 77 of the frequency dividing circuit 62 controlled in this way is supplied to the retiming circuit 65, and the phase of the input data signal 71 is retimed, and the multiplexing circuit 66 outputs 1og2n signals from the frequency dividing circuit 62. The switching signal 76 causes the output to become a serial output signal 79.

[Problem to be solved by the invention]

In the conventional parallel-to-serial converter described above, although the retiming circuit, the multiplexing circuit, and the like can be integrated into ICs, the other loop filters and VCOs have a drawback that it is difficult to integrate them into ICs.

Furthermore, when frequency stability of the VCO is required, there is also the drawback that the circuit becomes an expensive circuit such as a VCO using a crystal oscillator.

[Means to solve the problem]

The parallel-to-serial converter of the present invention includes a retiming circuit that corrects the phase of a parallel data signal, a multiplexing circuit that converts the output signal of the retiming circuit into a serial data signal multiplexed in a predetermined arrangement, and an external a multiplier circuit that multiplies a clock signal input from the outside by a predetermined number; a frequency divider circuit that divides the output of the multiplier circuit; and a clock signal input from the outside and supplied to the retiming circuit. a phase difference detection circuit that inputs a control signal, detects a phase difference, compares the magnitude with a predetermined threshold value, and outputs a determination signal for polarity inversion of the control signal; and the determination signal and the frequency dividing circuit. and an exclusive OR circuit which receives the output signal of the retiming circuit and outputs a control signal to the retiming circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. 1st
The illustrated embodiment includes a data input terminal 10 for parallel data, a data output terminal 11 for multiplexed serial data, clock input and output terminals 12 and 13, an input clock multiplier circuit 21, and a multiplier circuit 21 for multiplying the input clock. The circuit 21 output is 1/n
A frequency dividing circuit 22 that divides the frequency into
OR) Gate 23 and phase difference detection circuit 25 change the phase of the n-divided clock of frequency dividing circuit 22 by 0 or π. a retiming circuit 24 that retimes n pieces of parallel input data 31 using the output of the EX-OR gate 23;
The n outputs of the retiming circuit 24 are divided into the frequency dividing circuit output 33
(log2n lines), it is composed of a multiplexing circuit 26 that serially converts multiplexed signals. Next, the operation of this embodiment will be explained. The n parallel data signals 31 input from the data input terminal 10 are retimed by the retiming circuit 24, but the phase difference detection circuit 25 detects the phase difference between the retiming clock signal 34 and the parallel data signals 31. It is detected that the timing margin is small, and when the timing margin is small, the EX-OR gate 23 inverts the phase of the retiming clock signal 34. As a result, the retiming margin becomes larger than before inversion, and it is possible to prevent errors from occurring due to retiming. When the timing margin is large, the output of the phase difference detection circuit 25 does not change, and the phase of the retiming clock signal 34 remains unchanged. The n output signals of the retiming circuit 24 are always multiplexed into one serial signal 35 in the same order by the 1og2'n output signals 33 of the clock frequency dividing circuit 22.

Next, the circuit configuration and operation of the phase difference detection circuit 25 will be explained with reference to the circuit diagram in FIG. 2 and the operation explanatory diagram in FIG. First, if the input data signal 31 and the input clock 32 have the same rising edge as shown in FIG. It becomes maximum when it becomes.

Now, the phase difference of 8T between the retiming clock 34 and the input clock is determined by the exclusive NOR (EX-NOR) gate 91.
The output detected by the low-pass filter 92 is converted into an almost DC component. Here, the relationship between the change in the voltage of the output signal 102 of the low-pass filter 92 according to the phase difference of 8T between the two input clocks and the retiming clock signals 32 and 36 is as shown in FIG. 3(b). When the phase difference 8T is O, that is, when the timing margin is minimum, the voltage of the output signal 102 becomes maximum, and the voltage of the output signal 102 becomes 0 at a position where the phase difference ΔT is shifted by -π or +π. In other words, the timing margin is maximized. Note that the voltage on the vertical axis indicates the voltage normalized with the maximum voltage of the output signal 102 as 1. An output signal 102 that changes in this way and a reference voltage 103 that provides a certain threshold value
When inputted into the converter 93 and compared, Fig. 3 (
b) The shaded part shown in , that is, the phase difference △T is -8T.
1 to +ΔT. In between, the voltage of the output signal 102 becomes higher than the reference voltage 103, indicating that the timing margin is small. Therefore, the output signal 104 in this state
Accordingly, the clock signal 36 can be inverted to ensure a timing margin. If the reference voltage 103 is made smaller than 0.5, the range for monitoring the small timing margin will be expanded, but since the value of the phase difference 8T1 will be repeatedly inverted, the value of the phase difference 8T1 will be smaller than π/2. Make it smaller. If phase inversion is performed on the output signal 104 of the comparator 93 itself in this way, the phase inversion will be repeated, resulting in a return to the one with the smaller timing margin. Therefore, it is necessary to compare the previous state and the current state and perform phase inversion. Flip-flop 94.95 and Escursive or (EX-
The OR) gate 96 is a circuit for preventing this, and by inputting a clock signal 105 which is sufficiently slow compared to the operating speed of the phase difference detection circuit from the terminal 83, the comparator 9
The output of the phase difference detection circuit can be controlled so that the output signal 104 of No. 3 is always at a low level, that is, the timing margin for retiming is equal to or higher than a standard value. [Effects of the Invention] As explained above, the present invention provides a circuit that determines the phase difference between an input clock and a retiming clock using a predetermined threshold value and inverts the phase of the retiming clock, and a circuit that inverts the phase of the retiming clock before the determined signal. By providing a logic circuit that compares the state, compared to the conventional configuration using a PLL circuit,
This has the effect of significantly reducing the number of circuits that cannot be integrated into ICs. In addition, ■CO using a crystal oscillator like the conventional example
This has the effect of significantly lowering costs compared to using .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a main circuit diagram of this embodiment, FIG. 3 is an explanatory diagram of the operation of the phase difference detection circuit of this embodiment, and FIG. It is a block diagram of a conventional parallel-to-serial converter. 10.11...Data input and output terminal, 12, 13...Clock input and output terminal, 21...n multiplier circuit, 22...frequency divider circuit, 23
．． 96... EX-OR gate, 24... Retiming circuit, 25... Phase difference detection circuit, 26... Multiplexing circuit, 80-84... Terminal, 91... EX-NOR
Gate, 92...Low pass filter, (LPF), 9
3...Comparator, 94.95...Flip-flop, 96...EX-OR gate.

Claims (1)

[Claims] 1. A retiming circuit that corrects the phase of a parallel data signal, a multiplexing circuit that converts the output signal of the retiming circuit into a serial data signal multiplexed in a predetermined arrangement, and a retiming circuit that corrects the phase of a parallel data signal; A multiplier circuit that multiplies an input clock signal by a predetermined number, a frequency divider circuit that divides the output of the multiplier circuit, and control that supplies the externally input clock signal and the retiming circuit. a phase difference detection circuit that inputs a signal, detects a phase difference, compares the magnitude with a predetermined threshold value, and outputs a determination signal for polarity inversion of the control signal; 1. A parallel-to-serial converter comprising: an exclusive OR circuit that receives an output signal and outputs a control signal to the retiming circuit. 2. An exclusive NOR gate into which the phase difference detection circuit inputs the control signal and the clock signal input from the outside and outputs a logic signal; Claim 1, further comprising: a comparator for comparing the output signal of the comparator with a predetermined threshold signal, and a logic circuit for determining polarity reversal of the control signal after comparing the comparator output signal with a previous state of the control signal. Parallel-to-serial converter as described.