JP2959511B2 - Data strobe device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data strobe device, and more particularly to a data strobe device for reproducing a digital frequency modulation signal.

[0002]

2. Description of the Related Art One of the methods for modulating a digital signal is a digital frequency modulation method for modulating a digital signal into a so-called frequency modulation signal.
(Eight to Fourteen Modula
EFM signal modulated by the T.T. method is well known as a digital recording modulation method of a compact disc. The EFM signal converts an 8-bit digital signal into a 14-bit digital signal according to a predetermined rule, and further suppresses a DC component suppression bit (DSV: Digital Sum Variation) so as not to generate a DC component.
on), and 3 for the unique bit period T
It is a digital frequency modulation signal frequency-modulated at state inversion intervals of T, 4T, 5T,..., 11T.

Conventionally, the restoration of an EFM signal is performed by using a PLL (Pha) based on a synchronous clock based on the transmitted EFM signal.
There is known a method of reproducing an EFM signal transmitted with a synchronous clock by reproducing the signal with a “se Locked Loop” circuit. For example, there is a clock recovery circuit disclosed in Japanese Utility Model Application Laid-Open No. 60-67556 as an example of the method. The clock recovery circuit includes a voltage-controlled oscillator, a circuit that generates a clock based on the output of the voltage-controlled oscillator, a first latch circuit that latches an EFM signal with a clock, and a circuit between the input and output of the first latch circuit. A first phase difference detecting means for detecting a phase difference, a second latch circuit for latching a signal obtained by matching an EFM signal at a clock timing with a clock, and a phase difference between input and output of the second latch circuit. Second phase difference detection means; and means for controlling the voltage controlled oscillator such that two phase differences detected by the first phase difference detection means and the second phase difference detection means have a predetermined relationship. Is provided.

According to the clock recovery circuit described in this publication, a clock is generated based on a voltage controlled oscillator,
The M signal is latched by the clock, and the synchronous clock is reproduced by controlling the oscillation frequency of the voltage controlled oscillator so that the phase difference between the signals before and after the latch becomes a predetermined state, and transmitted by the synchronous clock. It operates to strobe the EFM signal.

In general, a transmitted EFM signal is affected by intersymbol interference, jitter noise, and the like. Re-identification is performed at the center of the waveform, which is the best identification point of the transmitted EFM signal, and the EFM signal is converted. Need to be restored. However, if the deviation of the strobe point of the strobe circuit, that is, the deviation of the rising or falling point of the reproduced clock from the best discrimination point of the restored EFM signal, greatly affects the code error rate in the data reproducing process. It becomes a factor.

This shift is caused by a frequency difference between the inherent bit frequency 1 / T of the transmitted EFM signal and the asynchronous state frequency fo of the voltage controlled oscillator.
The phase difference between the two signals detected by the phase difference detecting means and the second phase difference detecting means is smoothed by a low-pass filter to obtain the oscillation control voltage of the voltage controlled oscillator. This is because there must be a phase difference corresponding to the obtained EFM signal and the synchronization clock.

[0007]

In the conventional data strobe device described above, the specific bit frequency 1 / T of the transmitted EFM signal fluctuates, or the specific bit frequency 1 / T is asynchronous with the voltage controlled oscillator. If there is a frequency deviation from the frequency fo, the rising or falling point of the reproduced clock with respect to the best discrimination point of the transmitted EFM signal is shifted, and as a result, the bit error rate is greatly affected in the data reproducing process. May be given.

In order to solve the above problem, at least a clock recovery circuit for recovering a clock based on a transmitted digital frequency modulation signal and a strobe circuit for recovering data of the digital frequency modulation signal by using the clock as a trigger are provided. There is a data strobe device. In this data strobe device, a strobe point phase deviation signal obtained by using an input / output signal of a strobe circuit and a difference between respective integrated values of a strobe point control reference signal generated by using a clock and an input / output signal of the strobe circuit are used. By automatically controlling the clock phase shifter that controls the phase of the clock, the deviation of the strobe point is automatically corrected, and the deviation of the strobe point is automatically determined without depending on the transmission data sequence of the digital signal. The correction can be performed, and the bit error rate of the reproduced data can be reduced. This data strobe device is described in detail in JP-A-61-9058.

However, in the above data strobe device, a clock phase shifter for controlling the phase of the clock, and a strobe point phase deviation signal for generating a signal for automatically controlling the clock phase shifter and an integration of each of the strobe point control reference signal. Since the integrator for obtaining the value signal is composed of an analog circuit, the identification of the best identification point of the digital frequency modulation signal can be performed by the aging of the integration constant deviation of the integrator or the aging of the characteristics of the clock phase shifter. An offset may occur in the point phase. Further, since these circuits include analog circuits, it is difficult to integrate them in an LSI (Large Scale Integrated Circuit) or the like on the same process as the digital circuit from the viewpoint of process matching with the digital circuit.

Therefore, an object of the present invention is to solve the above-mentioned problems and to automatically correct the deviation of the strobe point by configuring the circuit only with a digital circuit,
An object of the present invention is to provide a data strobe device that can reduce an error rate of reproduced data.

[0011]

SUMMARY OF THE INVENTION A data strobe apparatus according to the present invention reproduces data of a digital signal based on a synchronous clock signal reproduced on the basis of a digital signal modulated and sent to a digital frequency modulation signal. A data strobe device including a strobe circuit for performing a clock signal generation, the clock signal generating means generating a clock signal having a frequency n times (n is a positive integer) the synchronous clock signal based on the digital signal; Edge detecting means for detecting a point based on the clock signal generated by the clock generating means; and n stages for sequentially shifting the output of the edge detecting means based on the clock signal generated by the clock generating means. A shift register, and counting each tap output signal of each stage of the shift register. A distribution measuring means for measuring the distribution of the appearance positions of the change points; a clock signal generated by the clock generating means divided by 1 / n to generate the synchronous clock signal; and a measurement result of the distribution measuring means. And a frequency dividing means for correcting the synchronous clock signal based on the digital signal. The digital signal is reproduced by the strobe circuit based on the output of the frequency dividing means.

The data strobe device of the present invention includes at least a synchronous clock recovery circuit and a strobe circuit. The synchronous clock recovery circuit reproduces a clock having a frequency n times (n is a positive integer) the synchronous clock. I have.

That is, in the data strobe device of the present invention, edge detecting means for detecting the signal change point of the digital frequency modulation signal by n times the synchronous clock, and the output of the edge detecting means are sequentially shifted according to the n times synchronous clock. an n-stage shift register, and n count counters for counting the output state of each shift register according to the corrected synchronous clock and outputting a carry when the count value becomes m (m is a positive integer); , ORing means for logically ORing the carry outputs of the n count counters, and when the i-th (i is a positive integer, i ≦ n) count counter among the n count counters outputs a carry, the numerical value i is 1 / n which is preset and divides n times the synchronous clock by 1 / n
A frequency divider is provided, and the digital frequency modulation signal is strobed using the output of the 1 / n frequency divider as a corrected synchronous clock.

With such a configuration, the data strobe device of the present invention can constitute the circuit concerned only with digital circuits, has no characteristic aging, has good process consistency, and has a large scale integrated circuit (LSI). ) Etc. can be easily integrated.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a data strobe device according to one embodiment of the present invention includes a synchronous clock recovery circuit 2, a synchronous clock generation circuit 3, a strobe circuit 4
, An input terminal 11, and output terminals 12 and 13.

The synchronous clock recovery circuit 2 is a circuit for recovering a synchronous clock of the digital signal 100 input to the input terminal 11, and includes a phase comparator 21, a charge pump circuit 22, a low-pass filter 23, a voltage controlled oscillator 24 and a 1 / n frequency divider 25.

The synchronous clock generation circuit 3 includes an edge detection circuit 31, a shift register 32, and count counters 331 to 331.
A count counter group 33 composed of 33n and an OR circuit 34
And a 1 / n frequency divider 35.

FIG. 2 is a timing chart showing the operation of the synchronous clock recovery circuit 2 of FIG. 1, and FIG. 3 is a timing chart showing the operation of the synchronous clock generation circuit 3 and the strobe circuit 4 of FIG. The operation of the embodiment of the present invention will be described with reference to FIGS.

The digital signal 100 modulated and transmitted to the digital frequency modulation signal is input to the input terminal 11 and transmitted to the synchronous clock reproducing circuit 2, the synchronous clock generating circuit 3, and the strobe circuit 4, respectively.

The synchronous clock reproducing circuit 2 is a circuit for reproducing a synchronous clock of the digital signal 100, and its basic configuration is the same as that of the above-described conventional technique as one method. That is, the digital signal 100 is
And the phases are compared by the clock φ from the 1 / n frequency divider 25.

As shown in FIG. 2, the phase comparator 21 converts the output clock nφ of the voltage controlled oscillator 24 into a 1 / n frequency divider 25 with respect to the natural frequency 1 / T of the digital signal 100.
The phase difference detection signal U indicates the phase advance when the frequency of the clock φ divided by the above is high, and indicates the phase lag when the frequency is low.
And a phase difference reference signal D having a width of a half cycle of the clock φ and corresponding to the phase difference detection signal U.

The generated phase difference detection signal U and phase difference reference signal D are both sent to the charge pump circuit 22, are combined in the charge pump circuit 22, and are output as the voltage controlled oscillator control signal Cp. Further, the carrier component of the clock φ is removed from the voltage controlled oscillator control signal Cp by the low-pass filter 23, and the voltage controlled oscillator control signal Vt
Is input to the voltage controlled oscillator 24. The voltage controlled oscillator 24 generates an output clock nφ having a frequency n times (n is a positive integer) the synchronous clock in accordance with the voltage controlled oscillator control signal Vt.

As described above, when the synchronous clock reproducing circuit 2 has a characteristic that the oscillation frequency of the voltage controlled oscillator 24 increases in direct proportion to the level of the control voltage, the phase comparison results in the output level of the voltage controlled oscillator control signal Vt. Is lower than the natural frequency 1 / T of the digital signal 100 with respect to the clock φ (the phase is advanced), and it is lower when the frequency is higher (the phase is delayed). The output clock nφ is reproduced by the 1 / n frequency divider 25 as the synchronous clock φ.

The edge detection circuit 31 of the synchronous clock generation circuit 3 detects a signal change point of the digital signal 100 by the output clock nφ of the voltage controlled oscillator 24, and the n-stage shift register 32 controls the output of the edge detection circuit 31 by voltage control. The shift is performed sequentially according to the output clock nφ of the oscillator 24.

The count counter group 33 includes count counters 331 to 33n arranged corresponding to the tap outputs of the n-stage shift register 32.
Each of 31 to 33n indicates the number of times that the tap output of the corresponding shift register 32 is active, that is, the number of times that the edge detection circuit 31 becomes a detection signal indicating that the signal change point of the digital signal 100 is detected, by the 1 / n frequency divider 35 The counting is performed according to the synchronous clock. Also, a counting counter 3
31 to 33n are predetermined values m in which the respective count values are set in advance.
A carry is output when (m is a positive integer). That is, the count counter group 33 measures the distribution of the appearance positions of the edge detection signals (signal change points) of the edge detection circuit 31.

The OR circuit 34 includes counters 331 to 331.
A logical OR operation is performed on the carry output of 33n, and the operation result is output to each of the counters 331 to 33n and the 1 / n frequency divider 35. When the output of the OR circuit 34 becomes active, each of the counters 331 to 33n resets its count value. The 1 / n frequency divider 35 divides the output clock nφ from the voltage controlled oscillator 24 by 1 / n to generate a synchronous clock ψ. In this case, the synchronous clock ψ is counted counter group 3
3 is a signal obtained by correcting the synchronous clock of the digital signal 100 in accordance with the distribution of the appearance positions of the edge detection signals measured in Step 3. That is, in the 1 / n frequency divider 35, in response to the carry output from each of the count counters 331 to 33n, a value corresponding to the count counter 331 to 33n that outputs the carry is preset. For example, when a carry is output from the i-th (i is a positive integer, i ≦ n) count counter 33i, a numerical value i is preset in the 1 / n frequency divider 35.

A series of operations of the synchronous clock generation circuit 3 measures the appearance distribution of the detected edge signal Ed sampled by the output clock nφ at the time interval 1 / ψ, and obtains the relative time position having the highest output probability, This is to generate a corrected synchronous clock 与 え る that gives an optimum strobe point.

That is, the detected edge signal Ed obtained by sampling the digital signal 100 with the output clock nφ is input to the n-stage shift register 32, sequentially shifted according to the output clock nφ, and output to the output Qi. The count counter 33i to which each of these outputs Qi is input counts according to the corrected synchronous clock で あ れ ば if the state of the output Qi at the timing of the rising edge of the synchronous clock “is“ H ”level, and the counted value is a predetermined value. The carry is output when the value reaches m. The carry output from the count counter 33i is ORed by the OR circuit 34, and the OR output resets the count counter group 33, and at the same time, divides the output clock nφ by 1 / n to correct the synchronous clock ψ (= 1 / n frequency divider 35 which outputs signal 101)
Acts to preset a numerical value i.

FIG. 3 shows the process of generating a corrected synchronous clock when i = 2 in the count counter group 33, that is, when the appearance probability of the detection edge signal Ed for the count counter 332 is high, when n = 8. Is shown. The operation in this case will be described in detail below.

When the signal 101 rises at a certain time a in the processing process and the output Q2 of the n-stage shift register 32 becomes active, the count counter 332 counts up and the count value becomes "m-2". From “m−1”. When the output Q1 of the n-stage shift register 32 becomes active at time b, the count counter 331 counts up,
The count counter 332 does not count up. Further, when the output Q2 of the n-stage shift register 32 becomes active at time c, the count counter 332 counts up, and the count value changes from “m−1” to “m”. At this time, the OR circuit 34 and 1 / n are output from the counter 332.
The carry is output to the frequency divider 35. The output of the OR circuit 34 is input to all the reset terminals of the respective counters 331 to 33n to reset the respective count values, and acts to preset the numerical value i = 2 in the 1 / n frequency divider 35.

Therefore, the output of the i / n frequency divider 35 becomes the corrected synchronous clock ψ with its signal inversion timing updated. The operation for updating the signal inversion timing of the synchronous clock は is performed when the count value of each of the counters 331 to 33n is “m”.
The detection edge signal Ed sampled by the output clock nφ at the time interval 1 / ψ
Is measured, the relative time position where the appearance probability is the highest is obtained, and the corrected synchronous clock 与 え る that gives the optimum strobe point is automatically generated.

The strobe circuit 4 receives the digital signal 100
Is the synchronous clock corrected by the synchronous clock generation circuit 3.
, And outputs a reproduced data signal 102 to the output terminal 13. The strobe is performed on the back side (falling edge in FIG. 3) of the timing of the synchronous clock の when the appearance distribution of the detected edge signal Ed is measured by the synchronous clock generating circuit 3, and is the best discrimination point of the digital signal 100. This is performed at the center of the waveform.

The operation of the embodiment of the present invention has been described in detail for the case where n = 8. However, it is needless to say that n is not limited to this and may be appropriately selected according to the required performance.

As described above, the voltage controlled oscillator 24 of the synchronous clock reproducing circuit 2 generates the output clock nφ having a frequency n times the synchronous clock of the digital signal 100, and the edge detection circuit 31 of the synchronous clock generating circuit 3 generates the output clock nφ. The appearance distribution of the detected edge signal Ed sampled from the digital signal 100 based on nφ is measured by the n-stage shift register 32 and the count counter group 33, and the synchronous clock corrected based on the relative time position having the highest appearance probability By generating ψ in the 1 / n frequency divider 35, a circuit that can automatically correct the deviation of the strobe point and reduce the code error rate of the reproduced data can be constituted only by the digital circuit. The characteristics do not change over time, the process consistency is good, and it can be easily integrated on an LSI or the like.

[0035]

As described above, according to the present invention, the digital signal is used as a reference and n times (n) times the synchronous clock signal.
Generates a clock signal with a frequency of (positive integer), detects the change points of the digital signal based on the clock signal, measures the distribution of the appearance positions of the detected change points, and based on the measurement result, By correcting the synchronous clock signal, the deviation of the strobe point can be automatically corrected by using only a digital circuit, and the error rate of reproduced data can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the synchronous clock recovery circuit of FIG.

FIG. 3 is a timing chart showing operations of a synchronous clock generation circuit and a strobe circuit of FIG. 1;

[Explanation of symbols]

 2 Synchronous Clock Regeneration Circuit 3 Synchronous Clock Generation Circuit 4 Strobe Circuit 21 Phase Comparator 22 Charge Pump Circuit 23 Low-Pass Filter 24 Voltage Controlled Oscillator 25, 35 1 / n Divider 31 Edge Detection Circuit 32 Shift Register 33 Count Counter Group 34 Logic Sum circuit 331-33n count counter

Claims (3)

(57) [Claims] 1. A data strobe device comprising a strobe circuit for reproducing data of a digital signal based on a synchronous clock signal reproduced on the basis of a digital signal modulated and sent to a digital frequency modulation signal, Clock generating means for generating a clock signal having a frequency n times (n is a positive integer) the synchronous clock signal based on the digital signal; and a clock generating means for generating a change point of the digital signal by the clock generating means Edge detecting means for detecting based on a signal, an n-stage shift register for sequentially shifting the output of the edge detecting means based on the clock signal generated by the clock generating means, and taps at each stage of the shift register Distribution measuring means for counting each output signal and measuring the distribution of the appearance positions of the change points; Frequency dividing means for dividing the clock signal generated by the clock generating means by 1 / n to generate the synchronous clock signal and correcting the synchronous clock signal based on the measurement result of the distribution measuring means. A data strobe device, wherein the digital signal is reproduced by the strobe circuit based on the output of the frequency dividing means. 2. The distribution measuring means is provided for each stage of the shift register and synchronizes the number of appearances of the change point with the output of the frequency dividing means based on the state of the corresponding tap output signal. 2. The data strobe device according to claim 1, further comprising n number of counting means for counting. 3. When the count value of the i-th (i is a positive integer and i ≦ n) counting means of the n counting means has reached a predetermined predetermined number, a numerical value is given to the frequency dividing means. 3. The data strobe device according to claim 2, wherein i is set.