JPH11185395A - Clock reproducing pll device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(phase-locked loop) device capable of preventing the deviation of the locking of the PLL due to a temp. change and also capable of generating the reference voltage of its own with high accuracy with a resolution finer than a phase difference signal. SOLUTION: In generating the output signal of a CLK in a VOC 9 by a control voltage to be applied to the VOC 9 through an LPF 8 from a differential amplifier 7, an input signal from a signal input terminal 1 is converted into a digital signal in an A/D converter 2 and the phase of this signal is compared with that of the output of the CLK in a phase comparator 3 and the digital phase difference signal of 8 bits is generated to be converted into an analog voltage in a D/A converter 4 and the analog voltage is made a first input of a differential amplifier 7. Besides, reference voltage data having the resolution of 12 bits are modulated in a time base direction in a data modulating circuit 19 to be converted into the reference voltage data having 8 bits capable of expressing 12 bits with the average value of the time base direction and these data are converted into an analog voltage in a D/A converter 20 to be made a second input of the amplifier 7 and a control voltage having a satisfactory accuracy is generated based on the reference voltage having the accuracy of 12 bits substantially. Moreover, temp. characteristics of the D/A converters 4,20 are roughly equal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) device, and more particularly to a PLL device capable of reducing the influence of a temperature change when extracting a clock from a digital signal transmitted from a magnetic recording / reproducing device or the like.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus for recording / reproducing a digital signal, when recording a signal, a magnetic domain is formed in accordance with the digital signal "1" or "0". When a recorded signal is reproduced, a reproduced signal is formed based on a signal obtained only at a change portion of the magnetic domain, that is, a signal obtained as a differential waveform of an edge portion of the magnetic recording signal.

FIG. 4 shows that a reproduced signal Sd as shown in FIG. 4C is obtained with respect to a magnetic recording signal Sr as shown in FIG. 4B recorded in correspondence with the clock (CLK) shown in FIG. Is shown.

In actual magnetic recording, since the clock itself is not recorded, it must be generated from the reproduction signal Sd. The present invention relates to a PLL device used for such clock recovery.

FIG. 5 is a block diagram of a conventional PLL device. The PLL device outputs a CL signal from a CLK output terminal 10 based on a reproduction signal input to a reproduction signal input terminal 1.
A device for extracting a K output signal. The reproduction input signal Sd input to the reproduction signal input terminal 1 is converted into a digital signal in an A / D (analog / digital) converter 2 in synchronization with the CLK output signal. This digital signal is provided to the next-stage phase comparator 3. The phase of the digital signal from the A / D converter 2 is compared with the phase of the CLK output signal.

[0006] The phase comparator 3 outputs a digital phase error signal Se as a result of the phase comparison. This phase error signal Se is a D / A that operates based on the CLK output signal.
The signal is converted into an analog signal via a (digital / analog) converter 4 and input to a first input terminal of the differential amplifier 7.

On the other hand, when reference voltage data is input from a reference voltage data input terminal 5 to an electronic voltage regulator (EVR) 6 called an electronic volume regulator, the EVR 6 converts the analog DC reference voltage corresponding thereto. And inputs it to the second input terminal of the differential amplifier 7. The differential amplifier 7 compares the phase error signal from the D / A converter 4 with a reference voltage from the EVR 6, and outputs a voltage corresponding to the difference between the two. The output voltage of the differential amplifier 7 is shaped through a low-pass filter (LPF) 8 having a sufficiently large time constant, and is input to a voltage-controlled oscillator (VCO) 9 as a control signal for reducing a phase error. Is done. VCO9
Controls the output frequency of CLK according to the input control voltage, and outputs the output from the CLK output terminal 10.

Now, in the above-described PLL device,
The detection of the phase error is performed by the phase comparator 3. Next, the operation will be described.

FIG. 6 shows a detailed configuration of the phase comparator 3. The phase comparator 3 includes an input terminal 11, a first delay circuit 12, a second delay circuit 13, a level discriminator 14,
A subtractor 15, a multiplier 16, and an output terminal 17 are provided.

Prior to describing the operation of the phase comparator 3 in FIG. 6, the principle of phase error detection will be described with reference to FIG. 4 and FIGS.

FIG. 7 is an enlarged view of a portion "A" where the first differential output is generated for the reproduced signal Sd in FIG. FIG.
, Two threshold values TH and TL are set for the reproduction signal Sd, and when Sd> TH, a = “+ 1” is output as the level signal a, and (1) Sd <TL In this case, a = “− 1” is output, and (2) a = “0” is output when TL ≦ Sd ≦ TH (3) The phase comparator 3 outputs a phase error signal δ having a certain value only when a = “+ 1” or “−1”, and outputs δ = 0 when a = “0”.

With respect to the reproduced signal Sd input to the phase comparator 3, FIGS. 7 to 9 are enlarged views of the first signal portion "A" where the level signal a = "+ 1". In FIG.
Assuming that the sampling cycle is T, the level signal a = "+ 1" is obtained at the sampling time t, and the instantaneous value Sd (t of the input reproduction signal Sd at the sampling times t-T and t + T before and after the time t is used as a reference. −T), Sd
Since (t + T) is compared, Sd (t−T) −Sd (t + T) = 0 (4) Therefore, it is determined that the phase lock is normally performed (that is, there is no phase error). On the other hand, in FIG. 8, Sd (t−T) −Sd (t + T)> 0 (5), and in this case, it is determined that the reproduction signal is in a phase advanced state with respect to CLK. . In FIG. 9, Sd (t−T) −Sd (t + T) <0 (6), and in this case, it is determined that the reproduced signal is in a state of being delayed in phase with respect to CLK.

The input reproduced signal Sd is passed through a delay circuit 12 having a delay time T.
4 and, on the other hand, to the second delay circuit 13. The second delay circuit 13 also has the same delay time T as the first delay circuit 12. Here, the delay time T is a time corresponding to the sampling period T in the digital circuit. An input signal is supplied to an input terminal 11 and the delay signal
When the reproduced signal at the time point t is represented as Sd (t) with reference to the signal generation time point t obtained through the step S2,
The reproduction signal input to the input terminal 11 at the time point t is the reproduction signal Sd (t + T) input at the time point t + T one sampling cycle T later. Similarly, the reproduction signal obtained at the output terminal of the delay circuit 13 is This is the reproduction signal Sd (t-T) input to the input terminal 11 at the time point t-T.

The signal input to the subtractor 15 is at time t +
A reproduction signal Sd (t + T) at T and a reproduction signal Sd (t-T) at time (t-T), where Sd (t + T)
T) −Sd (t−T), and the difference is calculated by the multiplier 1
6 as a first input. The level discriminator 14 discriminates the level of the reproduced signal Sd (t) at time t,
According to the equations (1) to (3), a level signal a having 0 (zero) or positive or negative content is output and given as a second input of the multiplier 16.

As a result, the phase error signal δ obtained as an output signal of the multiplier 16 is as follows: δ = a ｛(Sd (t−1) −Sd (t + 1)｝ (7)

In the phase comparator shown in FIG.
At both sampling times (t-T,
(t + T) and the time (t) of the level determination, there is a time difference of time T corresponding to the sampling period.
As described in, the LPF 8 having a sufficiently large time constant is provided in the signal path for processing the phase error signal δ, so that a sufficiently practical operation result can be obtained with the circuit configuration of FIG. 6 as a practical circuit. it can.

The phase error signal δ calculated as described above is output from the phase comparator 3.

As shown in FIGS. 7 to 9, it is known that individual reproduction waveforms in magnetic recording / reproduction are substantially symmetrical. Therefore, with respect to time t, the signal level at time t-T and the signal level at time t + T have the same value as long as the phase is locked. That is,
As shown in FIG. 7, in the locked state, (Sd (t
+1) -Sd (t-1) = 0, therefore, the output of the subtractor 15 is "0", and the phase error signal δ output from the multiplier 16 is also δ = 0.

On the other hand, as shown in FIG. 8, in the phase advance state, the signal output from the subtractor 17 is (Sd (t−
1) -Sd (t + 1)> 0, which is a positive value corresponding to the phase error. Further, as shown in FIG. 9, in the phase delay state, (Sd (t-1) -Sd (t + 1) <0), which is a negative value corresponding to the phase error.

The phase error signal δ obtained as described above
Is output from the phase error output terminal 17 to the D / A converter 4, where it is converted to an analog signal and input to the differential amplifier 7.

The differential amplifier 7 converts the phase error signal δ into an EVR
6, the differential amplifier 7 generates a control voltage so that the phase error signal δ from the phase comparator 3 becomes “0”, that is, a locked state.
By giving it to the VCO 9 via F8, a phase-locked CLK output signal is obtained and output to the CLK output terminal 10.

[0022]

The conventional PLL device configured as described above has the following problems.

The phase error signal δ obtained by the phase comparator 3
Is very small in amplitude because the difference between signals of minute amplitude with respect to the amplitude of the input signal is calculated. Therefore, in order to convert the phase error signal into the control voltage, it is necessary to use an amplifier having a large gain. Further, in order to amplify the DC component of the phase error signal, it is necessary to use a differential amplifier that operates based on a DC reference voltage.

For the reasons described above, the differential amplifier 7 is applied to obtain the control voltage of the VCO 9, and the EV for inputting the reference voltage data from the reference voltage data input terminal 5.
A reference voltage is given from R6.

However, many D / A converters 4 have a temperature dependency with respect to the DC voltage, and there is a problem that the output voltage fluctuates depending on the temperature. On the other hand, the EVR 6 that generates the reference voltage has almost no temperature dependency, and consequently, the control voltage corresponding to the output of the differential amplifier 7 has the temperature dependency.
As a result, the VCO 9 is supplied with a control voltage that fluctuates greatly depending on the temperature, and a state where the phase lock of the generated CLK output signal cannot be maintained, that is, a state in which the phase is out of phase due to the temperature is caused. was there.

Accordingly, the present invention provides a method for controlling the temperature dependence of P
An object of the present invention is to provide a PLL device capable of preventing LL lock loss and generating a reference voltage itself with a finer resolution than a phase error signal with high accuracy.

[0027]

To achieve the above object, the present invention provides an A / D converter for digitally converting an input signal, an oscillator for generating a clock signal based on a control signal, and an A / D converter. Phase comparison means for digitally calculating the phase difference between the output of the D conversion means and the clock to generate digital phase error data, and first D / A conversion for converting the phase error data into a phase error signal of an analog amount Means,
Reference voltage generating means for providing digital reference voltage data; second D / A conversion means for converting the reference voltage data into an analog amount of reference voltage signal; control of the oscillating means by comparing the phase error signal with the reference voltage signal It is an object of the present invention to provide a PLL device provided with arithmetic means for generating a signal and filter means for leveling a control signal in a time axis direction.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a PLL device according to an embodiment of the present invention.

In the figure, a data modulation (DM) circuit 19
Is a circuit for performing data modulation processing on reference voltage data. The output of the DM circuit 19 is supplied to a second D / A converter 20.
, And supplied to the differential amplifier 7. Here, as the D / A converter 20, one having a temperature characteristic completely or almost the same as that of the first D / A converter 4 is used. Other components are the same as those of the conventional device shown in FIG.

The operation of the PLL device shown in FIG. 1 will be described. First, the operation of the DM circuit 19 will be described. DM
The purpose of the circuit 19 is to change data of a limited number of bits with time, and to incorporate, into its output, an average value taken in the direction of the time axis to a fine amount that cannot be represented by the original output bits. Placed in

Here, the output data of the DM circuit 19 and the output data of the phase comparator 3 are both 8 bits,
It is assumed that A converters 4 and 20 both convert 8-bit data into analog. On the other hand, the reference voltage data is 12
Bit.

The DM circuit 19 generates 8-bit data to be DM-modulated based on the 12-bit data,
/ A converter 20 input. In this case, D / A
The output of the converter 20 is an analog quantity that changes on the time axis because the 8-bit data is DM-modulated, and this quantity is equalized to a resolution equivalent to 16 bits by flattening in the time axis direction. Can be converted to an analog quantity.

Here, a method of data modulation will be described. The simplest way to convert 12-bit data to 8-bit data is to represent only the upper 8 bits and truncate the lower 4 bits, but that is not satisfactory. However, the lower 4 bits can be represented by an average value in the time axis direction by data modulation. That is, the amount represented by the lower 4 bits is
By expressing the data in a time-division manner, an amount equal to or less than the least significant bit of 8-bit data can be expressed as an average value.

In order to represent the lower 4 bits of data in a time division manner, 16 numerical values 0 (HE
The lower 4 bits are expressed in the time unit of X) to F (HEX). Therefore, by causing the least significant bit “1” of the upper 8 bits of 12 bits to appear in the 16 time units at a ratio represented by the lower 4 bits of data, 16 times In the time frame constituted by the unit, the amount of the least significant bit of the 8-bit data can be expressed.

In this embodiment, one clock period is allocated as a time unit, and one clock frame has a width of 16 clocks. And the difference between the data is 1
LSB (Least Significant Bit = Least Significant Digit)
Data modulation conversion is performed using two pieces of 8-bit data.

Here, the operation of the DM circuit 19 will be described with reference to the timing charts of FIGS.

Assume that the reference voltage data input to the input terminal 5 is 803 (HEX). in this case,
Data modulation is performed using the upper 8 bits of 80 (HEX) and 81 (HEX) data obtained by adding “1” thereto. On the other hand, the lower 4-bit data is 3 (HEX),
Of the 16 clocks, 81 (HEX) data is output for 3 clocks and 80 data for 13 clocks. This is as shown in FIG.

Next, the reference voltage data is 81D (HE
X). In this case, the upper 8 bits 81
(HEX) and 82 (HEX) obtained by adding “1” thereto
Data modulation is performed with the data. On the other hand, the lower 4 bits of data are D (HEX), so of the 16 clocks,
The data of 82 (HEX) is output for 13 clocks, and the data of 81 is output for 3 clocks. This is as shown in FIG.

The 8-bit data obtained by the data modulation as described above is supplied to the D / A converter 20. The A / D converted value of such data-modulated data is smoothed by the LPF 8. By processing, take the average value,
The original data is equivalent to 16 bits.

This will be described with reference to 803 (HEX). Data 80 (HEX) is equivalent to three clocks and 81 (HEX).
Since X) is 13 clocks, when an average level during 16 clocks is obtained, $ 800 (HEX) × 3 + 810
(HEX) × 13｝ / 16, which is 803 (HEX).

Similarly, in the case of 81D (HEX),
Data 82 (HEX) is equivalent to 13 clocks and 81 (HEX).
Since X) is 3 clocks, when an average level during 16 clocks is obtained, ｛820 (HEX) × 3 + 810
(HEX) × 13｝ / 16, which is 81D (HEX).

As described above, the reference voltage obtained by the DM circuit 19 is subjected to analog conversion processing by the D / A converter 20 whose temperature characteristic is exactly the same as that of the D / A converter 4, so that the temperature changes. However, the amount of change is exactly the same as that of the D / A converter 4, and the difference from the phase error does not change. For this reason,
VCO generated by the differential amplifier 7 even if there is a temperature change
9 does not change.

On the other hand, the control voltage processed by the LPF 8 is
The average level is equivalent to that obtained based on reference voltage data corresponding to 12 bits. Therefore, the VCO 9 is controlled with a higher resolution reference value for the phase error obtained by the phase comparator 3, so that a more accurate PLL device can be realized.

In this embodiment, an example has been described in which 12 bits are used as the reference voltage data and the data handled as the input of the D / A converter 20 is 8 bits.
Needless to say, this can be arbitrarily selected according to the required specifications of the device.

In the DM circuit 19, the case where the least significant bit "1" of the upper 8 bits of data is represented by time division is exemplified. However, there are various methods of representing data by data modulation. , Time division using a higher frequency clock,
By dispersing and expressing in one time frame, a higher quality analog amount suitable for smoothing processing can be obtained.

[0046]

The PLL device according to the present invention is equivalent to a small phase error signal obtained by digital data,
Since the control voltage of the VCO is generated using the reference voltage having higher resolution, a highly accurate PLL operation can be performed.
On the other hand, since the reference voltage and the error voltage are applied to the operational amplifier used to generate the control voltage of the VCO through the D / A converter having the same temperature characteristic,
A PLL operation with less characteristic fluctuation due to temperature can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL device according to the present invention.

FIG. 2 is a timing chart showing an example of the operation of the data modulation circuit of FIG.

FIG. 3 is a timing chart illustrating another example of the operation of the data modulation circuit in FIG. 1;

FIG. 4 is a waveform diagram of a general magnetic recording / reproducing signal.

FIG. 5 is a block diagram of a conventional PLL device.

FIG. 6 is a block diagram showing an internal configuration of the phase comparator of FIG.

FIG. 7 is a waveform diagram in a phase locked state, showing an area A extracted from the reproduction signal waveform of FIG. 4;

FIG. 8 is a waveform diagram when a reproduction signal is in a phase advanced state.

FIG. 9 is a waveform diagram when a reproduction signal is in a phase delay state.

[Explanation of symbols]

 Reference Signs List 1 signal input terminal 2 A / D converter 3 phase comparator 4 D / A converter 5 reference voltage data input terminal 7 differential amplifier 8 LPF 9 VCO 10 clock output terminal 12 delay circuit 13 delay circuit 14 level discriminator 15 subtraction Unit 16 multiplier 19 data modulation (DM) circuit 20 D / A converter

Claims (5)

[Claims] A / D conversion means for digitally converting an input signal, oscillation means for generating a clock signal based on a control signal, and a phase difference between an output of the A / D conversion means and the clock. Phase comparison means for performing digital operation to generate digital phase error data, first D / A conversion means for converting the phase error data into a phase error signal of an analog amount, and reference voltage generation means for providing digital reference voltage data Second D / A conversion means for converting the reference voltage data into a reference voltage signal having an analog amount, and calculation means for comparing the phase error signal with the reference voltage signal and generating a control signal for the oscillation means And a filter means for levelizing the control signal in the time axis direction. 2. The first D / A converter and the second D / A converter.
2. The clock recovery PLL device according to claim 1, wherein the D / A conversion means has substantially the same temperature characteristics. 3. The method according to claim 2, wherein the reference voltage generating means is configured to generate the second D /
The data conversion means for generating reference voltage data of a bit number corresponding to the input bits of the second D / A conversion means from original data having a larger number of bits than the number of input bits of the A conversion means. The PLL device for clock recovery according to claim 1 or 2. 4. The data conversion means extracts the upper first bit number from the original data, and adds it to the lower second bit.
4. The clock recovery according to claim 3, wherein the data is converted into data that changes with time by performing modulation based on the number of bits of data, and the amount of resolution of the original data is expressed by an average value in the time axis direction. PLL device. 5. The PLL device for clock recovery according to claim 4, wherein the sum of said first number of bits and said second number of bits corresponds to the number of bits of said original data.