KR0143530B1 - Digital automatic frequency control device - Google Patents

Abstract

The present invention relates to an automatic frequency adjusting device, and more particularly, to a digital automatic frequency adjusting device for automatically adjusting a frequency digitally using a modulo counter.

Input analog horizontal sync signal and system clock signal (F_clk) to extract horizontal sync split point value, output clock number, digital horizontal sync signal (MHsync) and predetermined clock delay digital horizontal sync signal in one horizontal sync. Input the horizontal synchronous separation point value, the digital horizontal synchronous signal delayed by a predetermined clock, and the number of clocks in the horizontal synchronous to calculate the actual horizontal synchronization period by system clock, and subtract the standard horizontal synchronization period from the actual horizontal synchronization period. The jitter amount is calculated, and a low frequency conversion carrier color signal is input by outputting a low frequency conversion carrier color signal corrected by inputting a standard low frequency conversion carrier color signal (Fcu) and the line jitter amount. Generates a frequency signal.

Description

Digital automatic frequency regulator

1 is a block diagram showing a conventional analog automatic frequency adjusting device

2 is a block diagram of an automatic frequency adjustment device according to the present invention.

3 is a detailed circuit diagram of the horizontal synchronization converter 100 of FIG.

4 is a detailed circuit diagram of the line jitter calculating unit 200 in FIG.

5 is a detailed circuit diagram of the carrier color signal correction unit 300 in FIG.

6 is a detailed circuit diagram of a modulo counter 400 in FIG.

7 is a temporary operation waveform diagram applied to the present invention

* Explanation of symbols for main parts of the drawings

100: horizontal synchronization converter 200: line jitter calculator

300: color signal correction unit 400: modulo counter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit, and more particularly, to a digital automatic frequency control device for automatically adjusting a frequency digitally using a modulo counter.

In general, the role of automatic frequency adjustment in an image processing system such as a video cassette recorder is to generate a 629 kHZ low frequency carrier color signal (FCU) that tracks horizontal synchronization. Normally, automatic frequency adjustment (AFC) of a video cassette recorder is composed of the same circuit as in recording, but during recording, the horizontal sync signal (Hsync) extracted from the input video signal is used, and during playback, the horizontal sync signal extracted from the playback video signal is used. Use (Hsync) as the reference signal. However, the reproduced horizontal synchronizing signal inevitably generates jitter according to the characteristics of the recording medium such as the characteristics of the head and the tape of the apparatus. Therefore, it becomes very difficult to reproduce the original recorded video signal accurately. Therefore, by adjusting the frequency of the low frequency conversion carrier color signal (FCU) generated by the horizontal synchronization signal variation by automatic frequency adjustment to reproduce the original video signal.

1 is a block diagram showing a conventional analog automatic frequency adjusting device,

The horizontal synchronizing separator 11 inputs the video signal VI input through the input terminal 10, extracts a horizontal synchronizing signal having a frequency f _H , and outputs the horizontal synchronizing signal to the phase comparator 12. The phase comparator 12 compares the phase of the horizontal synchronization signal output from the horizontal synchronization separator 11 with the phase of the horizontal synchronization signal input from the second divider 15 and converts the difference into a DC voltage. Output to the voltage controlled oscillator 13. The voltage controlled oscillator 13 oscillates based on a frequency corresponding to 160f _H and changes the oscillation frequency according to the input DC voltage. The first divider 14 divides the frequency corresponding to 160f _H of the voltage controlled oscillator 13 into 1/4 to output the low frequency conversion carrier color signal Fcu of 40f _H to the output terminal 16 and the second divider ( 15) The second frequency divider 15 outputs the frequency f _H and the frequency divider 40f _H signal by 1/40 of a phase comparator 12.

The conventional automatic frequency adjusting device as described above is usable in analog video signal processing, and has a problem that it cannot be used in digital video signal processing.

Accordingly, an object of the present invention is to provide a digital automatic frequency adjustment device for automatically adjusting the frequency when processing a video signal in a digital manner to solve the above problems.

In order to achieve the above object, the present invention inputs an analog horizontal synchronizing signal and a system clock signal (F_clk) to extract a horizontal synchronizing split point value, the number of clocks in one horizontal synchronizing period and a digital horizontal synchronizing signal (MHsync) and three clocks. A horizontal clock conversion means for outputting a delayed digital horizontal synchronization signal (3DMHsnync), a horizontal synchronous split point value output from the horizontal synchronous conversion means, a digital horizontal synchronization signal (3DMHsync), and a number of clocks in the horizontal synchronization are inputted. A line jitter calculating means for calculating an actual horizontal driving section by subtracting the standard horizontal driving section from the actual horizontal driving section, and calculating a line jitter amount from a standard low-conversion carrier color signal Fcu and the line jitter calculating means. A carrier color signal correction means for inputting an output line jitter amount to output a corrected low-conversion carrier color signal, and the carrier color The low frequency conversion carrier color signal corrected from the signal correction means and the standard low frequency conversion carrier color signal are input to generate a new low frequency conversion carrier color signal for automatic frequency adjustment.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an automatic frequency adjustment device according to the present invention.

Input the analog horizontal sync signal and system clock signal (F_clk) to extract the horizontal sync split point value, and count the number of clocks, the digital horizontal sync signal (MHsync), and the 3 clock delayed digital horizontal sync signal (30DMHsync) in one horizontal sync. Horizontal synchronous conversion unit 100 for outputting,

The actual horizontal synchronizing period is calculated by a system clock by inputting the horizontal synchronizing split point value, the digital horizontal synchronizing signal (3DMHsync), and the horizontal synchronizing clock number value outputted from the horizontal synchronizing conversion unit 100, and the actual horizontal synchronizing unit. A line jitter calculating unit 200 which calculates a line jitter amount by subtracting the standard horizontal driving unit from the section,

A carrier color signal correction unit 300 for inputting a standard low frequency conversion carrier color signal Fcu and a line jitter amount output from the line jitter calculating unit 200 to output a corrected low frequency conversion carrier color signal;

The modulated counter 400 is configured to input a low-conversion carrier color code corrected from the carrier color signal correction unit 300 and a standard low-conversion carrier color signal to generate a new low-conversion carrier color signal for automatic frequency adjustment.

3 is a detailed circuit diagram of the horizontal synchronization converter 100 of FIG.

The first latch 101 latches the horizontal sync signal Hsync to the system clock F_clk signal, and the second latch 102 latches and outputs the horizontal sync signal latched and output from the first latch 101. Wow,

A subtractor 103 for subtracting and outputting the horizontal synchronous signal latch output from the first latch 101 and a reference level value for horizontal synchronous separation;

A subtractor 104 which subtracts and outputs the horizontal synchronous signal latch output from the second latch 102 and a reference level value Thr for separation of horizontal synchronous signals;

A flip-flop 106 for delaying a signal output from the oragate 15 by a system clock signal F_clk and outputting a digital horizontal synchronization signal MHsync;

A third latch 107 for inputting the latch output signal from the second latch 102 and latching it by the horizontal synchronization signal MHsync to output a second horizontal synchronization separation point value B;

A fourth latch 108 for inputting the latch output signal from the first latch 101 and latching it by the horizontal synchronization signal MHsync to output a first horizontal synchronization separation point value A;

A counter 109 which is loaded by the digital horizontal synchronization signal MHsync output from the flip-flop 106 and counts the number of clocks in the horizontal synchronization period;

A fifth latch 110 for latching and outputting the number of clocks output from the counter 109 by the digital horizontal synchronization signal MHsync;

The digital horizontal synchronization signal MHsync is configured to be flip-flops 111-113 for outputting the digital horizontal synchronization signal MHsync delayed three clocks by three clock delays by the system clock signal F_clk.

FIG. 4 is a detailed circuit diagram of the line jitter calculating unit 200 in FIG. 2.

A subtractor 201 which subtracts and outputs the reference level value Thr for the horizontal synchronous separation and the second horizontal synchronous separation point value B;

(202) subtracting the first horizontal synchronous separation point value (A) and the second horizontal synchronous separation point value (B);

A divider 203 for dividing and outputting a signal output from the subtractor 201 into a signal output from the subtractor 202;

A flip-flop 204 for delaying a signal output from the divider 203 by a digital horizontal synchronization signal MHysnc and outputting a first separation error signal Herror1;

A flip-flop 205 for delaying the first separated error signal Herror1 output from the flip-flop 204 by the digital horizontal synchronization signal MHysnc and outputting a second error signal Herror2;

A subtractor 206 for subtracting the second error signal Herror2 output from the flip flop 205 from the first error signal Herror1 output from the flip flop 204 and outputting an error difference value;

An adder 207 which adds and outputs the error difference value output from the subtractor 206 and the number N of clock signals in one horizontal synchronizing period output from the horizontal synchronizing converter 100;

A multiplier 208 that multiplies a signal added and output from the adder 207 by a system clock signal F_clk and outputs an actual horizontal dynamic period L_current;

And a subtractor 209 which outputs a line jitter DELTA Tline by subtracting the standard horizontal drive section L_standard from the actual horizontal drive section L_current output from the multiplier 208.

5 is a detailed circuit diagram of the carrier color signal correction unit 300 in FIG.

A multiplier 301 which multiplies and outputs the line jitter ΔTline and a constant K determined by the system;

An adder 302 for adding and outputting a signal multiplied by the first standard low-conversion carrier color signal Fcu1 and the multiplier 301,

An absolute value (ABS) 303 for taking an absolute value of the signal added from the adder 302 and outputting the absolute value;

A divider 304 for dividing the second standard low-conversion carrier color signal Fcu2 by taking the absolute value from the absolute value 303 and dividing the quotient and the rest;

An exclusive oragate 305 for performing a beta logical sum of the quotient output from the divider 304 and the most significant bit MSB of the signal output from the adder 302;

An adder 306 for adding and outputting a third standard low-conversion carrier color signal Fcu and a signal output from the exclusive oragate 306,

A latch 307 for outputting the signal added from the adder 306 in synchronization with the digital horizontal synchronization signal 3DMHysnc delayed by three clocks;

A latch 308 for outputting a third corrected low conversion carrier color signal NFcu3 corrected by synchronizing a signal output from the latch 307 with a system clock signal F_clk;

An exclusive oragate 309 which exclusively combines the remainder output from the divider 304 and the most significant bit MSB of the signal added and output from the adder 302, and

An AND gate 310 for logically outputting the signal added from the adder 302 and the second standard low-conversion carrier color signal Fcu2;

An adder 311 that adds and outputs a signal added and output from the adder 302, a signal output from the exclusive oragate 309, and a signal OR-output from the AND gate 310;

A latch 312 which outputs the signal added from the adder 311 in synchronization with the digital clock signal 3DMHysnc which is delayed by three clocks;

And a latch 313 for outputting a first corrected low-conversion carrier color signal NFcu1 corrected by synchronizing the signal output from the latch 312 with the system clock signal F_clk.

FIG. 6 is a detailed circuit diagram of the modulo counter 400 of FIG. 1.

An adder 401 for adding and outputting the first corrected low-conversion carrier color signal NFcu1 and the signal output from the buffer 403;

A modulo FCU2 402 for counting and outputting a signal added from the adder 401 to a module and outputting a carry signal when the counting value becomes a set value;

A buffer 403 which inputs a counting value output from the modulo Fcu2 402 and buffers and outputs it by a system clock signal F_clk;

An adder 404 for adding and outputting a carry signal output from the modulo Fcu2 402 and a signal buffered and output from the buffer 406 and a third corrected low-conversion carrier color transmission color code NFcu3;

A modulo FCU4 (405) for calculating a signal added and output from the adder (404) by a module and outputting a predetermined value;

A buffer 406 for buffering and outputting a logic value output from the modulo Fcu4 405 by a system clock signal F_clk;

An adder 407 that adds and outputs ½ values of the signal buffered and output from the buffer 406 and the second standard low-conversion color transport signal Fcu2 or the fourth standard low-conversion color transport signal Fcu4;

A MUX 408 for selecting and outputting one of the buffered output signal from the buffer 406 and the signal output from the adder 407 by a system clock signal F_clk;

And a ROM 409 for inputting a signal output from the MUX 409 to output a signed low-conversion carrier color signal SINFcu and a cosine low-conversion carrier color signal COSFcu.

7 is an operating waveform diagram of each part applied to the present invention.

One preferred embodiment of the present invention will be described in detail with reference to FIGS.

The horizontal synchronizing converter 100 inputs the analog horizontal synchronizing signal and the system clock signal F_clk to extract the horizontal synchronizing split point value, and the number of clocks in one horizontal synchronizing period, the digital horizontal synchronizing signal (MHsync), and three clock delays. Outputs the digital horizontal sync signal (3DMHsync). The line jitter calculating unit 200 inputs the horizontal synchronous split point value, the digital horizontal synchronous signal (3DMHsync), and the number of clocks in the horizontal synchronous clock output from the horizontal synchronous converter 100 to the actual horizontal sync interval. Is calculated, and the line jitter amount is calculated by subtracting the standard horizontal drive mechanism from the actual horizontal drive mechanism. The carrier color signal correcting unit 300 inputs the standard low frequency conversion carrier color signal Fcu and the line jitter amount output from the line jitter calculating unit 200 to output the corrected low frequency conversion carrier color signal. The modulo counter 400 inputs the low frequency conversion carrier color signal corrected from the carrier color signal correcting unit 300 and the standard low frequency conversion carrier color signal to generate a new low frequency conversion carrier color signal for automatic frequency adjustment.

The operation of generating a new low-conversion carrier color signal as described above will be described in detail with reference to FIGS. 3 through 7. In FIG. 3, the first latch 101 has an analog horizontal synchronization signal with FIG. 7B. (Hsync) is input and latched to the system clock signal F_clk as shown in FIG. 7A to output. The second latch 102 latches and outputs the horizontal synchronizing signal latched output from the first latch 101 again. The subtractor 103 subtracts and outputs the reference level value Thr for the horizontal synchronization separation from the analog horizontal synchronization signal latched from the first latch 101. The subtractor 104 subtracts and outputs the reference level value Thr for horizontal sync separation from the horizontal sync signal latched from the second latch 102. The OR gate 105 multiplies the signal subtracted and output from the subtractor 103 by the signal subtracted and output from the subtractor 104 and outputs a signal as shown in FIG. 7C. The flip-flop 106 delays a signal output from the oragate 105 by a system clock signal F_clk and outputs a digital horizontal synchronization signal MHsync as shown in FIG. 7D. The third latch 107 receives the latch output signal from the second latch 102 and latches the signal by the horizontal synchronization signal MHsync, so that the second horizontal synchronization separation point value B as shown in FIG. ) The fourth latch 108 receives the latch output signal from the first latch 101 and latches the signal by the horizontal synchronization signal MHsync, so that the first horizontal synchronization point value A as shown in FIG. ) The counter 109 is loaded by the digital horizontal synchronization signal MHsync output from the flip-flop 106 and counts the number of clocks in the horizontal synchronization section as shown in FIG. 7F. The fifth latch 110 latches the number of clocks output from the counter 109 by the bumped horizontal synchronization signal MHsync and outputs the same as in FIG. 7G. The flip-flop 111-113 delays the digital horizontal synchronization signal MHsync by three clocks by the system clock signal F_clk and outputs the digital horizontal synchronization signal 3MHsync which is three clock delayed as shown in FIG. 7E. .

The subtractor 201 outputs a separation error signal Herror by subtracting the reference level value Thr for the horizontal synchronous separation and the second horizontal synchronous separation point value B. The subtractor 202 subtracts the second horizontal synchronous separation point value B from the first horizontal synchronous separation point value A to output one period signal T_clk of the system clock signal F_clk. The divider 203 divides the signal output from the subtractor 201 into one period signal T_clk of the system clock signal F_clk output from the subtractor 202. The flip-flop 204 delays the signal output from the divider 203 by the digital horizontal synchronizing signal MHsync, so that the first separation error signal (see FIG. 7J) ) Flip-flop 205 is the first separation error signal (output from the flip-flop 204) ) Is delayed by the digital horizontal synchronization signal (MHsync) so that the second separation error signal (see FIG. ) The subtractor 206 is a first separation error signal (outputted from the flip-flop 204). From the flip-flop 205, the second separation error signal ( ) And subtract the error difference value. The adder 207 adds and outputs the error difference value output from the subtractor 206 and the number N of clock signals in one horizontal synchronizing period output from the horizontal synchronizing converter 100. The multiplier 208 multiplies the time T_clk corresponding to one period of the system clock signal F_clk used to separate the horizontal synchronization by adding the output signal added from the adder 207 to output the actual horizontal synchronization mechanism L_current. . The subtractor 209 subtracts the standard horizontal drive mechanism L_standard from the actual horizontal drive mechanism L_current output from the multiplier 208 to output a line jitter DELTA Tline.

The multiplier 301 multiplies and outputs the line jitter DELTA Tline output from the subtractor 209 and a constant K determined by the system. The adder 302 adds and outputs the first standard low-conversion carrier color signal Fcu1 and the signal multiplied by the multiplier 301. The absolute value (ABS) 303 takes an absolute value and outputs the signal added from the adder 302. The divider 304 divides the second standard low-conversion carrier color signal Fcu2 into a signal obtained by taking the absolute value from the absolute value 303, and outputs a quotient and the remainder. The exclusive oragate 305 exclusively combines the quotient output from the divider 304 and the most significant bit MSB of the signal added and output from the adder 302. The adder 306 adds and outputs the third blunt low-conversion carrier color signal Fcu3 and the signal output from the exclusive oar gate 306. The latch 307 outputs a signal PNFcu3 as shown in FIG. 7M by synchronizing the signal added from the adder 306 with the predetermined horizontal delayed digital horizontal synchronization signal 3DMHysnc. The latch 308 outputs the third corrected low-conversion carrier color signal NFcu3, which is corrected as shown in FIG. 7, by synchronizing the signal output from the latch 307 with the system clock signal F_clk. The exclusive oragate 309 exclusively combines the remainder output from the divider 304 and the most significant bit MSB of the signal added and output from the adder 302. The AND gate 310 logically outputs the signal added from the adder 302 and the second standard low-conversion carrier color signal Fcu2. The adder 311 adds and outputs a signal added and output from the adder 302, a signal output from the exclusive oragate 309, and a logical output signal from the AND gate 310. The latch 312 outputs a signal PNFcu1 as shown in FIG. 7L by synchronizing the signal added from the adder 311 with the three clock delayed digital horizontal synchronization signal 3DMHysnc. The latch 313 outputs the first corrected low-conversion carrier color signal NFcu1 corrected as shown in FIG. 7N by synchronizing the signal output from the latch 312 with the system clock signal F_clk.

As described above, the corrected low frequency conversion carrier color signal NFcu considering the jitter component may be represented by the following equation.

ΔTcu = time component of the line jitter corresponding to one cycle of the standard low conversion carrier color signal (Fcu), ΔTline = actual time interval of the _writer , and Cyc _Fcu = total number of cycles of the standard low conversion carrier color signal (Fcu) to be.

Suppose the interval time Tcu for one cycle of the standard low-conversion carrier color signal (Fcu),

Where NFcu is the corrected low-conversion carrier color signal.

Since ΔTcuTcu, the equation is further simplified by using this relationship.

In the above formula (3) Substituting the final frequency is shown in the following equation (4).

The generation of the jitter compensated frequency signal NEWFcu using the modulo counter may be represented by the following equation.

To generate the low-conversion carrier color signal NFcu corrected using Equation (5),

Becomes here Are constants that are system dependent

Set any constant value to K because it is a function of Fcu1, Fcu2, Fcu3, Tcu, Cyc _Fcu .

Becomes In order to make the equation (6) finally form the modulo counter, the value of ΔTlinexK is changed as the line jitter amount (= ΔTline) changes, so Fcu1 and Fcu3 must be replaced with new variable values for each line. . The decision method of these variables is as follows.

Becomes

If F _cu1- △ TlinexK ≥0, NFcu3 = Fcu3 + M, NFcu1 = R,

If F _cu1 -ΔTlinexK ≤ 0, NFcu3 = Fcu3-M-1, NFcu1 = Fcu2-R.

The modulo counter using the newly obtained variables NFcu1 and NFcu3 as described above may be configured by the following equation (7).

The operation of FIG. 6 for the modulo counter to satisfy Equation (7) as described above is as follows.

The first to third corrected low-conversion carrier color signals Fcu1 and Fcu3 output from the latches 308 and 313 are applied to the adders 401 and 404 of FIG.

Accordingly, the trailing device 401 adds the first corrected low-conversion carrier color signal NFcu1 and the signal output from the buffer 403 as shown in FIG. The modulo Fcu2 402 counts and outputs the signal added from the adder 401, and outputs a carry signal when the counting value becomes a set value. The buffer 403 inputs a counting value output from the modulo Fcu2 402 to buffer the output by the system clock signal F_clk. The adder 404 adds and outputs a carry signal output from the modulo Fcu2 402 and a signal buffered and output from the buffer 406 and a third corrected low-conversion carrier color transmission color arc NFcu3. The modulo Fcu4 405 calculates the signal added by the adder 404 with the set value and outputs a predetermined logic value. The buffer 406 buffers and outputs the logic value output from the modulo Fcu4 405 by the system clock signal F_clk. The adder 407 adds and outputs the buffered output signal from the buffer 406 and the second standard low conversion color transfer signal Fcu2 or the fourth standard low conversion color transfer signal Fcu4. The MUX 408 selects and outputs a signal buffered from the buffer 406 and a signal output from the adder 407 by a system clock signal F_clk. The ROM 409 inputs a signal selected and output from the MUX 409 to alternately output a signed low-conversion carrier color signal SINFcu and a cosine low-conversion carrier color signal COSFcu as shown in FIG. 7P. . The ROM 409 is composed of a lookup table, and alternately outputs a low-conversion carrier color signal SINFcu and a cosine low-conversion carrier color signal COSFcu, which are wrapped by an address selected and output from the MUX 408. .

As described above, the present invention has an advantage in that the image processing system digitally performs automatic frequency adjustment to compensate for jitter generated according to the characteristics of the head or tape, thereby reproducing a clear image quality.

In addition, the present invention has the advantage of compensating the analog PLL to be recovered after a few lines to automatically return to the automatic frequency adjustment when the PLL circuit for automatic frequency adjustment in the analog system is returned to the original state after a large jitter occurs.

Claims (12)

In a digital automatic frequency control device, an analog horizontal synchronization signal and a system clock signal (F_clk) are input to extract horizontal synchronization separation point values, and the horizontal number outputs the number of clocks and a digital horizontal synchronization signal (MHsync) within one horizontal synchronization period. The actual horizontal synchronizing unit is calculated by the system clock by inputting the synchronous converting unit, the horizontal synchronizing split point value output from the horizontal synchronizing converting unit, and the number of clocks in the horizontal synchronizing unit, and the standard horizontal synchronizing unit is calculated from the actual horizontal synchronizing unit. A line jitter calculating means for calculating the line jitter amount by subtracting?, And a carrier color signal correction for outputting a corrected low frequency conversion carrier color signal by inputting a standard low frequency conversion carrier color signal Fcu and the line jitter amount output from the line jitter calculating means. Means, and a low-conversion carrier color arc corrected from the carrier color signal correction means and a standard low-conversion carrier color A digital automatic frequency control device comprising a modular counter that generates a new low-conversion carrier color signal for automatic frequency adjustment by entering a call. The horizontal synchronization converting means according to claim 1, wherein the horizontal synchronization converting means comprises a digital horizontal synchronizing means for generating a digital horizontal synchronizing signal by inputting a horizontal synchronizing signal (Hsync) to a system clock (F_clk) signal and a horizontal synchronizing signal (Hsync). A horizontal synchronous split point value extracting means for inputting a system clock (F_clk) signal to extract a horizontal synchronous split point value by the digital horizontal synchronous signal, and a system clock signal in a horizontal synchronous section inputted to the digital horizontal synchronous signal And a clock signal counting means for counting and outputting the counted number. 3. The digital horizontal synchronous generating means comprises: a first latch (101) for latching a horizontal synchronous signal (Hsync) to a system clock (F_clk) signal, and a horizontal latch output from the first latch (101). A second latch 102 for latching and outputting the synchronization signal again; a subtractor 103 for subtracting and outputting the horizontal synchronization signal latched from the first latch 101 and a reference level value for horizontal synchronization separation; A subtractor 104 which subtracts and outputs the horizontal synchronous signal latch output from the second latch 102 and the reference level value Thr for the horizontal synchronous separation, a signal subtracted and output from the subtractor 103 and the subtractor 104. A digital horizontal synchronization signal (MHsync) by inputting a subtracted output signal from < RTI ID = 0.0 > (0) < / RTI > and a predetermined delay by the system clock signal F_clk. Characterized in that the flip-flop 106 to output Digital automatic frequency regulator The method of claim 3, wherein the horizontal synchronous split point extracting means comprises: a first latch (101) for latching a horizontal synchronous signal (Hsync) to a system clock (F_clk) signal, and a latch output from the first latch (101). A second latch 102 for latching and outputting the latched horizontal sync signal again and a signal output latched from the second latch 102 and latched by the horizontal sync signal MHsync to generate a second horizontal sync split point. A third latch 107 for outputting a value B and a signal latched out from the first latch 101 are input and latched by the horizontal synchronization signal MHsync to obtain a first horizontal synchronization separation point value A. Digital latch, characterized in that consisting of a fourth latch 108 outputs. 5. The counter of claim 4, wherein the clock signal counting means is loaded by a digital horizontal synchronization signal (MHsync) output from the flip-flop (106) and counts the number of clocks in the horizontal synchronization section, and the counter And a fifth latch (110) for latching and outputting the number of clocks outputted from (109) by the digital horizontal synchronization signal (MHsync). The digital automatic frequency control device as claimed in claim 2, further comprising a flip-flop for outputting a predetermined clock delay of the digital horizontal synchronization signal (MHsync) by a system clock signal (F_clk). 7. The apparatus according to claim 6, wherein the line jitter calculating means comprises: a subtractor 201 for subtracting and outputting a reference level value Thr for horizontal synchronous separation and the second horizontal synchronous separation point value B; (202) subtracting the synchronous separation point value (A) and the second horizontal synchronous separation point value (B), and dividing and outputting a signal output from the subtractor 201 into a signal output from the subtractor 202. A flip-flop 204 for delaying the signal output from the divider 203 by the digital horizontal synchronization signal MHysnc and outputting a first separation error signal from the flip-flop 204 The flip-flop 205 outputs the second separated error signal by delaying the outputted first separated error signal by the digital horizontal synchronization signal MHysnc, and the first separated error signal output from the flip-flop 204. An error difference value is output by subtracting the second separation error signal output from the flip-flop 205. A subtractor 206, an adder 207 that adds and outputs an error difference value output from the subtractor 206 and a number N of clock signals in one horizontal synchronizing period output from the horizontal synchronizing converter 100; A multiplier 208 for multiplying the signal added and outputted from 207 by the system clock signal F_clk and outputting an actual horizontal drive period L_current, and an actual horizontal drive period L_current output from the multiplier 208; A subtractor (209) for outputting line jitter (△ Tline) by subtracting the standard horizontal dynamic period (L_standard) from the). The carrier color signal correcting means according to claim 7, wherein the carrier color signal correcting means includes: a multiplier 301 for multiplying and outputting the line jitter? Tline and a constant K, a first standard low-conversion carrier color signal Fcu1, and the multiplier ( An adder 302 for adding and outputting a signal multiplied by 301, an absolute value (ABS) 303 for taking an absolute value of the added signal from the adder 302, and outputting the second standard low-conversion carrier color signal; The divider 304 outputting the quotient and remainder by dividing the signal obtained by taking the absolute value from the absolute value 303 from the absolute value 303, and the quotient output from the divider 304 and the adder output from the adder 302. Exclusive o-gate 305 for exclusively adding and outputting the received signal, and an adder 306 for adding and outputting a third standard low-conversion carrier color signal Fcu and a signal output from the exclusive o-gate 306. ) And a signal added from the adder 306 by a predetermined clock. A latch 307 for outputting in synchronization with the delayed digital horizontal synchronization signal and a third corrected low-conversion carrier color signal NFcu3 corrected by synchronizing the delayed output signal from the latch 307 with the system clock signal F_clk. An exclusive oragate 309 for exclusively combining and outputting the latch 308, the remainder output from the divider 304, and the signal output from the adder 302, and the adder 302. An AND gate 310 for logically outputting the added signal and the second standard low-conversion carrier color signal Fcu2, a signal output from the adder 302, and a signal output from the exclusive oar gate 309. And an adder 311 for adding and outputting a signal multiplied by the AND gate 310, and outputting the signal added from the adder 311 in synchronization with a predetermined clock delayed digital horizontal synchronization signal 3DMHysnc. Value 312 and a latch 313 for outputting a first corrected low-conversion carrier color signal NFcu1 corrected by synchronizing a signal output from the latch 312 with a system clock signal F_clk. Digital frequency adjuster. The modulator according to claim 8, wherein the modulo counter adds from the first corrected low-conversion carrier color signal (NFcu1) and the signal output from the buffer (403) and the adder (401). Counts and outputs the counted signal, and outputs a carry signal when the counting value becomes a set value, and inputs a counting value output from the modulo Fcu2 402 and the modulo Fcu2 402 to input a system clock signal (F_clk). A buffer 403 for buffering and outputting, a carry signal output from the modulo Fcu2 402, a signal buffered and output from the buffer 406, and a third corrected low-conversion carrier color transmission color arc (NFcu3). A modulator Fcu4 405 for calculating a predetermined logic value by calculating an adder 404, a signal added and output from the adder 404 with a set value, and a logic value output from the modulo Fcu4 405. Buffer 4 buffered and output by clock signal F_clk 06), an adder 407 which adds and outputs the signal buffered and output from the buffer 406 and the second standard low conversion color transfer signal Fcu2 or the fourth standard low conversion color transfer signal Fcu4; MUX 408 for selecting and outputting one of the buffered output signal from the buffer 406 and the signal output from the adder 407 by a system clock signal F_clk, and a signal selected and output from the MUX 409. And a ROM (409) for inputting and outputting a signed low frequency conversion carrier color signal (SINFcu) and a cosine low frequency conversion carrier color signal (COSFcu). The method of claim 1, wherein the line jitter calculating means comprises: a subtractor 201 for subtracting and outputting a reference level value Thr for horizontal synchronous separation and the second horizontal synchronous separation point value B; Subtracting (202) the synchronous separation point value (A) and the second horizontal synchronous separation point value (B), and dividing and outputting the signal output from the subtractor 201 into the signal output from the subtractor 202. A flip-flop 204 for delaying the signal output from the divider 203 by the digital horizontal synchronization signal MHysnc and outputting a first separation error signal from the flip-flop 204 From the flip-flop 205 outputting the second error signal by delaying the outputted first separated error signal by the digital horizontal synchronization signal MHysnc, and from the first error signal Herror1 output from the flip-flop 204. The second error signal output from the flip-flop 205 is subtracted to output an error difference value. An adder 206, an adder 207 that adds and outputs an error difference value output from the subtractor 206 and the number N of clock signals in one horizontal conduit section output from the horizontal synchronization converter 100; A multiplier 208 for multiplying the signal added and output from the adder 207 with a system clock signal F_clk to output an actual horizontal drive mechanism L_current, and an actual horizontal drive mechanism L_current output from the multiplier 208. A subtractor (209) for outputting line jitter (△ Tline) by subtracting the standard horizontal dynamic period (L_standard) from the). 2. The apparatus of claim 1, wherein the carrier color signal correcting means includes: a multiplier 301 for multiplying and outputting the line jitter? Tline and a constant K, a first standard low-conversion carrier color signal Fcu1, and the multiplier ( An adder 302 for adding and outputting a signal multiplied by 301, an absolute value 303 for taking an absolute value of the added signal from the adder 302, and outputting the second standard low-conversion carrier color signal Fcu2. The divider 304 outputs the quotient and the remainder by dividing the signal taking the absolute value from the absolute value 303, and the quotient output from the divider 304 and the signal output from the trailing device 302. An exclusive oragate 305 for outputting the exclusive logic summation, an adder 306 for adding and outputting a third standard low-conversion carrier color signal Fcu3 and the signal output from the exclusive oragate 306; And adds a signal added from the adder 306 to a predetermined clock. A latch 307 for outputting in synchronization with the connected digital horizontal synchronization signal, and a third corrected low-conversion carrier color signal NFcu3 corrected by synchronizing the signal output from the latch 307 with the system clock signal F_clk. An exclusive oragate 309 for exclusively combining and outputting the latch 308, the remainder output from the divider 304 and the signal added and output from the adder 302, and the adder 302. An AND gate 310 for logical AND output of the added signal and the second standard low-conversion carrier color signal Fcu2, a signal output from the adder 302, and a signal output from the exclusive oragate 309 And an adder 311 for adding and outputting the AND signal 310 outputted from the AND gate 310, and a latch 312 for synchronizing the signal added from the adder 311 with a digital clock signal delayed by a predetermined clock. And a latch 313 for outputting a first corrected low-conversion carrier color signal NFcu1 corrected by synchronizing a signal output from the latch 312 with a system clock signal F_clk. Adjuster. The modulator according to claim 1, wherein the modulo counter includes an adder 401 for adding and outputting the first corrected low-conversion carrier color signal NFcu1 and the signal output from the buffer 403, and a signal added from the adder 401. Counts and outputs the modulated value, and outputs a carry signal when the counted value becomes a set value. The counted value output from the modulo Fcu2 402 is input to the system clock signal F_clk. An adder that adds and outputs a buffer 403 buffered and output, a carry signal output from the modulo Fcu2 402, a signal buffered and output from the buffer 406, and a third corrected low-conversion carrier color transmission color code NFcu3 ( 404 and a modulo Fcu4 405 for calculating a predetermined logic value by calculating a signal added and output from the adder 404 with a set value, and a system clock signal for a logic value output from the modulo Fcu4 405. A buffer 406 buffered and output by (F_clk), An adder 407 that adds and outputs the buffered output signal from the buffer 406 and the second standard low-conversion color transport signal Fcu2 or the fourth standard low-conversion color transport signal Fcu4, and the buffer 406 MUX 408 which selects and outputs the buffered output signal from the adder 407 and the signal output from the adder 407 by a system clock signal F_clk; And a ROM (409) for outputting the converted carrier color signal (SINFcu) and the cosine low-conversion carrier color signal (COSFcu).