JP3612465B2 - Image coding / decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image encoding / decoding device, and more particularly to an image encoding / decoding device that samples and transmits a color television signal on a transmission side and decodes and reproduces a received signal on a reception side using a reproduction sampling clock.
[0002]
[Prior art]
In a digital color television (hereinafter abbreviated as TV) system, an analog color TV signal is sampled (sampled or digitized) with a sampling clock on the transmission side and encoded and transmitted. On the receiving side, the sampling clock is reproduced, and the digital image signal is D / A (digital / analog) converted with the sampling clock to reproduce the analog TV signal.
[0003]
As a conventional example (1) of such a device, a method for reproducing a sampling clock on the receiving side is performed by transmitting frequency information and sampling so that the number of sampling clocks in a fixed period is the same for both transmission and reception. There is a method of performing frequency synchronization (see, for example, Japanese Patent Application No. 52-117613). In this conventional method, the transmission side samples the sampling clock count value at regular intervals and sends it to the reception side as integer value count information (frequency information). The reception side regenerates the sampling clock based on this frequency information. To do. Since the frequency of the reproduction sampling clock is controlled based on the count value of the integer value obtained at regular intervals, a stable frequency with higher accuracy than the accuracy (integer) of the count value (frequency information) cannot be obtained. Further, the reproduced sampling clock frequency has a drawback that it fluctuates due to the influence of a quantization error obtained by quantizing the frequency information into an integer, and the color subcarrier (subcarrier, hereinafter abbreviated as SC) of the reproduced TV signal. The stability was not high enough.
[0004]
For example, when sampling is performed at a frequency four times that of the SC, one clock of the sampling frequency corresponds to ¼ of the frequency of the color SC, so that the magnitude of the quantization error of one count value is 90 degrees. This caused a phase shift. If the analog TV signal on the transmission side and the reproduced TV signal on the reception side are directly compared on the vector scope (phase measuring device) due to the influence of this quantization error, the sampling clock phase shift (change in relative phase) ), The relative phase angle of both color bursts fluctuates greatly, and the vector on the receiving side changes rotationally with respect to the transmitting side. For this reason, when a color TV signal is edited using the decoded signal, a phase synchronizer such as a frame synchronizer is required to synchronize the phase of the color burst. Further, since the frequency of the color SC of the TV signal in the broadcasting station is stable, it has been conventionally considered to use this as a reference signal. An organization of the Ministry of Posts and Telecommunications publishes measurement data of SC frequency deviation at each broadcasting station. In this case, the frequency stability is about 10 to the 11th power, and high-precision stability is required. In the method of the conventional example (1), it is difficult to reproduce a TV signal with such high frequency accuracy on the receiving side, no matter how high and stable the SC on the transmitting side is.
[0005]
On the other hand, in order to obtain high accuracy, there is a method of encoding and transmitting an image signal by synchronizing a transmission path clock with a sampling clock. In this case, restrictions such as the fact that the transmission line cannot be placed on a standard transmission line network, the transmission line clock fluctuates depending on the SC of the TV signal, and the transmission line clock fluctuates due to switching of the TV signal to be transmitted. There is. There was a drawback that it could not be used universally. As a method of solving this, instead of sending an integer count value as frequency information, the transmission side samples and obtains a signal at that phase angle from a phase reference signal synchronized with the sampling clock phase, It is multiplexed with the video signal and transmitted to the receiving side. On the receiving side, there is a method of performing phase synchronization based on the transmitted phase angle signal.
[0006]
As a conventional example (2), there is a “sampling clock recovery system and apparatus” disclosed in Japanese Patent Application Laid-Open No. 8-1226029. This prior art can be regarded as a method of sending count information with precision below the decimal point, from a different perspective. FIGS. 12A and 12B are block diagrams of the transmission side and the reception side of the conventional example (2), respectively. 13 shows a detailed configuration of the phase angle generation circuit 206 in FIG. 12A, and FIG. 14 shows a configuration of the phase comparison circuit 216 in FIG. First, in FIG. 12A, an A / D converter 201 to which a TV signal is input, an SC generation circuit 203, a sampling clock generation circuit 202, an encoding circuit 204, a multiplexing circuit 205, a phase angle generation circuit 206, A transmission clock generation circuit 207 and a control circuit 208 are included. The SC generation circuit 203 generates an SC signal in synchronization with the color SC of the input TV signal, and supplies it to the phase angle generation circuit 206 and the sampling clock generation circuit 202. The sampling clock generation circuit 202 generates a sampling clock and supplies it to the A / D converter 201. The A / D converter 201 samples the TV signal and outputs a digital signal to the encoding circuit 204. The encoding circuit 204 performs data compression encoding on the digital TV signal and supplies the encoded data to the multiplexing circuit 205.
[0007]
As shown in FIG. 13, the phase angle generation circuit 206 includes an adder 221, a phase angle circuit 222, a register 223, a sine wave generation circuit 224, a D / A converter 225, and a comparator 226. The phase angle for each clock generated by the phase angle circuit 222 is integrated for each transmission path clock by an integrator composed of an adder 221 and a register 223 to obtain the phase angle for each transfer clock, and the sine wave generation circuit 224 This is supplied to the multiplexing circuit 205. The sine wave generation circuit 224 generates a digital sine wave corresponding to this phase angle and performs D / A conversion by the D / A converter 225. Then, the comparator 226 compares the phase with the SC signal supplied from the SC generation circuit 203, supplies the error signal to the phase angle circuit 222, corrects the value of the next phase angle, and controls the phase to match. To do. The phase angle of the reference signal at each sampling time by the transmission clock is obtained by setting one cycle of SC (reference signal) to 360 °. 360 ° is normalized with an N-bit dynamic range, and the value of the phase angle for each transmission path clock is obtained as an N-bit phase angle signal. According to the control signal from the control circuit 208, the phase angle signal for each fixed period. Is extracted and supplied to the multiplexing circuit 205. The transmission clock generation circuit 207 generates a transmission clock and supplies it to the multiplexing circuit 205, the control circuit 208 and the phase angle generation circuit 206. The control circuit 208 generates a frame control signal for constructing a frame and a timing control signal for controlling a cycle for sending the phase angle signal. The frame control signal is sent to the multiplexing circuit 205, and the timing control signal is sent to the phase angle generation circuit. 206. The multiplexing circuit 205 multiplexes compressed data, phase angle signals, and other control data necessary for decoding based on the control signal, and outputs a transmission signal.
[0008]
On the other hand, the receiving side shown in FIG. 12B includes a separation circuit 209 and a transmission clock recovery circuit 210, a control circuit 211, a decoding circuit 212, an SC recovery circuit 213, a D / A converter 214, a sample to which a reception signal is input. And a phase comparison circuit 216. As shown in FIG. 14, the phase comparison circuit 216 includes an adder 221, a phase angle circuit 222, a register 223, a sine wave generation circuit 224, a D / A converter 225, a comparator 226, and a comparison circuit 227. The The transmission clock recovery circuit 210 recovers the transmission clock and supplies it to the separation circuit 209, the control circuit 211, and the phase comparison circuit 216. Based on the control signal from the control circuit 211, the separation circuit 209 separates the compressed data, the phase angle signal, the control data necessary for decoding, and the like and supplies them to each unit. The control circuit 211 detects a frame from the transmission signal, sends a control signal for separating the data multiplexed in the frame to the separation circuit 209, and obtains a phase angle signal on the receiving side for each frame period. A control signal is supplied to the phase comparison circuit 216. The decoding circuit 212 decodes the compressed data, reproduces the digital TV signal, and is converted into an analog signal by the D / A converter 214. The sampling clock recovery circuit 215 controls the VCO according to the control signal of the differential signal from the phase comparison circuit 216, and outputs the phase angle signal sent from the transmission side and the phase angle signal obtained on the reception side. The oscillation frequency of the reproduction sampling clock is controlled so that the phase angles of the SC signals to be transmitted and received are synchronized. The recovered sampling clock is supplied to the D / A converter 214. The SC generation circuit 213 reproduces the continuous sine wave SC in synchronization with the color verse of the reproduced TV signal and supplies it to the phase comparison circuit 216.
[0009]
The phase comparison circuit 216 shown in FIG. 14 obtains the phase angle on the reception side from the regenerated SC and the transmission path clock in the same manner as the phase angle generation circuit 206 on the transmission side, and receives the phase angle signal on the transmission side. The comparison circuit 227 compares the transmitted and received phase angle signals every frame period and outputs a comparison error signal. The error signal is supplied to the sampling clock recovery circuit 215. The sampling clock recovery circuit 215 controls the VCO (voltage controlled oscillator) based on the phase angle difference signal of the error signal, and controls the recovered sampling clock so that the SC phases match. Usually, since the transmission time of the transmission path clock is a constant and stable clock, the phase of the color burst of the reproduced TV signal becomes the color burst on the transmission side by synchronizing the SC phase of transmission and reception with the above configuration. Phase synchronized. As a result, the phase of the sampling clock and the phase of the sampling clock on the receiving side are synchronized. That is, in this method, the phase angle generation circuit 206 generates a phase angle value as a digital value for each transmission line clock, reads out the PCM value of a sine wave from the corresponding ROM, and performs D / A conversion. To generate an analog sine wave local SC signal. Then, the phase comparison between the local SC signal and the reference SC obtained from the video signal is performed. The comparison error signal is feedback-controlled to the phase angle generation value, and the phase angle is controlled so that the local SC and the reference SC coincide with each other, so that the phase angle of the reference SC is equivalently obtained as a digital phase angle value. The obtained phase angle value is transmitted to the receiving side at regular intervals.
[0010]
On the other hand, the reception side obtains the reproduction SC from the reproduced TV signal, and the phase comparison circuit 216 obtains the local SC synchronized with the reproduction SC in the same manner as the transmission side, thereby obtaining the phase angle of the reproduction SC. The phase angle of the SC on the transmission side and that on the reception side are compared for each period sent from the transmission side. Using this comparison result, the frequency of the recovered clock that is recovered by the sampling clock recovery circuit 215 is controlled so that the phase angles of transmission and reception match. By thus synchronizing the phases, a sampling clock with high frequency accuracy is reproduced.
[0011]
[Problems to be solved by the invention]
The prior art described above has several problems. First, in order to make the local SC signal highly accurate including an analog circuit, a filter with good characteristics is required, and the apparatus becomes large-scale and difficult to put into practical use.
[0012]
Secondly, in order to simplify the filter and obtain highly accurate phase information, the phase angle generation circuit needs to operate at a sufficiently high speed compared to the frequency of the reference SC. In the prior art, the operation clock of the digital processing circuit that generates the phase angle with respect to the reference SC frequency (3.5795 MHz) uses a transmission line clock, and a clock with a high frequency (44.736 MHz in the case of DS1). The power consumption and mounting area increased due to the high-speed processing circuit. Also, a comparator that compares the reference SC and the local SC needs to be able to sufficiently compare at a high frequency.
[0013]
Third, in order to reduce the size of the apparatus, it is necessary to reduce the number of parts by using LSI or processor processing. If the circuit is high-speed processing, high-speed LSI development is required to implement LSI. High speed and high power consumption made it difficult to downsize and expensive. Furthermore, since an analog processing circuit including a D / A converter is required, it is difficult and expensive to make an analog / digital mixed LSI compared to an LSI having only a digital circuit.
[0014]
Fourth, in order to apply the method of the conventional example (2) to the apparatus configured in the conventional example (1), there is a difference between the information to be transmitted as frequency information or phase information. Changes on both the sending and receiving sides were required, and the changes were massive.
[0015]
OBJECT OF THE INVENTION
An object of the present invention is to use a sampling clock recovery circuit capable of reproducing a sampling clock with high frequency accuracy with a simple configuration in a method of reproducing the sampling clock by sending frequency information or phase information of an integer count value. An image encoding / decoding device is provided.
[0016]
[Means for Solving the Problems]
An image encoding / decoding apparatus according to the present invention uses a sampling clock obtained by decoding an image data such as a color TV signal on the transmission side and encoding and transmitting the signal on the transmission side and decoding and reproducing the encoded data from the reception signal on the reception side. This is a device for reproducing the signal described above. The feature is that an averaging circuit that averages the frequency information on the transmission side to obtain highly accurate frequency information, a transmission clock recovery circuit that recovers a transmission clock from the received signal, frequency information from the averaging circuit, and A comparison control circuit that obtains a control signal by comparing received frequency information, a sampling clock recovery circuit that regenerates a sampling clock based on the control signal, and a sampling clock that is sampled with a reference clock from a transmission clock recovery circuit A sampling circuit that obtains the sample value of the sampling clock, an M-dividing counter that divides the reference clock by a predetermined dividing ratio M, and one cycle of the sampling clock from the dividing counter value of the M-dividing counter. The phase shift number generation circuit that generates the phase shift numbers so that the phases are arranged in order, and the frequency information of the sampling clock when sampling by the sampling circuit are obtained in the comparison control circuit. And a frequency phase information generating circuit which force is to sample the decoded signal with the sampling clock.
[0017]
According to the embodiment of the present invention, the reference clock is obtained from a frequency dividing circuit that divides the output from the transmission clock recovery circuit. Phase information is received instead of frequency information, averaged with high accuracy to obtain phase information, and phase information is obtained with high accuracy from the sampling clock to reproduce a sampling clock with high frequency accuracy. By using a clock obtained by switching clocks having the same frequency and different phases in a predetermined order as a reference clock, the same function as that obtained by using a reference clock of substantially high frequency is obtained. In addition, a memory circuit that stores the sample value of the sampling clock in the phase number is provided. As a sampling clock on the transmission side, a frequency four times the SC frequency, a reference clock frequency of 19.44 MHz, and a frequency division ratio M of the M frequency division counter are selected to be 167. Further, the sampling clock frequency on the transmission side is set to 13.5 MHz, the reference clock frequency is set to 19.44 MHz, and the frequency division ratio M of the M frequency division counter is selected to be 36. Furthermore, instead of frequency information, time stamp information is received, and frequency information or phase information averaged with high accuracy is obtained from the time stamp information, and frequency information or phase information is obtained with high accuracy from the reproduction sampling clock. Based on this phase information, a sampling clock with high frequency accuracy is regenerated.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, the configuration and operation of a preferred embodiment of the image encoding / decoding apparatus according to the present invention will be described in detail with reference to the accompanying drawings.
[0019]
According to the present invention, in a device for encoding a TV signal obtained by sampling a sampling clock that is four times the color SC and transmitting it on a 155.52 Mbps transmission line, the frequency information of the sampling clock is transmitted from the transmission side to the reception side. Transmit to. On the receiving side, the frequency information on the transmitting side is averaged, the frequency information on the regenerated sampling clock is obtained to the precision below the decimal point, and the frequency information on the sampling clock on the transmitting side and the receiving side is compared with high precision below the decimal point. . By controlling the frequency of the reproduced sampling clock so as to eliminate the comparison error, it is possible to reproduce a sampling clock that matches the sampling clock frequency on the transmission side with high accuracy, and the frequency accuracy of the color SC of the reproduced TV signal is improved. An image encoding / decoding device using a sampling clock recovery circuit capable of reproducing a TV signal whose frequency coincides with the transmission side with high accuracy is obtained.
[0020]
First, FIG. 1 shows a block diagram of a preferred embodiment of an image encoding / decoding apparatus according to the present invention, where (A) is a transmitting side and (B) is a receiving side. 1A includes an A / D converter 1, an encoding circuit 2, a multiplexing circuit 3, a frequency information generating circuit 4, a sampling clock circuit 5, a control circuit 6, a transmission clock circuit 7, and a frequency dividing circuit. 8 comprises. The A / D converter 1 samples (digitizes) the TV signal into 10 bits. The encoding circuit 2 encodes the digital signal. The multiplexing circuit 3 multiplexes and transmits the encoded signal, the frequency information signal sampled at regular intervals, and other necessary control signals. The sampling clock circuit 5 generates a 14.3 MHz sampling clock synchronized with four times the color burst (SC) of the input TV signal. The frequency information generation circuit 4 counts the number of sampling clocks and resamples the sampling clock frequency count value for each period of the signal supplied from the control circuit 6 to obtain frequency information. The transmission clock circuit 7 generates a transmission clock of 155.52 MHz. The frequency dividing circuit 8 divides the transmission clock by 8 to generate a 19.44 MHz divided transmission clock (reference clock). The control circuit 6 generates a control signal at regular intervals (for example, every cycle obtained by dividing the reference clock by K) in order to send frequency information to the receiving side.
[0021]
The receiving side shown in FIG. 1B includes a separation circuit 13 and a transmission clock recovery circuit 20, a decoding circuit 12, a D / A converter 11, an averaging circuit 15, and a comparison control to which a reception signal via a transmission path is input. The circuit 14 includes a frequency phase information generation circuit 16, a memory circuit 17, a phase number generation circuit 18, a control circuit 19, a sampling clock recovery circuit 21, a sampling circuit 22, an M frequency dividing counter 23, and a frequency dividing circuit 24. . The transmission clock recovery circuit 20 extracts the clock timing from the reception signal described above and recovers the 155.52 MHz transmission clock. The separation circuit 13 separates the encoded signal, frequency information, control signal, and the like from the received signal. The decoding circuit 12 decodes the encoded signal and reproduces the digital image signal. The D / A converter 11 converts a digital image into an analog image signal. The averaging circuit 15 obtains transmission side frequency information averaged from the frequency information sent from the transmission side. The comparison control circuit 14 compares the reception side frequency information with the averaged transmission side frequency information, and generates a control signal so that the phase information on the reception side matches the transmission side. The sampling clock recovery circuit 21 recovers the sampling clock according to the control signal. The frequency dividing circuit 24 divides the transmission clock by 8 to generate a frequency divided clock (reference clock) of 19.44 MHz. The sampling circuit 22 samples the reproduced sampling clock with a 19.44 MHz reference clock and outputs a sample value of a 1-bit sampling clock. The M-dividing counter 23 divides the 19.44 MHz reference clock by 167. The phase number generation circuit 18 generates the phase number i so that the phases of one cycle of the sampling clock are arranged in order from the frequency division counter value n. The memory circuit 17 stores the sample value of the sampling clock in the phase number. The frequency phase information generation circuit 16 calculates the difference between the phase number of the reference phase of the sampling clock obtained from the change point of the sampling values of the sampling clocks arranged in order of the phase number and the phase number corresponding to the M division counter value. The frequency information of the sampling clock at the time of sampling by the sampling circuit 22 is obtained with a precision below the decimal point for every fixed period. The control circuit 19 generates a timing for every fixed period for obtaining frequency information.
[0022]
FIG. 2 shows a specific configuration example of the transmission-side frequency phase information generation circuit 4 shown in FIG. For example, an 8-bit counter 41 that operates with a sampling clock, a register 42 that samples a counter value with a control signal of a transmission cycle from the control circuit 6, a register 43 that delays the output of this register 42 by one control cycle, and both these registers The subtractor 44 calculates the frequency counter value of one control cycle from the difference between 42 and 43 with the precision of the lower 8 bits. The counter 41 is a free counter that counts up every sampling clock, and the counter output is sampled every transmission cycle. From the output of the subtracter 44, the lower 8-bit value of the counter value for one transmission period is output. On the other hand, FIG. 3 shows a specific configuration example of the frequency phase information generating circuit 16 on the receiving side shown in FIG. The shift register 30, determination circuit 31, reference phase number device 32, modulo subtractor 33, register 34, comparator 35, counter 36, converter 37, register 38, register 39 and subtractor 40 are included. Components 30 to 33 constitute a normalized phase number generator 300.
[0023]
Next, the operation of the sampling clock recovery circuit shown in FIG. 1 will be described. The control circuit 6 on the transmission side divides the divided transmission clock (reference clock) of 19.44 MHz by 2430 × 8 × 16 to generate a transmission cycle timing control signal having a frequency of 62.5 Hz, and has a cycle of about 16 ms. The counter value is sampled to obtain frequency information. This transmission period corresponds to about one field (1/60 second) of the TV signal. The count value of the sampling clock of 14.3 MHz in this one cycle is about 0.25 MHz. Since the width of the value represented by the lower 8 bits of the counter value of one transmission cycle is ± 128, frequency information that can cover a frequency variation of about ± 500 ppm is sent. Since an SDH signal with a transmission rate of 155.52 Mbps constitutes a frame of 9 rows × 270 columns of bytes, the frequency information is sampled and sent every 128 times this period.
[0024]
The M dividing counter 23 on the reception side divides the supplied 19.44 MHz divided transmission clock (reference clock) by 167 and outputs a count value n in the range of 0 to 166 to the phase number generation circuit 7. . From the relationship between the sampling clock frequency (14.31818 MHz) and the divided transmission path clock frequency (19.44 MHz), the value of M at which an integral multiple M of the divided transmission clock cycle is substantially equal to an integral multiple of the sampling clock cycle is calculated. Ask. When M = 167, the magnification is 123.0008 times, so M = 167 is set in advance.
[0025]
The phase number generation circuit 18 is between the counter value n and the phase number i.
n = MOD (−19 × i, 167) = MOD (148 × i, 167)
The phase number i corresponding to the input of the counter value n is output. The following characteristic is obtained from the characteristic of n = MOD (−19 × i, 167).
Phase number i = 0, 1, 2, 3, 4,... 165, 166
Counter value n = 0, 148, 129, 110, 91,..., 38, 19
When this is rearranged in the order of n, the relationship becomes i = MOD (123 × n, 167).
Counter value n = 0, 1, 2, 3, 4,..., 165, 166
Phase number i = 0, 123, 79, 35, 158,..., 88, 44
[0026]
In accordance with the characteristics of this conversion table, the phase number i for the counter value n is output. The control circuit 19 divides the divided transmission clock (reference clock) of 19.44 MHz by a value of 2430 × 8 × 16 and generates a timing control signal having a frequency of 62.5 Hz. The frequency phase information generation circuit 16 uses the phase number from the phase number generation circuit 18, the sample value of the sampling clock from the memory circuit 17, and the control signal of the transmission cycle from the control circuit 19, and has 8 bits beyond the decimal point. The count information of a 16-bit reproduction sampling clock having a total precision of 16 bits with 8 bits after the decimal point is obtained and output every transmission cycle. The averaging circuit 15 temporarily stores 8-bit frequency information (integer count information) supplied from the separation circuit 13 for each transmission period, and averages the frequency information over a long period (for example, 128 transmission periods). For each transmission cycle (about 16 ms). In this case, a count value with an accuracy of 7 bits after the decimal point is obtained, and the obtained transmission-side average frequency information is supplied to the comparison control circuit 14.
[0027]
Next, the comparison control circuit 14 subtracts the transmission side averaged frequency information from the reception side reproduction clock frequency information with 16-bit accuracy to obtain a 16-bit comparison error signal (accuracy of 8 bits below the decimal point). . When feedback control is performed from the comparison error signal E, the controlled variable is generally the sum of products of the coefficients α, β, γ of the signals dE, E, ΣE, where dE is the differential signal and ΣE is the integral signal. A frequency control signal C of (α · E + β · E + γ · ΣE) is given. The frequency control signal C is supplied to the sampling clock generation circuit 21 to control the VCXO for clock generation, the reproduction frequency of the sampling clock is controlled, and feedback control is performed so that the comparison error becomes zero. The coefficient β determines the time constant until the frequency becomes constant, the coefficient α determines the pulling acceleration in the frequency change region, and the coefficient γ determines the time constant at which the phase is constant. The control amount is determined in consideration of the voltage response characteristics of the VCXO.
[0028]
The counter value n generated by the M frequency dividing counter 23 in FIG. 1B is supplied and supplied to the reference phase number unit 32 and also to the memory circuit 17 as an address. The shift register 30 shown in FIG. 3 reads the sample value of the sampling clock corresponding to the address of the count value from the memory circuit 17 and holds it. The time when the sample value Yn of the sampling clock changes from Yn−1 = “0” to Yn = “1” is determined as the rising point of the sampling clock, and the reference phase number at this time is (n−1). And However, in applications where the sampling clock frequency fluctuates significantly, the sampling clock cycle fluctuates in time, and the sequence of sample points projected on the phase of one cycle and the sample value are jitter or There is a possibility of going crazy under the influence of errors. Therefore, a case will be described in which determination is made by detecting changes in sample values at three consecutive sample points (n-2), (n-1) and n so that more stable determination can be made. When the address to the memory circuit 17 is i, the shift register 31 supplies three consecutive sample values Yn−2, Yn−1, and Yn including the sample value Yn read from the memory circuit 17 to the determination circuit 31.
[0029]
When Yn-2 = “0”, Yn−1 = “0”, and Yn = “1”, the determination circuit 31 determines that the sampling clock rises, and sets a signal for setting a reference phase number as a reference phase This is supplied to the numbering unit 32. The reference phase number unit 32 delays the input address value n by one clock by the divided transmission clock and supplies it to the reference register as the address value n-1. When the set signal from the determination circuit 31 is received, the reference phase number is set. When Yn−2 = “0”, Yn−1 = “0”, and Yn = “1”, n−1 is set as a reference phase number in indicating the rising point of the sampling clock. The reference phase number is set about once with a frequency dividing period of 167. The modulo subtracter 33 subtracts the reference phase number in supplied from the reference phase number device 32 from the phase number i supplied from the phase number generation circuit 18, but subtracts it by a modulo operation of 167 to obtain a divided transmission clock. The standardized phase number j = MOD (i-in, 167) indicating the phase when the sampling clock is sampled is output.
[0030]
Next, the phase number signal obtained by the normalized phase number generator 300 is supplied to the comparison / determination unit 35, the register 34, and the converter 37. The register 34 outputs a signal delayed by the period of the reference clock. The comparison determination circuit 35 compares the current phase number J with the phase number Jn-1 one clock before. If the phase number exceeds 167, it exceeds the rising point of the sampling clock. Therefore, 167 is subtracted to indicate the phase value from 0 again. Therefore, if Jn <Jn−1, it can be determined that the sampling clock has risen during this period, and one clock is supplied to the counter 36. In other cases, it is determined that the sampling clock does not rise, and the clock is not supplied to the counter 36. The counter 36 is an 8-bit counter, counts the number of rising edges of the sampling clock, and supplies an integer frequency count value to the register 38. The converter 37 normalizes the normalized phase number j with a value of 8 bits (256) after the decimal point and outputs the result. The converter 37 has conversion characteristics for converting the value of 256/167 × j into an integer and outputting it with respect to the input of the phase number j. The converter 37 can be configured by a multiplier, a ROM, or the like. The phase number value indicating the decimal point normalized to 8 bits is supplied to the register 38.
[0031]
Therefore, the register 38 obtains phase information which is a total 16-bit phase angle value W having 8 bits after the decimal point and 8 bits after the decimal point. The signal is sampled and output at the timing of the transmission period signal from the control circuit 19 and supplied to the register 39 and the subtractor 40. The register 39 operates with the timing clock of the transmission cycle signal and outputs a signal delayed by one cycle to the subtractor 40. The subtracter 40 subtracts the phase angle signal of the previous period of the register 39 from the phase angle signal of the register 38, and obtains the frequency count value of the frequency information for each transmission period with the precision below the decimal point. A total of 16 bits of frequency information having an integer part of 8 bits and a decimal part of 8 bits is obtained and output from the frequency phase information generation circuit 16.
[0032]
Next, FIG. 4 shows a specific configuration example of the averaging circuit 15 in FIG. The averaging circuit 15 includes a memory circuit 51, a counting circuit 52, an integrating circuit 53, and a control circuit 54. The memory circuit 51 stores frequency information for each transmission cycle. The control circuit 54 monitors fluctuations in frequency information. When this frequency information is stable, the frequency information up to the previous 128 cycles is read sequentially, the coefficient circuit 52 multiplies the coefficient by 1/128, the integration circuit 53 accumulates the 128-cycle frequency information, Output frequency information averaged over 128 periods. On the other hand, when the frequency information fluctuates, the frequency information up to four cycles before is sequentially read out, multiplied by a coefficient of 1/4 by the coefficient circuit 52, and the frequency information of the four periods is accumulated by the integrating circuit 53. Output frequency information averaged over four periods.
[0033]
Next, a second embodiment of the sampling clock recovery circuit according to the present invention will be described. In the second embodiment, the frequency information uses a count value of a frequency accumulation count from the first transmission cycle to each transmission cycle (in other words, a value indicating a phase). A free counter that operates with a sampling clock corresponds to a counter value sampled for each transmission period, and this frequency information can be regarded as phase information of an integer part. In the first embodiment described above, since the count value for each transmission cycle is transmitted, if there is a transmission path error, the information on the relative phase obtained by integrating the frequency information cannot be correctly reproduced on the receiving side and reproduced. The phase of the TV signal is shifted. Frequency information or phase information is also used as frequency phase information.
[0034]
In the second embodiment, even if there is a transmission error, frequency information indicating the correct phase is transmitted in the transmission cycle in which the frequency information indicating the next phase (frequency phase information) is transmitted. It is possible to maintain the relative phase with periodic accuracy. The configuration of the second embodiment is different in the frequency information generating circuit 4, the averaging circuit 15, and the frequency phase information generating circuit 16 of FIG. 1 showing the first embodiment. In FIG. 2, the frequency information generating circuit 4 of the second embodiment outputs the sampled cumulative counter value obtained at the output of the register 42 as frequency information indicating the phase, multiplexes it, and transmits it to the receiving side. .
[0035]
A specific configuration example of the averaging circuit 15 ′ in the second embodiment is shown in FIG. That is, the register 61, the subtracter 62, the average value circuit 63, the adder 64, the subtracter 65, the nonlinear circuit 66, the adder 67 and the register 68 are included. The phase frequency information is input to the register 61 and the subtracters 62 and 65 of the average value circuit 15 ′. A frequency counter value within one transmission period is obtained at the output of the subtractor 62. This value is input to the average value circuit 63, and an average value obtained by calculating the average value over a long transmission period is output. The average value circuit 63 has the same function as the averaging circuit 15 in FIG. 1 and has the configuration shown in FIG. The adder 64 adds the average value of one transmission cycle and the cumulative count value up to the previous cycle output from the register 68 to obtain a cumulative counter value up to the current transmission cycle. The subtractor 65 obtains a difference value between the accumulated counter value sent from the transmission side and the reproduced accumulated counter value, and inputs the difference value to the non-linear circuit 66. The non-linear circuit 66 has an output of 0 until the magnitude of the miscalculation is 1. On the other hand, in the case of 1 or more, the output characteristic is such that the inclination is initially smaller than 1, for example, 1/4, gradually increased, and coincides with the inclination line after intersecting the straight line with the inclination 1 from the origin. Have The output value of the non-linear circuit 66 is input to the adder 67 and added to the reproduction counter value. When the reception-side cumulative counter value deviates from the transmission-side cumulative counter value, correction is performed so that it gradually approaches the transmission-side cumulative counter value. The corrected counter value becomes an output and is input to the register 68.
[0036]
Next, the frequency phase information generation circuit 16 of the second embodiment outputs the accumulated counter value obtained as the output of the register 38 as it is in FIG. The comparison control circuit 14 performs comparison control of a 16-bit signal using the accumulated counter value without using the transmission period counter value as frequency information. Other functional operations are the same as those in the first embodiment.
[0037]
Next, a third embodiment of the sampling clock recovery circuit according to the present invention will be described. This is a case where the sampling clock is 13.5 MHz, and the configuration diagram thereof is the same as FIG. When the sampling clock FS = 13.5 MHz and the divided transmission clock (reference clock) FL1 = 19.44 MHz, (13.5 / 19.44) × M is close to an integer value when M = 36 (13.5 / 19.44) × 36 = 25. From the relationship between the sampling clock frequency (13.5 MHz) and the divided transmission path clock frequency (19.44 MHz), the value of M at which an integral multiple M of the divided transmission clock cycle is substantially equal to an integral multiple of the sampling clock cycle is calculated. As a result, when M = 36, it becomes 25.0000 times, so M = 36 is set.
[0038]
The M-dividing counter 23 divides the 19.44 MHz divided transmission clock supplied thereto by 36 and outputs a count value n in the range of 0 to 35 to the phase number generation circuit 18. By dividing by 36, the phase information can be determined with an accuracy of 1/36 of one cycle of the sampling clock. As in the case of the first embodiment, as a result of obtaining the relationship between the counter value (sampling number) n and the phase number i, the phase number generation circuit 7
n = MOD (13 × i, 36)
The phase number i corresponding to the input of the counter value n is output. The following characteristics are obtained from the characteristics of n = MOD (13 × i, 36).
Phase number i = 0, 1, 2, 3, 4, 5,..., 34, 35
Counter value n = 0, 13, 26, 3, 17, 30,..., 10, 23
When this is rearranged in the order of n, the relationship becomes i = MOD (25 × n, 36).
Counter value n = 0, 1, 2, 3, 4,..., 34, 35
Phase number i = 0, 25, 14, 3, 28,...
In accordance with the characteristics of this conversion table, the phase number i for the counter value n is output.
[0039]
In the block diagram of the first embodiment, it is necessary to change the M frequency dividing counter 23, the phase number generation circuit 18, the memory circuit 17, and the frequency phase information generation circuit 16 so as to correspond to the above-described characteristics. The frequencies of the sampling clock circuit 5 and the sampling clock recovery circuit 21 are also changed. Other configurations are the same as those in the first embodiment.
[0040]
Next, a fourth embodiment of the sampling clock recovery circuit according to the present invention will be described. The block diagram is the same as that of the third embodiment described above. However, in the third embodiment, when the sampling clock is 13.5 MHz and the divided clock (reference clock) FL1 = 19.44 MHz, the phase identification accuracy of the sampling clock is 1/36 of one cycle (74 ns). Accuracy. This means that the sampling phase quantization accuracy in the time axis direction corresponds to about 2 ns. In the fourth embodiment, the frequency of the divided transmission clock is increased to make the sampling phase highly accurate and reduce the error. The frequency dividing circuit 24 is divided from 8 to 2 and the divided transmission clock (reference clock) is FL1 = 77.76 MHz. The value of 13.5 / 77.76 × M, which is an integer multiple of FS / FL1, is close to the integer value when M = 144. It becomes an integer at 13.5 MHz / 77.76 MHz × 144 = 25. The M divider counter 23 divides the inputted 77.76 MHz divided transmission clock by 144, and inputs the count value n in the range of 0 to 143 to the phase number generation circuit 7. Dividing by 144 means that the accuracy of 1/144 period of the sampling clock, and hence approximately O.D. The phase information can be determined with an accuracy of 5 ns.
[0041]
The phase number generating circuit 7 is between the counter value n and the phase number i.
n = MOD (−23 × i, 144)
The phase number i corresponding to the input of the counter value n is output. The following characteristic is obtained from the characteristic of n = MOD (−23 × i, 144).
Phase number i = 0, 1, 2, 3, 4, 5,..., 142, 143
Counter value n = 0, 121, 98, 75, 52, 29,..., 46, 23
When this is rearranged in the order of n, the relationship becomes i = MOD (25 × n, 144).
Counter value n = 0, 1, 2, 3, 4, 5,..., 142, 143
Phase number i = 0, 25, 50, 75, 100, 125,..., 94, 119
In accordance with the characteristics of this conversion table, the phase number i for the counter value n is output. In the configuration diagram of the third embodiment described above, the frequency dividing circuit 24, the M frequency dividing counter 23, the phase number generating circuit 18, the memory circuit 17, and the frequency phase information generating circuit 16 are changed in accordance with the above characteristics. There is a need. Other configurations are the same as those in the third embodiment.
[0042]
Next, a fifth embodiment of the sampling clock recovery circuit according to the present invention will be described. In the fourth embodiment, the resolution of the phase information can be increased by increasing the reference clock. However, since the circuit for obtaining the phase information requires high-speed processing of 77.76 MHz, a technique for obtaining high accuracy by low-speed processing is used. Show. FIG. 6 is a block diagram on the transmission side of the fifth embodiment. In this embodiment, the frequency of the frequency-divided transmission clock (reference clock) is 19.44 MHz, and the phase of the frequency-divided transmission clock is shifted at a period of 77.76 MHz every time sampling is completed at a period of M = 36, Sampling is performed four times sequentially. As a result, the sampling time is four times longer, but the frequency of the reference clock is 19.44 MHz and the sampling clock sampling point can be obtained with the same phase accuracy as sampling at 77.76 MHz. it can.
[0043]
In the circuit shown in FIG. 6, the same reference numerals are used for the components corresponding to those in FIG. The receiving side of the sampling clock recovery circuit in FIG. 6 includes a D / A converter 11, a decoding circuit 12, a separation circuit 13, a comparison control circuit 14, an averaging circuit 15, a memory circuit 17, a control circuit 19, and a transmission clock recovery circuit. 20. In addition to the sampling clock recovery circuit 21 and the sampling circuit 22, a frequency phase information generation circuit 72, a phase number generation circuit 73, an M frequency division counter 75, and an adaptive frequency division circuit 76 are provided. The adaptive divider circuit 76 generates a 19.44 MHz reference clock. However, a reference clock with a phase delay of 77.76 MHz is generated every fixed period T (period of 36 clocks at 19.44 MHz).
[0044]
Next, FIG. 7 shows a clock waveform diagram. (A), (b), (c) and (d) show a 19.44 MHz clock having four phases which are sequentially shifted in phase. The output clock is a clock obtained by switching these four clocks every period T. Four periods (da), (ab), (bc), and (cd) form one period. The phase delay is one cycle T1 (1 / 77.76 MHz) of the 77.76 MHz clock, and is sequentially delayed from 0 to 3 times the cycle ((a) phase to (d) phase). The rising edge of the clock is delayed by a period T1 for each phase change. When switching from (d) phase to (a) phase, it is advanced by three times the period T1. Therefore, there is an overlapping portion between the last clock of (d) phase and the first clock of (a) phase. Therefore, the output of the final clock of (d) phase is stopped. In the order of the phases (a) to (d), the number of clocks (the number of rising edges) in each T period is 36, 36, 36, and 35, which is 143 in total. The sampling circuit 22 performs sampling at the rising edge of this clock.
[0045]
In the clock diagram, the numbers in parentheses are numbers that are sample points corresponding to the same phase as the count value (0 to 143) when the period of T is sampled with a 77.76 MHz clock. One sample point of 143 is missing, but the phase information can be judged with accuracy of 1/72 at one missing location and the accuracy of 1/144 at the other 142 locations, so the sample at 77.76 MHz. Almost the same accuracy as that obtained. The adaptive frequency dividing circuit 76 outputs a reference clock consisting of a 19.44 MHz clock whose phase is changed every fixed period as shown in FIG. 7 to the sampling circuit 22 and the M frequency dividing counter 75. In addition, (a) to (d) a 2-bit phase display signal k (k = 0 to 3) indicating the delay phase is output to the M frequency dividing counter 75. The M-dividing counter 75 divides the 19.44 MHz reference clock by 36 or 35. When k = 0 to 2, the counter is divided by 36, and when k = 3, the counter is divided by 35. Assuming that the counter value is m, a value obtained by adding the phase display signal k to a value obtained by multiplying the counter value by 4 is set to 4m + k as a count value n. This corresponds to the numerical value in parentheses in FIG. The M frequency dividing counter 75 outputs the obtained count value n (= 4m + k) to the phase number generation circuit 73 and the frequency phase information generation circuit 72.
[0046]
The phase number generation circuit 73 has the conversion characteristic of i = MOD (25 × n, 144) shown in the fourth embodiment, converts the input counter value n into the phase number i according to the conversion characteristic, and outputs it. To do. The frequency phase information generation circuit 72 is configured in the same manner as in FIG. Then, a normalized phase number is obtained from the phase number, a further normalized counter value W is obtained, and a counter value W sampled every transmission cycle is obtained and output to the comparison control circuit 14. As a result, even when sampling is performed at a low frequency of 19.44 MHz, it is possible to obtain a phase pulling accuracy equivalent to that performed by sampling with a high frequency reference clock of 77.76 MHz.
[0047]
Next, a sixth embodiment of the present invention will be described. In the first to fifth embodiments, the divided transmission clock obtained by dividing the transmission clock is used as the reference clock output from the frequency dividing circuit 12. However, as a reference clock for obtaining phase information, it is not always necessary to use a transmission clock generated in the transmission side device. If the transmission system is a synchronous network, phase information is obtained in synchronization with the network clock at the transmission side device and the reception side device even in a system configuration in which transmission data is packetized and transmitted by ATM or the like on the synchronous network. If the reference clock is generated, a synchronized reference clock can be obtained by transmission and reception. The phase information of the sampling clock can be obtained with high accuracy, and the phase of the sampling clock can be synchronized with high accuracy by transmission and reception.
[0048]
A seventh embodiment of the present invention will be described. In order to obtain a phase number indicating the reference point of the rising edge of the sampling clock, the memory circuit 17 has addresses corresponding to M for convenience of explanation, and once stores the sample values, the sample values having consecutive phase numbers are stored. However, the memory circuit 17 may be omitted. FIG. 8 shows a block diagram of the receiving side in the seventh embodiment. D / A converter 11, decoding circuit 12, separation circuit 13, comparison control circuit 14, averaging circuit 15, phase number generation circuit 18, control circuit 19, transmission clock recovery circuit 20, sampling clock recovery circuit 21, sampling The circuit 22 includes an M frequency dividing counter 23, a frequency dividing circuit 24, and a frequency phase information generating circuit 91. That is, compared with the block diagram shown in FIG. 1B, there is no memory circuit 17 and the configuration of the frequency phase information generating circuit 91 is partially changed. FIG. 9 shows a detailed configuration of the normalized phase number generator 300 ′ of the frequency phase information generation circuit 91. The shift register 30, the reference phase number device 32, the subtractor 33, the determination control circuit 101, and the determination circuit 102 are the same as those in FIG. 3.
[0049]
In the first embodiment described above, when the phase number of the counter value n is i, there is a relationship of n = MOD (−19 × i, 167), and the sample value for each counter value n of 19 has a phase number. Adjacent. The determination control circuit 101 stores the last written phase number in the shift register 30 as the final phase number. Next, the phase number i supplied from the phase number generation circuit 18 is compared with the final phase number. When the phase number coincides with the adjacent phase number, the control signal for writing the sample value supplied from the sampling circuit 22 to the shift register 30. And the phase number at that time is set as a new final phase number. The shift register 30 is a 3-bit shift register, and the sample value of the sampling clock is written every time the phase number is decreased by 1 by the write signal. At the output of the shift register 30, three sample values arranged in order from the smallest phase number are obtained. The determination circuit 102 detects the rising point of the sampling clock from the three consecutive sample values. When detected, the detection signal is output to the determination control circuit 101 and the reference phase number unit 32. The reference phase number unit 32 sets and outputs the phase number corresponding to the detection position supplied from the control circuit 19 when a detection signal is received. It takes a worst 19 times the period until the rising edge is detected. Once the reference phase number is detected, the next phase number corresponding to the vicinity of the reference phase number, in this case, a value 6 larger than the reference phase number is set as the final phase number, and detection is started again. When writing to the shift register is performed 6 to 7 times, the phase number becomes close to the reference phase number, the rising edge can be detected quickly, and the reference phase number can be repeatedly detected approximately every cycle.
[0050]
Next, an eighth embodiment of the present invention will be described. The reference clock (divided transmission clock FL1) for sampling the sampling clock FS can be realized in the same manner without any particular problems even when the reference clock is lower. ITU-T standard H.264 color TV signal. 261 / H. The sampling clocks on the transmission side and the reception side are synchronized as applied to the case of encoding with a method such as H.263, transmitting at 6.312 Mbps, and reproducing on the reception side. Therefore, the color burst of the TV signal on the transmission side and the TV signal reproduced on the reception side can be synchronized. FIG. 10 is a block diagram on the receiving side of the eighth embodiment. D / A converter 11, decoding circuit 12, separation circuit 13, comparison control circuit 14, averaging circuit 15, frequency phase information generation circuit 16, phase number generation circuit 18, control circuit 19, transmission clock recovery circuit 20, sampling The clock recovery circuit 21, the sampling circuit 22, and the M frequency division counter 23 are configured. The separation circuit 13 separates the compression-encoded data at a predetermined rate that has been encoded so as to have a data rate assigned for transmission of the video signal, and outputs it to the decoding circuit 12. The decoding circuit 12 is an ITU-T standard H.264 standard. A signal obtained by encoding and compressing a TV signal using the H.263 encoding method is decoded. The transmission clock recovery circuit 20 generates a 6.312 MHz clock and outputs it to the sampling circuit 22, the M frequency dividing counter 23 and the control circuit 19.
[0051]
H. In the method of 261 or 263, the sampling clock is FS = 13.5 MHz. The transmission line is 6.312 MHz, and an integer multiple M of 13.5 MHz / 6.312 MHz = 2.1387832 is searched for a value of M that is as close as possible to the integer value. When M = 36, it becomes 2.1388782 × 36 = 76.9962. The error is 0.0038. Since the accuracy of 1/36 is 0.027, the magnitude of the error 0.0038 with respect to the resolution accuracy of 0.027 is a negligible effect at about 1/7. The M frequency dividing counter 23 is constituted by a 36 frequency dividing counter. The phase number generation circuit 18 has the following conversion characteristics.
[0052]
In this example embodiment, between the counter value n and the phase number i,
n = MOD (−7 × i, 36)
The relationship is established. From this relationship, the following characteristics are obtained.
Phase number i = 0, 1, 2, 3, 4, 5,..., 34, 35
Counter value n = 0, 29, 22, 15, 8, 1,..., 14, 7
When this is rearranged in the order of n, the relationship becomes i = MOD (5 × n, 36).
Counter value n = 0, 1, 2, 3, 4, 5,..., 34, 35
Phase number i = 0, 5, 10, 15, 20, 25,..., 26, 31
The phase number generation circuit 18 outputs the phase number i for the counter value n according to the characteristics of this conversion table. The frequency phase information generation circuit 91 obtains the frequency phase information of the counter value W sampled at regular intervals from the sample value and the phase number i.
[0053]
Next, a ninth embodiment of the present invention will be described. The transmission period for sending the frequency information is obtained by dividing the reference clock, but the transmission period may not be an integral multiple of the reference clock period. Since the reference clock uses the transmission clock, if the phase information in the transmission cycle is known to the phase information at the sampling point of the reference clock in the vicinity, the advance amount of the sampling clock phase for each reference clock, Calculated from the relationship between the reference clock phase and the transmission cycle phase. For example, in the first embodiment, when the reference clock is 19.44 MHz, the phase of the sampling clock that advances by one clock is 0.736532. Therefore, in the period of the transmission line clock of 155.52 MHz, the value of 1/8 is 0.0920665, and the phase number at this time corresponds to 15.375. In other words, in the clock period of 155.52 MHz, the phase is shifted by 15.375 / 167, so that the correction can be made according to the shift between the reference clock and the sampling phase of the predetermined transmission period. For example, if the sampling phase of the phase information is advanced by 3 clocks with a 155.52 MHz clock from the reference clock, the phase number obtained with the reference clock phase is 15.375 × 3 = about 46 If the value is added and corrected, frequency phase information at a phase having no sample point can be obtained.
[0054]
Finally, a tenth embodiment of the present invention will be described. In the MPEG-2 system standardized by ITU-T, a time stamp system is used to send sampling clock information, but this embodiment is an example when time stamp information is received. . The block diagram of the basic configuration is the same as FIG. 1 described above, but the configuration of the averaging circuit 15 is different. The average value circuit 15 of this embodiment determines the time difference and the frame number difference from the previous time stamp information from the time stamp information and the time. Based on this, frequency information is obtained and the frequency information is further averaged to obtain frequency information averaged with high precision after the decimal point. By controlling the frequency of the reproduction sampling clock based on this, a sampling clock having a stable frequency can be reproduced.
[0055]
FIG. 11 is a timing chart showing the relationship between sampling points of the sampling clock and the reference clock. (A) shows a sampling clock, (b) shows a corresponding sample number, (c) shows a phase number, (d) shows a reference clock, and (e) shows a count value n.
[0056]
The configuration and operation of various exemplary embodiments of the image encoding / decoding device according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention, and of course does not limit the present invention. Those skilled in the art will readily understand that various modifications and changes can be made without departing from the scope of the present invention.
[0057]
【The invention's effect】
As is clear from the above, according to the image encoding / decoding device of the present invention, the following remarkable effects can be obtained. First, the phase of the sampling clock can be detected with high accuracy without using an analog circuit. The reason is that, when the sampling clock is sampled with the reference clock (frequency-divided transmission clock), N and M are obtained such that an integer multiple M of the reference clock period is approximately equal to an integer multiple N of the sampling clock period. At this time, the sampling clock is sampled with M reference clocks having different phases. This is because the phase of the sampling clock can be easily detected with high accuracy of 1 / M by rearranging the sampling clock sample values in order of phase and detecting the rising edge of the sampling clock.
[0058]
Second, even when integer count information is sent from the transmitting side, the receiving side can accurately calculate the average count value obtained by averaging the count information and the phase information of the reproduction sampling clock with high accuracy. Since the sampling clock can be generated with high accuracy by comparing the obtained reproduction count information with a comparison error of 0, the SC of the TV signal can be reproduced with high stability and high accuracy.
[Brief description of the drawings]
FIG. 1 shows a block diagram of a first embodiment of a sampling clock recovery circuit according to the present invention, where (A) is a transmission side and (B) is a reception side.
FIG. 2 is a block diagram of a detailed configuration example of a frequency phase information generation circuit shown in FIG.
FIG. 3 is a detailed block diagram of the frequency phase information generating circuit shown in FIG.
4 is a block diagram illustrating a specific configuration example of an averaging circuit illustrated in FIG.
FIG. 5 is a block diagram of another specific configuration example of the averaging circuit.
FIG. 6 is a block diagram on the receiving side in the third embodiment of the image coding / decoding apparatus according to the present invention;
7 is a timing chart of a reference clock generated by the adaptive frequency dividing circuit shown in FIG. 6. FIG.
FIG. 8 is a block diagram showing a configuration of a receiving side in a seventh embodiment of an image encoding / decoding apparatus according to the present invention.
9 is a detailed block diagram of a main part of the frequency phase information generating circuit shown in FIG.
FIG. 10 is a block diagram showing a configuration of a receiving side in an eighth embodiment of an image encoding / recovering clock recovery circuit according to the present invention.
FIG. 11 is a diagram illustrating a relationship between a sampling clock and a reference clock at a front office.
FIGS. 12A and 12B are block diagrams showing a configuration of a conventional sampling clock recovery circuit, where FIG. 12A is a transmission side and FIG. 12B is a reception side.
13 is a detailed block diagram of the phase angle generation circuit of FIG.
FIG. 14 is a detailed block diagram of the phase comparison circuit of FIG.
[Explanation of symbols]
1 A / D converter
2 Encoding circuit
3 Multiplex circuit
4, 16, 91 Frequency information generation circuit
5 Sampling clock circuit
6, 19 Control circuit
7 Transmission clock circuit
8, 24 divider circuit
11 D / A converter
12 Decoding circuit
13 Separation circuit
14 Comparison control circuit
15, 15 'averaging circuit
17 Memory circuit
18 Phase number generation circuit
20 Transmission clock recovery circuit
21 Sampling clock recovery circuit
22 Sampling circuit
23 M frequency division counter

Claims (8)

Image coding / decoding, in which an image signal such as a color television signal is sampled and encoded and transmitted on the transmission side, and encoded data is decoded from the received signal on the reception side, and the signal is reproduced with the reproduced sampling clock In the conversion device,
An averaging circuit that averages the frequency information on the transmission side to obtain highly accurate frequency information, a transmission clock recovery circuit that recovers a transmission clock from the received signal, and frequency information and reception side frequency information from the averaging circuit A comparison control circuit for obtaining a control signal by comparing the sampling clock, a sampling clock recovery circuit for recovering a sampling clock based on the control signal, and sampling the sampling clock with a reference clock from the transmission clock recovery circuit A sampling circuit for obtaining a sampling value of the sampling clock, an M dividing counter for dividing the reference clock by a predetermined dividing ratio M, and a period of the sampling clock from the dividing counter value of the M dividing counter. The phase number generation circuit that generates the phase numbers so that the phases are arranged in order, and the frequency information of the sampling clock when sampling by the sampling circuit, the comparison And a frequency phase information generating circuit for inputting the control circuit, the decoded signal with the sampling clock picture coding and decoding apparatus characterized by converting D / A. 2. The image encoding / decoding apparatus according to claim 1, wherein the reference clock is obtained by a frequency dividing circuit that divides the output from the transmission clock recovery circuit. Receiving phase information instead of the frequency information, obtaining phase information averaged with high accuracy, obtaining phase information with high accuracy from the reproduced sampling clock, and reproducing the sampling clock with high frequency accuracy The image coding / decoding apparatus according to claim 1 or 2, characterized in that: As the reference clock, a clock obtained by switching clocks having the same frequency and different phases in a predetermined order every predetermined period is used to obtain substantially the same function as when a high-frequency reference clock is used. The image encoding / decoding device according to claim 1, 2, or 3. The image encoding / decoding apparatus according to claim 1, further comprising a memory circuit that stores a sample value of the sampling clock in a phase number. 2. The sampling clock on the transmitting side is selected to be four times the subcarrier frequency, 19.44 MHz for the reference clock frequency, and 167 for the frequency division ratio M of the M frequency division counter. The image encoding / decoding device described. 2. The image code according to claim 1, wherein the sampling clock frequency on the transmission side is 13.5 MHz, the reference clock frequency is 19.44 MHz, and the division ratio M of the M division counter is 36. Encoding / decoding device. Receiving time stamp information instead of the frequency information, obtaining frequency information or phase information averaged with high accuracy from the time stamp information and obtaining frequency information or phase information with high accuracy from the reproduction sampling clock, 2. The image encoding / decoding apparatus according to claim 1, wherein a sampling clock with high frequency accuracy is regenerated based on the phase information.

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