JP2006254041A - Clock recovery information forming circuit and clock recovery circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock recovery information generating circuit and a clock recovery circuit wherein clock information transmitted from a transmission side can be made small in volume while making the total cumulative value of video image clocks serve as a control input. <P>SOLUTION: A clock recovery information generating circuit on a transmission side is equipped with a counter 1 which forms reference term pulses from the transmission clocks, a counter 2 which counts the video image clocks from zero to a natural number C-1 or I-1, a register 3 which holds values of the counter 2 for each reference term pulse, a selector 4 which switches the value of C or I through control pulses, a clearing unit 5 which returns the reading of the counter 2 to zero comparing its count values, and a pulse generator 6 which outputs control pulses. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is used in, for example, an HDTV system or an SDTV system, samples a video signal and converts it into a digital signal, and is a transmission path asynchronous with a video signal sampling clock (hereinafter referred to as “video clock”). In a transmission apparatus that transmits video on a synchronous transmission line using a synchronous clock (hereinafter referred to as “transmission clock”), clock transmission that generates clock recovery information used when the video clock is recovered on the reception side on the transmission side The present invention relates to an information generation circuit and a clock recovery circuit that recovers a video clock using a PLL on the receiving side.

  In such a transmission apparatus, it is necessary to reproduce the video clock on the receiving side. On the receiving side, the video data is clock-converted through a video buffer memory such as FIFO, but if the video clock input to the transmitting side is not completely reproduced, the video buffer overflows or underflows. Flow and video distortion occurs.

  Therefore, it is necessary to transmit information for reproducing the video clock (hereinafter referred to as “clock reproduction information”) to the receiving side together with the video, but the clock reproduction information should be made as small as possible due to the bit rate limitation of the transmission path. Is preferred. On the other hand, since the jitter in the output video signal needs to satisfy the standard, the accuracy of the clock reproduction information needs to be equal to or higher than a predetermined value.

  The clock recovery information is generally the number of clocks in the PLL sampling period (hereinafter referred to as “reference period”), that is, the value of a counter that operates continuously during that period. If the reference period is short, the value is small, but the number of times of sending increases. If the reference period is long, the number of times of sending decreases, but the value increases.

  The PLL inputs the clock recovery information as a control target value (hereinafter referred to as “control input”), and uses the difference from the feedback amount relative thereto as a control deviation (hereinafter referred to as “control amount”). The output is changed so that becomes 0, and a reproduced video clock is obtained as an output that matches the input target value.

In a PLL that digitally handles an input amount when a video clock is reproduced on the receiving side, usually only the number of clocks (hereinafter referred to as “delta value”) existing in one reference period is used as a control input (for example, a patent). Reference 1). When the delta value is used as clock recovery information, when the number of bits to be transmitted is reduced, the upper bit does not change because the frequency deviation of the input video clock is limited. For example, the lower number of the original delta value The delta value can be recovered by transmitting only the bits and adding the known higher bits on the receiving side.
Japanese Patent No. 2594666

  However, if the control input of the PLL when reproducing the video clock on the receiving side is a delta value, if the response of the PLL is delayed in order to suppress the low-frequency jitter of the reproduced clock, the data occupancy of the video buffer There is a disadvantage that the video is disturbed due to overflow or underflow of the video buffer over a long period of time. In order to solve this inconvenience, the PLL control input is not the delta value, but the total number of clocks after the video starts to flow (hereinafter referred to as “total accumulated value”), but is almost constant for each reference period. Unlike the delta value indicating the value in the range, the total cumulative value increases with time, so that it is difficult to handle as a clock reproduction information or to configure a PLL circuit.

  An object of the present invention is to provide a clock recovery information generation circuit and a clock recovery circuit capable of reducing the clock recovery information transmitted from the transmission side while using the total accumulated value of the video clock as the control input of the PLL.

A clock recovery information generation circuit according to the present invention includes:
When a video signal is sampled and converted to a digital signal, and the video is transmitted via a synchronous transmission line using a synchronous clock that is asynchronous with the video signal sampling clock, the video clock is generated using a PLL on the receiving side. A clock reproduction information generation circuit for generating clock reproduction information used for reproduction,
The first natural number is subtracted at least once for each reference period obtained by counting the synchronous clock from the cumulative value of the sampling clock of the video signal from the video transmission start time, and the subtracted residual is calculated as a second value. Means to output the remainder when dividing by the natural number of
The remainder is generated as clock reproduction information.

A clock recovery circuit according to the present invention includes:
When a video signal is sampled and converted into a digital signal, and the video is transmitted through a synchronous transmission line using a synchronous clock that is asynchronous with the video signal sampling clock, the video clock is generated using a PLL on the receiving side. A clock recovery circuit for reproducing,
The first natural number is subtracted at least once for each reference period obtained by counting the synchronous clock from the accumulated value of the sampling clock of the video signal from the video transmission start time, and the subtracted residual is set to the second Means for receiving a remainder when dividing by a natural number of
Means for calculating a cumulative value of the frequency deviation of the sampling clock from the remainder;
The cumulative value of the frequency deviation is used as the control amount of the PLL.

  The video data is continuous data and is not interrupted. When all the time from when video is input to the transmission side to when it is output from the reception side is viewed as one large video buffer, once video starts to flow, writing and reading are always performed in the video buffer.

  The data occupancy amount of the video buffer at a certain time is obtained by subtracting the “total read amount” from the “total write amount” until the time when the video starts to flow. Therefore, the control for preventing the buffer from overflowing or underflowing (that is, the image is not disturbed) is to make the value obtained by subtracting the “total read amount” from the “total write amount” constant.

  This can be seen as a PLL that reproduces the video clock, by subtracting the “total number of PLL oscillator clocks since the start of video” from the “total number of video clocks since the start of video”. The difference between the input and the feedback amount). For this reason, the PLL that reproduces the video clock preferably uses the total accumulated value of the video clock as a control input.

  In the circuit described in Patent Document 1, since the delta value is used as the clock reproduction information, the total accumulated value cannot be transmitted. In addition, when trying to calculate the total accumulated value by accumulating the delta value on the receiving side, if transmission of the clock recovery information fails even once, the total accumulated value cannot be accurately reproduced thereafter, and transmission failure occurs. Errors are accumulated as they occur.

  When the PLL control input is set to the total cumulative value of the clock, for example, the PCR in MPEG is the total cumulative value of the clock itself, but the data amount is relatively large (42 bits), and the counter goes round and returns to zero. Sometimes further processing is required.

  Furthermore, if the frequency of the clock locked by the PLL is increased, the number of digits of the counter that counts the total accumulated value of the clock and the operation speed are increased, so that the number of bits of the clock reproduction information further increases and it is difficult to realize the counter circuit. become.

  According to the present invention, the frequency obtained from the remainder when subtracted by the first natural number and divided by the second natural number is equivalent to the accumulated value of the sampling clock of the video signal from the video transmission start time. Since the accumulated value of the deviation is used as the control input of the PLL, even if the response of the PLL is delayed in order to suppress the low-frequency jitter of the reproduced clock, the data occupancy of the video buffer does not fluctuate. It is possible to realize video clock reproduction without disturbing the video.

  Further, instead of directly transmitting the total accumulated value, the clock reproduction information is configured with a small number of bits by using the remainder when the total accumulated value is subtracted by the first natural number and divided by the second natural number. Transmission overhead can be reduced.

  Even when the clock recovery information is not transmitted, the number of bits to be handled is small because the accumulated value of the frequency deviation is used for the control input of the PLL. A PLL that synchronizes frequency clocks can be realized.

  Further, two kinds of natural numbers, ie, a first natural number and a second natural number different from the first natural number, are set in accordance with a frequency deviation between a video signal sampling clock (video clock) and a transmission path synchronization clock (transmission clock). Setting, it is possible to reduce the amount of change in the value of the information for reproducing the video clock (clock recovery information). As a result, even if there is a lack of information due to a transmission error, it is missing on the receiving side. Since the estimated value can be easily estimated, the influence of a transmission error on the PLL circuit is reduced.

  In order to obtain the cumulative value of the frequency deviation, it is necessary to separately transmit carry / carry information described later, in addition to the clock reproduction information. Preferably, the receiving side is provided with means for determining carry and carry from the remainder, so that it is not necessary to transmit carry and carry information. Also, comprising means for counting the number of times the carry and carry are accumulated, by calculating separately the carry / carry component and the transmitted remainder component when calculating the cumulative value of the frequency deviation, Since a counter having a large number of bits is not required, a circuit can be configured with a small number of bits, and the circuit scale can be reduced even when clock recovery information is not transmitted.

Embodiments of a clock recovery information generation circuit and a clock recovery circuit according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration of a transmission side of a transmission apparatus including a clock reproduction information generation circuit. This transmission apparatus is used in, for example, an HDTV system or an SDTV system, and includes a clock recovery circuit according to the present invention on the receiving side, as will be described later.

  The transmission side includes counters 1 and 2, a register 3, a selector 4, a clear unit 5, a pulse generator 6, a multiplexer 7, and an output terminal 8. The counter 1 operates in accordance with the transmission clock and generates pulses at equal intervals (hereinafter referred to as “reference period pulses”) once every reference period. The counter 2 operates continuously by the video clock and counts the number determined by the selector 4.

  The register 3 holds the value of the counter 2 by the reference period pulse generated by the counter 1, and the value held by the register 3 becomes clock reproduction information. The selector 4 selects one of the first natural number (C) and the second natural number (I), and the clear unit 5 outputs the counter 2 equal to I or C. When this happens, the value of counter 2 is reset to zero. That is, the possible value of the counter 2 can be switched to I or C. The pulse generator 6 inputs the reference period pulse generated by the counter 1, and controls the same number of times as the number of times that the value to be switched by the selector 4 is C until the next reference period pulse arrives. A pulse is generated and applied to the selector 4. The multiplexer 7 multiplexes clock reproduction information and video data. The output terminal 8 outputs the multiplexed data to the transmission line.

  The selector 4 normally selects the counter 2 to count from 0 to I-1, but the counter 2 changes from 0 to C− only once every time one control pulse from the pulse generator 6 is applied. Switch to count to 1.

  FIG. 2 is a diagram showing a configuration on the receiving side of a transmission apparatus including a clock recovery circuit according to the present invention. On the receiving side, the counters 11 and 12, the register 13, the selector 14, the clear unit 15, the pulse generator 16, the input terminal 17, the separator 18, the register 19, the initial register 20, and the carry Carry-out determining units 21 and 22, an up / down counter 23, a multiplier 24, an adder 25, a PLL integrator 26, a D / A converter 27, and a voltage controlled crystal oscillator (VCOX) 28 Yeah.

  A signal from the transmission line is input to the input terminal 17. The separator 18 performs the reverse operation of the multiplexer 7 in FIG. 1, and separates video data and clock reproduction information. The register 19 temporarily stores the transmitted clock recovery information. The initial value register 20 holds clock reproduction information used for the control of the PLL first.

  The counter 11 has the same configuration as the counter 1 of FIG. 1 and generates a receiving-side reference period pulse. The counter 12 has the same configuration as the counter 2 of FIG. 1, is provided with the clock reproduction information held in the initial value register 20 as an initial value, and operates according to the output clock of the VCXO 28. The register 13 has the same configuration as the register 3 in FIG. 1 and holds the value of the counter 12 by the reference period pulse generated by the counter 11. The selector 14, the clear unit 15 and the pulse generator 16 have the same configuration and perform the same operations as the selector 4, the clear unit 5 and the pulse generator 6 of FIG.

  A carry / carry determination unit 21 determines whether a carry or a carry has occurred from the value of the register 19, and a carry / carry determination unit 22 carries a carry or a carry from the value of the register 13. Whether or not has occurred is determined. The carry / carry will be described in detail later. The up / down counter 23 increases / decreases the value in accordance with the number of carry or carry of the carry / carry determination units 21 and 22.

  The multiplier 24 multiplies the output from the up / down counter 23 by I (the reason will be described later). The adder 25 adds the difference value between the value of the register 19 and the value of the register 13 to the output of the multiplier 24. The output of the adder 25 becomes an input of the PLL integrator 26, and after passing through the PLL integrator 26, the VCXO 28 is controlled by the voltage analogized by the D / A converter 27.

  FIG. 3 is a diagram showing the configuration of the pulse generator 6 of FIG. 1 and the pulse generator 16 of FIG. This has an input terminal 31, counters 32 and 33, a comparator 34, and an output terminal 35.

  The counter 32 is a counter that starts counting by a reference period pulse input from the input terminal 31 and repeatedly outputs a pulse at a necessary interval because the counter 2 in FIG. 1 or the counter 12 in FIG. 2 finishes counting C. is there. The counter 33 is a counter that counts the number of control pulses. The comparator 34 compares the count value of the counter 33 with the number of times the counter 2 or the counter 12 counts C, and outputs a reset pulse to the counter 32 and the counter 33 when they match. By the reset pulse, the counter 32 and the counter 33 return the count value to 0 and stop the operation. The output terminal 35 outputs the number of output pulses of the counter 32 equal to the number of times the counter 2 or the counter 12 counts C as control pulses.

  Here, first, the operation in the case of I = C will be described. The selector 4 in FIG. 1 or the selector 14 in FIG. 2 does not change regardless of which is selected when I = C.

  As an example, the operation when the video clock is 270 MHz, which is common in SDTV systems, and the reference period generated by the transmission clock is 1/8 kHz = 125 μs will be described. First, the generation of clock reproduction information on the transmission side will be described. The counter 2 always counts up at 270 MHz, and I (= C) values can be taken. The value of the counter 2 at the timing indicated by the reference period pulse, that is, the clock reproduction information, represents the accumulation of the 1/8 kHz reference period by the number of 270 MHz clocks, and the remainder when it is divided by I (referred to as r). Can be seen. That is, if 125 μs of 1/8 kHz period is counted at 270 MHz, it becomes 270000000 ÷ 8000 = 33750 clocks. If I = 10, 33750 ÷ 10 = 3375 is divisible and the remainder r = 0. . The clock reproduction information is updated and transmitted every reference period. In this case, the value of the clock reproduction information (remainder r) is 0 every time, no matter how long the video transmission period is.

  In general, in a steady state, there is a frequency deviation (slight deviation) in one or both of the transmission clocks that make up the 270 MHz of the video clock and the reference period 1/8 kHz, so the remainder r is not 0, With I-1 as the maximum value, it increases or decreases at a constant speed (change amount) each time the value is updated.

This is expressed by a sequence of total clock accumulated values sampled every reference time. The first clock recovery information is r1, the second clock recovery information is r2, and {r1, r2,. . . } If the transmission clock is used as a reference now, when the video clock 270 MHz is synchronized with the transmission clock, the total accumulated value shown for each reference period is:
{270000000 ÷ 8000 = 33750, 270000000 ÷ 8000 × 2 = 33750 × 2,270000000 ÷ 8000 × 3 = 33750 × 3,. . . }
= {33750, 67500, 101250} (1)
On the other hand, the remainder r calculated for each reference period is
{33750 ÷ 10 = 3375 residue 0, 33750 × 2 ÷ 10 = 3375 × 2 residue 0, 33750 × 3 ÷ 10 = 3375 × 3 residue 0,. . . }
= {0,0,0, ...} (2)
It becomes.

If the transmission clock and the video clock are not synchronized, and the video clock has a deviation of 28008000 Hz, the total accumulated value shown for each reference period is
{2708000/8000 = 33751,2700008000 / 8000 × 2 = 33751 × 2,2700008000 ÷ 8000 × 3 = 33751 × 3,. . . }
= {33751, 67502, 101253} (3)
And the remainder r calculated for each reference period is
{33751 ÷ 10 = 3375 remainder 1,33751 × 2 ÷ 10 = 3375 × 2 remainder 2,33751 × 3 ÷ 10 = 3375 × 3 remainder 3,. . . }
= {1, 2, 3, ...} (4)
It becomes. That is, the amount of change in the total accumulated value caused by the frequency deviation of the video clock is obtained by subtracting the number sequence (1) from the number sequence (3). Match)

  The PLL is “the amount of control obtained by subtracting the total accumulated value of the oscillator (VCXO28) clock possessed by the PLL from the total accumulated value of the video clock”, but the result of the sequence (1) included in both of them is Since the minute becomes 0 by taking the difference, “the increase in the clock number caused by the frequency deviation of the oscillator clock from the total accumulated value of the increase (or decrease) in the clock number caused by the frequency deviation of the video clock ( Or the amount obtained by subtracting the total accumulated value of the decrease) is the control amount. That is, only the remainder r needs to be transmitted as a total accumulated value.

  However, the value obtained by subtracting the number sequence (1) from the number sequence (3) continues to increase as {..., 8, 9, 10, 11,. .., 8, 9, 0, 1,...} And returns to 0 at the maximum value I-1. This indicates that a carry of an I-digit has occurred (if a decimal number, the tens place is incremented by 1. Hereinafter, it will be referred to as “carry”. Similarly, a carry may be a decimal number. This means that the tens place has decreased by one.) Therefore, to obtain the total accumulated value, it is necessary to transmit carry and carry information or to detect carry or carry on the receiving side.

Detection of carry or carry on the receiving side can be performed as follows.
When the difference between the previous value of the remainder r and the current value (hereinafter referred to as “amount of change once”) is relatively small, if the amount of change of the residue r changes rapidly more than a certain amount, a carry / carry It can be determined that a fall has occurred. In other words, if the value obtained by subtracting the present remainder r from the previous remainder r is equal to or greater than the carry / decay threshold (S is a natural number smaller than I), a carry is generated. Yes, if the value obtained by subtracting the previous remainder r from the current remainder r is equal to or greater than the threshold value S, a carry is generated. Such a carry / carry determination is performed by the carry / carry determinators 21 and 22 on the receiving side.

  In addition, since the total accumulated value is handled, it is necessary to accumulate the number of times the carry or carry has occurred. If this accumulated value is multiplied by I and only the latest remainder r is added, the “total accumulated value of the frequency deviation of the video clock” (or “total accumulated value of the frequency deviation of the oscillator clock”) can be calculated.

  The remainder r has a measurement error of ± 1, but the number of occurrences of carry / carry does not include an error unless the carry / carry judgment is wrong, and the total accumulated value of the obtained frequency deviation is always It contains only ± 1 error.

  FIG. 4 is a diagram showing a configuration of the carry / carry-down determiners 21 and 22 of FIG. The carry / carry determination units 21 and 22 include registers 41 and 42, a subtracter 43, comparators 44, 45 and 46, and AND gates 47 and 48.

  The register 41 is a register that holds the current clock recovery information, and the register 42 is a register that holds the previous clock recovery information. The subtracter 43 subtracts the smaller one of the values of the register 41 and the register 42 from the larger value. When the subtraction result is larger than the threshold value S, the comparator 44 indicates that a carry or a carry has occurred. It can be determined that a carry has occurred if the previous large value has rapidly decreased beyond the threshold S, and a carry has been determined if the previous small value has rapidly increased beyond the threshold S. it can.

Assuming that the deviation of the video clock is doubled to 2700016000 Hz with respect to the sequence (3), the total accumulated value shown for each reference period is
{27016000 ÷ 8000 = 33752, 27006000 ÷ 8000 × 3 = 33752 × 2,27000000 ÷ 8000 × 3 = 33752 × 3,. . . }
= {33752, 67504, 101256} (5)
And the remainder r calculated for each reference period is
{33752 ÷ 10 = 3375 remainder 2,33752 × 2 ÷ 10 = 3375 × 2 remainder 4,33752 × 3 ÷ 10 = 3375 × 3 remainder 6,. . . }
= {2, 4, 6, ...} ... (6)
Thus, the rate at which the remainder r increases with respect to the sequence (4) is increased. (In other words, the amount of change at a time becomes larger.)

  Further, when the video clock with the increased deviation becomes 200400000 Hz, the remainder r changes as {0, 5, 0, 5,...}, And it is not possible to distinguish whether a carry or a carry has occurred. It becomes possible. Therefore, it is necessary to select the value of I so that the amount of change in the remainder r determined by the maximum deviation between the video clock and the transmission clock is less than I / 2, and the threshold value S is I / 2. .

  When I = 10, the maximum natural number less than I / 2 is 4, but since the remainder r has a measurement error of ± 1, the registers 41 and 42 are allowed to have an error of ± 1, respectively. Since the change amount of the remainder r at one time is 2, and (33750 + 2) × 8000 = 2700016000 Hz, if the deviation is within about ± 59 ppm, the carry / carry-down determination can be correctly determined. Since the maximum value of the remainder r at this time is I-1 = 9, the number of bits necessary for transmission as clock recovery information is 4 bits.

  In the relationship where the video clock is 270 MHz and the reference period created by the transmission clock is 1/8 kHz as in the above example, the video clock and the reference period are divisible as shown in the sequence (2). When the relationship between the clock and the reference period is not divisible, the remainder that is not divisible is added as a single change amount of the clock reproduction information, and the maximum change amount of the single change of the residue r is considered in the same way as when the frequency deviation increases. Select I so that the value is less than I / 2. That is, depending on the relationship between the frequency of the video clock and the reference period, and the combination of the frequency deviation between the video clock and the transmission clock, the amount of change in the remainder r increases, so it is necessary to increase the number of bits of the clock reproduction information.

  Next, the operation on the receiving side when I = C will be described. Also for the clock of the VCXO 28 of the PLL, the total accumulated value of the frequency deviation is obtained using the remainder r as in the transmission side. The counter 11 generates a reference period pulse on the receiving side from the same transmission clock as that on the transmitting side.

  The counter 12 counts the remainder r and holds the value in the register 13 by the reference period pulse. At this time, the initial value at the start of the operation of the counter 12 is given by the register 20 holding the value of the first clock recovery information used when starting the control of the PLL among the clock recovery information sent, and received. When the reference period pulse generated by the counter 11 on the side arrives, the counting starts. Thus, the value of the counter 12 when the reference period pulse generated by the counter 11 on the reception side arrives is the value of the counter 2 when the reference period pulse generated by the counter 1 on the transmission side arrives (used) Matches the first clock recovery information). Since the initial control amount of the PLL is always 0, the PLL can start operation regardless of the value of the first clock recovery information to be used.

  In addition, the phase of the two reference period pulses on the transmitting side and the receiving side are not necessarily the same, but the delay from the reference period pulse on the transmitting side to the reference period pulse on the receiving side is regarded as a fixed delay in the transmission of the clock recovery information. Can do. The value of the first clock reproduction information to be used and the initial value of the counter 12 do not change depending on the amount of delay, so the control amount of the PLL does not change. The point in time at which the PLL can start operation simply by the reference period pulse on the receiving side is delayed within one reference period, that is, within one sampling of the PLL, and does not constitute a problem in the operation of the PLL.

  The PLL uses the difference between the “total accumulated frequency deviation of the video clock” and the “total accumulated frequency deviation of the oscillator clock” based on the transmission clock as the control amount. The “cumulative value” is the remainder r (that is, one digit in decimal number) indicated by the register 13 and the number of carry / carry-down accumulations by the carry / carry determination unit 21 (that is, more than ten in decimal number). The total accumulated value of the oscillator clock frequency deviation is also divided into two elements in the same way, so "the cumulative number of carry and carry of the video clock frequency deviation" May be calculated first by subtracting “the accumulated number of carry / carry of frequency deviation of the oscillator clock”, and this is performed by the up / down counter 23. That is, the accumulated difference value of the number of carry / carry times is held in the up / down counter 23 from the result of carry / carry-down judgment of the clock reproduction information and the result of carry / carry-down judgment by the value of the register 13. The increment method of the up / down counter 23 is shown in Table 1 below.

  The “transmitted clock recovery information” in Table 1 is the value of the register 19, and the “carry”, “carry”, and “no change” are the results of the carry / carry determination unit 21. It is. Similarly, the “remainder r in the VCXO clock” is the value of the register 13, and the “carry”, “carry” and “no change” are the results of the carry / carry determination unit 22. is there.

  In the steady state in which the PLL is locked, the up / down counter 23 always takes a value near 0 and handles the total accumulated value. However, in reality, there is no counter with a large number of bits for counting the accumulated value. do not need. Since the value of the up / down counter 23 represents the I-th or higher place of the I-adic number, it is multiplied by I and added by the adder 25 together with the remainder r indicated by the register 19 subtracted from the remainder r indicated by the register 13.

  Next, the case where I ≠ C will be described. As described above, when the video clock is 270,8000 Hz, the change of the remainder r when I = C = 10 is as {1, 2, 3,...} As shown in the sequence (4). However, here, C = 11, I = 10, 0 to C-1 is counted only once for 33751 clocks in one reference period, and all other times are counted up to I-1. In this case, the value r of the register 3 (FIG. 1) can be regarded as a remainder when C is subtracted for each reference period from the number of clocks representing the accumulation of the reference period and divided by I. Therefore, since (33751-11) ÷ 10 = 3374 remainder 0 is divisible, the value r of the register 3 can always be 0. Similarly, when the video clock is 2,700,000 Hz, the change of the remainder r when I = C = 10 is {2, 4, 6,...}, But C = 11, I = 10, Assuming that 0 to C-1 is counted only twice with respect to the 33752 clock of one reference period and all other times are counted to I-1, (33752-11 × 2) ÷ 10 = 3373 remainder 0 Therefore, the value r of the register 3 can always be 0. Alternatively, even if 0 to C-1 is counted only once in one reference period with C = 12, (33752-12) / 10 = 3374 remainder 0 and the same result is obtained. In other words, the clock reproduction information generation circuit is a circuit for subtracting the natural number C at least once for each reference period from the clock base representing the accumulation of the reference period, and obtaining a remainder when the natural number C is divided by the natural number I. The number of times the value and C are subtracted and the value of the natural number I are set so that the amount of change of the obtained remainder r once is minimized. The clock recovery information is transmitted as a remainder when dividing by I.

  In FIG. 5, the fact that the counter 2 (FIG. 1) has counted all the way from 0 to the maximum possible value is represented by a box, and the counted number of clocks is displayed in the box. For example, the fact that the counter 2 (FIG. 1) has counted from 0 to 15 (when I = 16 or C = 16) is represented by a square represented by 16.

  As shown in FIG. 5, when the position of the reference period pulse is used as a reference, the value of the register 3 (FIG. 1) is the position of the box with respect to the reference when only the box crossing the reference is focused. When the moves to the next box, a carry or a carry occurs. Here, assuming that the box straddling the reference is necessarily an I box, the clock reproduction information x for obtaining the total cumulative number of clocks generated due to the frequency deviation is a value obtained by holding the count value in the I box with a reference period pulse. can do. The reason is that the increase / decrease in the value of x indicates the number of clocks exceeding the reference, and the accumulation of the number of clocks exceeding the reference is nothing but the total accumulated value of the number of clocks generated by the frequency deviation. x represents the first place when the total accumulated value of clocks exceeding the reference is expressed in I-base. That is, if the position of the I box relative to the reference period pulse (clock recovery information) and the cumulative number of I boxes exceeding the reference (the cumulative number of carry / carry down) are known, the total number of clocks generated by the frequency deviation is determined. Cumulative value can be calculated.

  Therefore, the size of the C box inserted at a position that does not cross the reference (the value of C) or the number of C boxes that are inserted in one reference period does not shift the position of the I box that crosses the reference as much as possible. (That is, the amount of change in x once is small).

  In order to ensure that the box that actually crosses the reference is always an I box, the C box is inserted at a position that does not become the box that crosses the reference, and all other boxes may be I boxes. The number and timing of C box insertions are controlled by the pulse generator 6. If a reference period pulse is input to the pulse generator 6 and a constant delay pulse synchronized with the reference period pulse is output, C It is easy to prevent the box from becoming a box straddling the standard.

  As in the above example, the operation when the video clock is 270 MHz and the reference period generated by the transmission clock is 1/8 kHz = 125 μs will be described. First, the generation of the clock recovery information on the transmission side will be described. The pulse generator 6 inputs the reference period pulse output from the counter 1 and then the position (C box) until the reference period pulse arrives. At a position that does not cross the reference period pulse), a predetermined number of pulses for inserting the C box are generated. The selector 4 selects C every time the pulse of the pulse generator arrives, and the counter 2 counts from 0 to C-1. Since the position at which the C box is inserted is a position that does not straddle the reference period pulse, the box at the position that straddles the reference period pulse is the I box.

  If the value of C is set to I ± α, the relationship between the frequency of the video clock and the transmission clock in one reference period and the increase (or decrease) that occurs according to each frequency deviation can be set in units of 1. Therefore, the amount of change in the clock reproduction information at a time can be suppressed to 0.5 or less. Select the relationship between the frequency of the video clock and the transmission clock, the value of C and I according to each frequency deviation, and the number of insertions of C, and set the amount of change in the clock recovery information to be 0.5 or less Therefore, it is not necessary to increase the number of bits of the clock recovery information, and even if the clock recovery information cannot be received due to a transmission error, it is easy to estimate the value (the change amount of the value once is limited to 0 or 1). Guessing will not cause a large error).

It will be described that the amount of change in the clock reproduction information can be suppressed to 0.5 or less by setting the C value and the number of insertions of the C box.
Now, assuming that the video clock has a deviation of 2,800,000 Hz with reference to the transmission clock, the total accumulated value shown for each reference period is from the above sequence (3):
{33751, 67502, 101253, ...}
When I = C = 10, the remainder r calculated for each reference period is obtained from the above-described sequence (4).
{1, 2, 3, ...}
However, assuming that C = 11, I = 10 and the number of C boxes to be inserted is 1, the clock reproduction information is obtained by dividing one subtracted 11 by 10 for each reference period. Because it is a surplus of time,
{(33751-11) ÷ 10 = 3374 remainder 0, (33751-11) × 2 ÷ 10 = 3374 × 2 remainder 0, (33751-11) × 3 ÷ 3 = 3374 × 3 remainder 0,.
= {0,0,0, ...} (10)
It becomes.

Similarly, assuming that the deviation of the video clock doubles to 27006,000 Hz, the total accumulated value shown for each reference period is from the sequence (5).
{33752, 67504, 101256, ...}
When I = C = 10, the remainder r calculated for each reference period is obtained from the sequence (6).
{2, 4, 6, ...}
However, if C = 12, I = 10,
{(33752-12) ÷ 10 = 3374 residue 0, (33752-12) × 2 ÷ 10 = 3374 × 2 residue 0, (33752-12) × 3 ÷ 3 = 3374 × 3 residue 0,.
= {0,0,0, ...} (11)
It becomes. Or, if C = 11, I = 10 and the number of C boxes to be inserted is 2,
{(337752- (11 × 2)) ÷ 10 = 3373 remainder 0, (337752- (11 × 2)) × 2 ÷ 10 = 3373 × 2 remainder 0, (33752- (11-2)) × 3 ÷ 10 = 3373 × 3 remainder 0,.
= {0,0,0, ...} (12)
It becomes.

That is, the clock reproduction information becomes 0 if the adjustment amount by C is increased by 1 every time the deviation of the video clock increases by 8000 Hz (frequency of the reference period) with reference to the transmission clock. From this, when the deviation of the video clock is 4000 Hz, 12000 Hz,... Which is the middle of 8000 Hz, 16000 Hz,. For example, if the video clock is 27003,000 Hz, the total accumulated value shown for each reference period is
{270001000/8000 = 33751.5, 27003000/8000 × 2 = 33751.5 × 2, 200123000/8000 × 3 = 33751.5 × 3,.
= {33751.5, 67503, 101254.5, ...} (13)
And C = 11, I = 10, and the number of C boxes to be inserted is 1, the clock recovery information calculated for each reference period is
{(33751.5-11) ÷ 10 = 3374 remainder 0.5, (33751.5-11) × 2 ÷ 10 = 3374 × 2 remainder 1, (33751.5-11) × 3 ÷ 10 = 3374 × 3 Remainder 1.5, ...}
= {0.5, 1, 1.5, ...} (14)
Although the amount of change at one time is 0.5, since the clock reproduction information is a natural number indicated by the counter 2, in reality, = {0, 1, 1, 2, 2,. 54)
As in the case where the value increases once every two times, the amount of change at one time is the maximum.

  Therefore, if the value of C and the number of boxes of C are set appropriately, even if the clock recovery information is not transmitted due to a transmission error, it is assumed that the clock recovery information that could not be received on the receiving side is the same value as the previous time. Even so, the maximum error is 1, which does not have a great influence on the PLL operation.

  In addition, if normal clock recovery information is obtained after a transmission error, the total accumulated value is calculated from the latest clock recovery information. Not included. The determination of carry or carry is continued when the clock recovery information cannot be obtained due to a transmission error, and the value of the clock recovery information immediately before the transmission error occurs and the value of the clock recovery information immediately after the transmission error ends. As long as the difference does not reach the carry / decay threshold value S, no error occurs.

  Conversely, whether or not the value of C and the number of boxes of C are appropriate can be determined by looking at the amount of change in the output clock recovery information at one time. In other words, it is not appropriate if the amount of change in the output clock recovery information once exceeds 0.5. Observe the amount of change in the clock reproduction information at one time. If the amount of change is not appropriate, change the number to be increased or decreased by ± 1 depending on the value of C and the number of boxes in C, and the amount of change at a time becomes 0.5 or less. Repeat until you can make the appropriate settings.

  In the case where the reference period generated by the video clock and the transmission clock is not divisible, the non-divisible remainder is superimposed as a single change in the clock reproduction information. By selecting the value of C and the number of boxes of C, even if the relationship between the video clock and the reference period is not divisible, it is possible to reduce the amount of change in the clock reproduction information at one time.

  As an operational setting method, I is assumed to be a fixed value, the value of C and the number of C boxes to be inserted are set according to the frequency deviation, and this is notified in advance to the receiving side before the PLL operation. . At this time, for example, if the I box is 10 and the C box is 17 (5 bits are required), it is necessary to increase the number of bits of the counter, and the operation speed of the counter circuit decreases, so that the number of bits does not increase. It is appropriate to adjust the value of C to I + 1 or I-1, and then adjust the number of C boxes.

Next, the operation of the receiving clock recovery circuit in FIG. 2 will be described.
The clock recovery information transmitted from the transmission side represents the number of clocks exceeding the reference in FIG. 5 in the box I, and the carry / carry determination unit 21 performs carry / carry determination in the I box. If this is done, the “total cumulative value of the increase in the number of clocks caused by the frequency deviation” can be obtained, and this can be directly used as the control input of the PLL.

  The receiving side also has the same clock reproduction information generation circuit as the transmitting side using the output of the VCOX 28 as a clock, and the value of C set on the transmitting side and the number of C boxes (the number of times the counter 12 counts from 0 to C-1). ), The remainder is obtained in the same manner as on the transmission side, but the other carry / carry-down decision units 21, 22, up / down counter 23, multiplier 24, adder 25, D / A converter 27 and VCXO 28 are The circuit configuration and operation are the same as in the case of I = C. The initial register 20 provides clock recovery information used for control first to the counter 12 as an initial value.

Also on the reception side, the same value as that on the transmission side is subtracted from the total accumulated value of the oscillator clocks depending on the value of C set by the clock recovery information generation circuit on the transmission side and the number of C boxes. Now, if the total accumulated value of the video clock is X, the total accumulated value of the oscillator clock is Y, and the total amount to be subtracted by the value of C and the number of boxes of C set by the clock reproduction information generation circuit on the transmission side is A, the PLL Control amount, that is, the difference value between the total accumulated value of the video clock and the total accumulated value of the oscillator clock is
XY
Even if X-A is used instead of X and YA is used instead of Y,
(X−A) − (Y−A) = X−Y−A + A = (X 1 Y)
Therefore, the control amount of the PLL is the same. In other words, the value of C and the number of C boxes are independent of the control amount of the PLL and are independent.

  As described above, the clock reproduction information is a remainder when X-A is divided by I, and can be regarded as one place when X-A is represented by an I-ary number. The fall judging devices 21 and 22 judge carry or carry in I, and the judgment threshold value S is I / 2. Since the up / down counter 23 accumulates the number of carry / carry times in I of the carry / carry determination units 21 and 22, the multiplier 24 multiplies I, and the adder 25 uses X−A. A difference value from YA, that is, XY is obtained.

  In this embodiment, by selecting I and C (I is an arbitrary natural number, and C and I are arbitrary natural numbers different from each other) according to the frequency deviation between the video clock and the transmission clock, With respect to the frequency deviation between the video clock and the transmission clock, the range that can be covered by the clock recovery information can be set appropriately. Further, by appropriately setting I and C according to the frequency deviation between the video clock and the transmission clock, the amount of change in the clock reproduction information is reduced, and the clock reproduction information to be transmitted does not change greatly. This means that even if missing, the value can be easily estimated, and as a result, determination of carry or carry is not made erroneously, so that a cumulative value of error ± 1 can be obtained even after missing.

The present invention is not limited to the above-described embodiment, and many changes and modifications can be made.
For example, in the above embodiment, for simplicity of explanation, the operation when the video clock is 270 MHz, which is common in SDTV systems, and the reference period generated by the transmission clock is 1/8 kHz = 125 μs. However, other video clocks and reference periods such as those employed in HDTV systems can also be used.

It is a figure which shows the structure of the transmission side of the transmission apparatus containing the clock reproduction | regeneration information generation circuit by this invention. It is a figure which shows the structure of the receiving side of the transmission apparatus containing the clock reproduction circuit by this invention. It is a figure which shows the structure of a pulse generator. It is a figure which shows the structure of a carry / carry-down determination device. It is a figure for demonstrating operation | movement of the clock reproduction information generation circuit by this invention, and a clock reproduction circuit.

Explanation of symbols

1, 2, 11, 12, 32, 33 Counter 3, 13, 19, 41, 42 Register 4, 14 Selector 5, 15 Clear unit 6, 16 Pulse generator 7 Multiplexer 8 Output terminal 17, 31 Input terminal 18 Separator 20 Initial value register 21, 22 Carry / carry determination unit 23 Up / down counter 24 Multiplier 25 Adder 26 PLL integrator 27 D / A converter 28 Voltage control crystal oscillator 35 Output terminal 43 Subtractor 34, 44, 45, 46 Comparator 47, 48 AND gate

Claims (3)

When a video signal is sampled and converted into a digital signal, and the video is transmitted through a synchronous transmission line using a synchronous clock that is asynchronous with the video signal sampling clock, the video clock is generated using a PLL on the receiving side. A clock reproduction information generation circuit for generating clock reproduction information used for reproduction,
The first natural number is subtracted at least once for each reference period obtained by counting the synchronous clock from the accumulated value of the sampling clock of the video signal from the video transmission start time, and the subtracted residue is used as the second natural number. With a means to output the remainder when dividing by
A clock reproduction information generation circuit generating the remainder as clock reproduction information. When a video signal is sampled and converted into a digital signal, and the video is transmitted through a synchronous transmission line using a synchronous clock that is asynchronous with the video signal sampling clock, the video clock is generated using a PLL on the receiving side. A clock recovery circuit for reproducing,
The first natural number is subtracted at least once for each reference period obtained by counting the synchronous clock from the accumulated value of the sampling clock of the video signal from the video transmission start time, and the subtracted residue is used as the second natural number. Means for receiving the remainder when divided by
Means for calculating a cumulative value of the frequency deviation of the sampling clock from the remainder;
A clock recovery circuit using the accumulated value of the frequency deviation as a control amount of the PLL. Means for calculating the cumulative value of the frequency deviation comprises means for determining a carry and a carry from the remainder; and a means for counting the cumulative number of carry and carry.
3. The clock recovery circuit according to claim 2, wherein a cumulative value of the frequency deviation is calculated using the accumulated number of carry and carry and the remainder.

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