JP5105072B2 - Timing information collection device - Google Patents

Description

  The present invention relates to a timing information collection device, and more particularly to a timing information collection device that collects timing information such as transmission channel jitter information, frequency offset information, and frequency drift information of data received under an environment where transmission channel jitter is large. Transmission path jitter refers to data phase fluctuation, frequency offset refers to frequency deviation of transmitted / received data, and frequency drift refers to temporal fluctuation in frequency offset.

  When communication is performed through packet switching or an ATM network, fluctuations in data delay time (transmission path jitter) that occur in the transmission path become a problem. In order to regenerate the received clock while suppressing such transmission line jitter, the receiver has a buffer and controls the regenerative clock so that the amount of data staying there is always constant. (ITU-T Recommendation I.363.1) is known.

  In order to improve the tracking characteristics of transmission line jitter in the “active block regeneration method”, the reference time is generated from the clock count value (independent time function count value) of the independent oscillator provided on the receiving side, resulting in transmission line jitter. A “clock recovery method and reception clock generator” that controls a voltage-controlled crystal oscillator that predicts the amount of delay variation is known (for example, see Patent Document 1).

  This technique first increases the write clock count value (transmitted write count value) to the buffer and the read clock count value (received from the buffer) for each fixed frame arrival unit assuming that no transmission line jitter has occurred. The phase comparison function is predicted and calculated from the read count value) and the increment of the independent time function count value for each fixed frame arrival unit. Then, this phase comparison function and a value weighted to a value proportional to a deviation from the set value of the data retention amount of the buffer (a value that does not cause the buffer to fail even when synchronization between transmission and reception clocks is not established). By adding, a control signal for the voltage controlled crystal oscillator is generated.

JP-A-2002-368726 (page 3 to page 5, FIG. 1)

  However, the above-described prior art aims at reproducing a clock with improved transmission line jitter tracking characteristics. However, in order to reproduce the transmitted data in detail on the receiving side, it is not sufficient. Jitter information, frequency offset information, and frequency drift information are essential.

  In particular, the timing information included in the data received through an environment with a large transmission line jitter has a problem that the jitter component is mixed as a frequency offset component or drift component, which increases the error in frequency offset sampling and frequency drift sampling. There is.

  Therefore, an object of the present invention is to provide a timing information collection device that improves the characteristics and performance of timing information collection even in an environment where transmission channel jitter is large.

  The present invention employs the following technical configuration in order to achieve the above object. That is, in the present invention, first, a control is provided in which a receiving side has a free-running oscillator that oscillates independently, a reference time is generated from the count value of the free-running oscillator, and a delay fluctuation amount caused by transmission line jitter is predicted. To synchronize the reception clock.

  According to the first aspect of the present invention, a reproduction synchronization clock generation function is provided that receives clock information on the transmission side supplied from the transmission path and reproduces a clock whose phase synchronization is established on the reception side. This function is realized by a normal method using a voltage controlled crystal oscillator (VCXO), but the control amount generation method has the feature of the present invention. That is, when calculating the control amount of VCXO, in order to predict the amount of delay variation caused by transmission line jitter, the result of phase comparison with a free-running oscillator that is not affected by transmission line jitter is added to the feedback amount. .

  However, when phase synchronization is fully performed on the free-running oscillator, the asynchronous component with the clock information on the transmission side is accumulated as a stationary phase error, so this stationary phase error information is also added to the feedback amount to establish phase synchronization. . In other words, by calculating the control amount by appropriately weighting the phase comparison result with the free-running oscillator and the stationary phase error between the clock information on the transmission side, it has resistance to the influence of transmission line jitter, and It is possible to realize a reproduction synchronous clock generation function in which the clock information on the transmission side is synchronized.

  After that, by sampling the count value of the number of clocks of the recovered clock output signal obtained and the count value of the number of clocks of the free-running oscillator, the transmission line jitter is instantly sampled when the timing information reaches the receiver. It has a function to measure information, frequency offset information, and frequency drift information.

With regard to jitter information, the previous value difference value of the clock information on the transmission side does not include transmission line jitter, but the count value of the number of clocks of the regenerative synchronization clock output signal is sampled as soon as the timing information reaches the receiver. The previous value difference value of the obtained value indicates a value including the transmission line jitter, and the difference between the two values indicates the transmission line jitter, so that jitter information is collected.

Here, when the regenerative synchronization clock output signal is not synchronized with the clock that generates timing information sent from the transmission side, the asynchronous clock deviation is superimposed on the previous value difference value of both, and the transmission line jitter is zero In addition, it has an offset value, which causes erroneous collection as jitter information. Therefore, even when the transmission path jitter is large, it is impossible to collect an accurate amount of jitter unless the reproduction synchronization clock signal is reliably generated on the receiving side and the jitter information is not collected. In the present invention, the reproduction synchronous clock signal is reproduced even in an environment where the transmission line jitter is large.

  For frequency offset information, the update value of the clock information on the transmission side is compared with the update value of the count value of the oscillation clock matched with the clock frequency of the transmission side that is the reference for sampling at regular intervals. Measurement is possible. However, when comparing the update increase values of both, if one of them does not include transmission line jitter and one of them is measured under conditions including transmission line jitter, the number of clocks due to the influence of transmission line jitter should be the number of clocks that should be attributed to the frequency offset. Even when the frequency offset is zero, that is, when the clock is synchronized, the jitter information is erroneously collected as a frequency offset.

  Therefore, simply compare the difference value before multiple samples (for example, N) of timing information including the clock information on the transmitting side with the clock sample value used as a reference for instantaneous collection when the information arrives. It is impossible to measure an accurate frequency offset only by doing. In the present invention, in order to prevent the influence of transmission line jitter when measuring frequency offset, the count value of the reproduction synchronization clock counter that reproduces the reproduction synchronization clock signal even in an environment where the transmission line jitter is large, and the sampling reference The frequency offset is measured by sampling and comparing the count value of the clock at the same instant.

  As for the frequency drift information, the fluctuation value of the frequency offset information is measured every predetermined time. For this reason, when frequency offset information is measured, if it is affected by transmission line jitter, the effect is spread as erroneous sampling of frequency drift information. In the present invention, as described above, the frequency offset information is measured so as not to be affected by the transmission line jitter, and the frequency drift information is measured based on the frequency offset result.

  The second aspect of the present invention calculates the counter count value at the timing designated by the simulation operation without mounting the VCXO when it is not always necessary to generate the reproduction synchronization clock on the receiving side. It has a realization function. In other words, a VCXO control voltage is generated by the D / A converter, and a reproduction synchronous clock count value simulation calculation is performed by latching the count value of the VCXO clock number at a specified timing. As a result, the measurement function of jitter information, frequency offset information, and frequency drift information is realized without mounting the D / A converter and VCXO, as in the first mode.

  In short, the timing information collection device of the present invention is a timing information collection device that collects timing information of input data received from a transmission line, and includes a clock output unit (reproduction clock output unit D in FIG. 1 and pseudo reproduction clock output in FIG. 2). Unit E), a free-running clock generation unit (B in FIGS. 1 and 2), a timing information output unit (A in FIGS. 1 and 2), and a frequency control unit (C in FIGS. 1 and 2). Features.

  The clock output unit generates a latch count value related to a reproduction clock or a pseudo reproduction clock that is synchronized with a transmission source clock whose information is embedded in the input data as a timing information data value.

  The free-running clock generation unit (B in FIGS. 1 and 2) oscillates a free-running clock that is asynchronous with the transmission source clock, performs frequency correction on the free-running clock, and conforms to the nominal frequency of the transmission source clock. The free running clock count value and the previous value difference value of the free running clock count value are calculated.

  The timing information output unit (A in FIGS. 1 and 2) detects and extracts timing information data values from input data, and uses the timing information data value, the latch count value, and the free-running clock count value as a jitter information value, The offset information value and the drift information value are collected, and a detection timing signal indicating the detection instant of the timing information data value is output.

Frequency control unit (Figure 1, C-2), the phase comparison between the latch count value from the timing information data value and a clock output section, and the prefix differential of the prefix differential and latch the count value of the free-running clock output value And a frequency control signal is calculated by a value obtained by multiplying each comparison result by a weighting factor and supplied to the clock output unit.

  The first effect of the present invention is that the clock of the free-running oscillator is counted and the phase comparison is performed in consideration of the influence of the transmission line jitter. Therefore, in the clock synchronous reproduction of the data received through the environment where the transmission line jitter is large. This means that phase synchronization can be established.

  The second effect of the present invention is that transmission path jitter information, frequency offset information, and frequency drift included in data received through an environment having a large transmission path jitter can be accurately collected. This is because jitter information is collected by performing clock synchronous reproduction with phase synchronization established, and the transmission line jitter component is not mixed as a frequency offset component.

  The third effect of the present invention is that it is possible to calculate and control the necessary timing amount by simulation, so that jitter information, frequency offset information, and frequency can be obtained without mounting a D / A converter and VCXO. This means that the drift information measurement function can be realized by reducing the size and weight, reducing the power consumption, increasing the integration, and simplifying the circuit and device configuration.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of configuration]
FIG. 1 is a block diagram showing a timing information collection device according to Embodiment 1 of the present invention. This timing information collection device outputs a reproduction synchronization clock u for input data a input via a transmission path of a packet switching network or an ATM network, and also includes a jitter information value p, an offset information value q, and drift information. Collect the value r. For this purpose, the timing information collecting apparatus is composed of a timing information output unit A, a free-running clock generation unit B, a frequency control unit C, and a reproduction clock output unit D. In the input data a, the clock information of the transmission source (count value corresponding to the nominal frequency) is embedded.

  The timing information output unit A receives the input data a from the transmission line, detects and extracts a timing information data value (sender clock information) c, and outputs a jitter information value p, an offset information value q, and a drift information value. r (collectively referred to as timing information) is collected. The jitter information value p is a value representing the phase fluctuation while the input data a propagates through the transmission line, the offset information value q is the frequency deviation value of the input data a, and the drift information value r is the input data a. It is a frequency fluctuation value. In the offset information value q and the drift information value r, a jitter component is probably mixed as an offset component and a drift component, respectively. The collected timing information is output to the user's terminal (not shown) and provided for the reproduction of the input data a.

  The free-running clock generator B oscillates a free-running clock that is asynchronous with the clock of the timing information data value c, corrects the frequency of the free-running clock, and matches the nominal frequency held by the timing information data value c. The free-running clock count value h and the previous value difference value k of the free-running clock count value are calculated. Frequency correction refers to conversion of a count value corresponding to a free-running clock into a count value corresponding to a transmission source clock. The free-running clock count value h is supplied to the timing information output unit A, the frequency control unit C, and the reproduction clock output unit D.

The frequency control unit C compares the phase between the timing information data value c and the latch count value i from the recovered clock output unit D, and the previous value difference k, the latch count value i, and the previous value difference of the free-running clock count value h. And the frequency control signal s is calculated using a value obtained by multiplying each comparison result by a weighting factor. The latch count value i is a value obtained by latching the reproduction synchronization clock count value v corresponding to the reproduction synchronization clock u at the change point of the free-running clock count value h.

  The reproduction clock output unit D generates a reproduction synchronization clock u based on the frequency control signal s and supplies the latch count value i to the timing information output unit A and the frequency control unit C. Timing information is collected by the timing information output unit A based on the timing information data value c, the free-running clock count value h, and the latch count value i.

  Details of the timing information output unit A, the free-running clock generation unit B, the frequency control unit C, and the reproduction clock output unit D will be described below.

  The timing information output unit A includes a data receiving unit 1, a timing information detection / extraction unit 2, and a timing information collection unit 14.

  The data receiving unit 1 receives input data a supplied from a transmission path (not shown) and outputs it as received data b. Here, the input data a refers to packet data such as MPEG data or IP packets, in which clock information of the data transmission source is embedded.

  The timing information detection and extraction unit 2 receives the reception data b supplied from the data reception unit 1 and detects and extracts the timing information data value c. Then, the timing information data value c is supplied to the timing information collection unit 14 and the frequency control unit C, and the detection timing signal f indicating the detection instant of the timing information data value c is supplied to the free-running clock generation unit B.

  The timing information collection unit 14 calculates the timing information data value c, the latch counter value i from the reproduction clock output unit D, and the free-running clock count value h from the free-running clock generation unit B to calculate the jitter information value p and the offset information. The value q and the drift information value r are collected. Details of the timing information collection unit 14 will be described later.

  The free-running clock generation unit B includes a free-running oscillator 3, an oscillator counter 4, a reception timing stamping latch unit 5, a nominal frequency adaptation unit 6, and a previous value difference calculation unit 7.

  The free-running oscillator 3 generates a free-running clock d that is not synchronized with the transmission source clock corresponding to the timing information data value c and supplies it to the oscillator counter 4. The oscillator counter 4 counts the free-running clock d generated by the free-running oscillator 3 to generate a free-running clock count value e and supplies it to the reception timing stamping latch unit 5. The reception timing stamping latch unit 5 latches and holds the free-running clock count value e at the moment when the detection timing signal f is received from the timing information detection / extraction unit 2, and generates a latch free-running clock count value g to be nominal. This is supplied to the frequency adaptation unit 6.

  The nominal frequency adaptation unit 6 performs frequency correction by multiplying the latch free-running clock count value g by the ratio of the nominal frequency corresponding to the timing information data value c to the nominal oscillation frequency of the oscillator counter 4 to extract extracted timing information data. The free-running clock count value h adapted to the nominal frequency held by the value c is calculated and supplied to the timing information collection unit 14, the frequency control unit C, and the reproduction clock output unit D, respectively. The free-running clock count value h is updated every time the detection timing signal f is generated.

  The previous value difference calculation unit 7 generates a previous value difference value k of the free-running clock count value h and supplies it to the phase comparator 12 every time the free-running clock count value h is updated.

  The frequency control unit C includes a phase comparator 8, a weight coefficient adjustment unit 9, a frequency control information calculation unit 10, a previous value difference calculation unit 11, a phase comparator 12, and a weight coefficient adjustment unit 13.

  The phase comparator 8 performs a phase comparison operation between the timing information data value c and the latch count value i, generates a timing phase comparison signal l, and then supplies the timing phase comparison signal l to the weight coefficient adjustment unit 9. The weighting coefficient adjustment unit 9 performs weighting calculation on the timing phase comparison signal l to generate the weighting timing phase comparison signal m, and then supplies the weighting timing phase comparison signal m to the frequency control information calculation unit 10.

  The previous value difference calculation unit 11 generates a previous value difference value j of the latch count value i every time the latch count value i is updated, and then supplies it to the phase comparator 12. The phase comparator 12 performs a phase comparison operation between the previous value difference value k and the previous value difference value j, generates a latch count phase comparison signal n, and then supplies it to the coefficient adjustment unit 13. The weighting coefficient adjusting unit 13 performs weighting on the latch count phase comparison signal n to generate a weighted latch count phase comparison signal o, and then supplies the weighted latch count phase comparison signal o to the frequency control information calculation unit 10.

  Here, since the timing information data value c does not include the influence of the transmission line jitter, the latch count value i includes the influence of the transmission line jitter. Therefore, the frequency control signal s is obtained by using only the timing phase comparison signal l. Therefore, PLL control cannot be performed properly in an environment where the transmission path jitter is large. On the other hand, the frequency control signal s is generated only by the latch count phase comparison signal n in which the influence of the transmission line jitter is offset by the difference between the previous value difference value k and the previous value difference value j, both of which include the influence of the transmission line jitter. Then, the original purpose that the VCXO 17 synchronizes with the free-running oscillator 3 and regenerates the synchronous clock with the clock information of the timing information value c cannot be achieved. Therefore, the weight coefficient adjusting units 9 and 13 are balanced by weighting the timing phase comparison signal l and the latch count phase comparison signal n, respectively.

  The frequency control information calculation unit 10 generates the frequency control signal s based on the weight timing phase comparison signal m generated by the weight coefficient adjustment unit 9 and the weight latch count phase comparison signal o generated by the weight coefficient adjustment unit 13. , And supplied to the reproduction clock output unit D. Details of the frequency control information calculation unit 10 will be described later.

  The reproduction clock output unit D includes a change point detection unit 15, a D / A converter 16, a VCXO 17, an oscillator counter 18, and a latch function unit 19.

  The change point detection unit 15 updates the free-running clock count value h, generates a latch timing signal w that tells the instantaneous timing at which the value has changed, and then supplies it to the latch function unit 19. The latch function unit 19 is the final stage of the feedback path.

  The D / A converter 16 converts the digital value of the frequency control signal s into an analog value to generate an analog frequency control signal t, and then supplies the analog frequency control signal t to the voltage controlled crystal oscillator (VCXO) 17. The VCXO 17 controls the oscillation frequency by the analog frequency control signal t to generate the reproduction synchronization output clock u, and then supplies it to the oscillator counter 18 for output to the outside.

The oscillator counter 18 counts the number of reproduction synchronization clocks u to generate a reproduction synchronization clock count value v, and then supplies it to the latch function unit 19. The latch function unit 19 holds and outputs the instantaneous value to which the latch timing signal w is input with respect to the reproduction synchronization clock count value v to generate the latch count value i, and then the timing information collection unit 14 and the phase comparator 8. And the previous value difference calculation unit 11.

FIG. 3 shows details of the timing information collection unit 14. The timing information collecting unit 14 includes a previous value difference calculating unit 31, a previous value difference calculating unit 32, a subtracting unit 33, an N difference calculating unit 34, an N difference calculating unit 35, a subtracting unit 36, and an M number. The difference calculation unit 37 is configured.

The previous value difference calculation unit 31 calculates the previous value difference signal (d_c) by performing the previous value difference calculation of the timing information data value c, and then supplies it to the subtraction unit 33 as a subtraction value. The previous value difference calculation unit 32 calculates the previous value difference signal (d_i) by performing the previous value difference calculation of the latch count value i, and then the subtraction unit 33.
Is supplied as a subtracted value. Subtraction unit 33, from the prefix differential signal (d_i), prefix differential signal (d_c)
Is calculated and a jitter information value p indicating the jitter amount is calculated, and then output to the outside as a sampling result.

The previous difference signal (d_c) does not include the effect of transmission line jitter, whereas the previous difference signal (d_c)
Since i) includes the effect of transmission line jitter, the difference between the two indicates the transmission line jitter. When the transmission / reception clock is asynchronous, the asynchronous clock deviation becomes the previous value difference signal (d_i), and the jitter information value p even if the transmission line jitter is zero. In order to avoid this, the previous value difference signal (d_i) is calculated using the latch count value i related to the reproduction synchronization clock.

  The N difference calculation unit 34 calculates a difference signal (dn_i) by performing a difference calculation between the latch count value i and N (positive integer) samples before, and supplies the difference signal (dn_i) as a subtraction value. The N difference calculation unit 35 calculates a difference signal (dn_k) by performing a difference calculation with respect to N samples before the free-running clock count value h, and supplies the difference signal (dn_k) as a subtracted value. The subtraction unit 36 subtracts the difference signal (dn_i) from the difference signal (dn_k) to calculate an offset information value q indicating the frequency offset amount, and then outputs the result as a collection result to the outside.

  Although it is possible to calculate the offset information value q based on the timing information data value c and the free-running clock count value h, the timing information data value c does not include the influence of transmission line jitter. Since the free-running clock count value h is latched by the detection timing signal f, it includes the influence of transmission line jitter. Therefore, the number of clocks due to the effect of transmission line jitter is superimposed on the difference in the number of clocks that should be caused by the frequency offset, and even if the frequency offset is zero, i.e., when it is synchronized, the jitter information is Mistaken as a frequency offset. In order to avoid this, a latch count value i including the influence of transmission line jitter is used.

  The M (positive integer) difference calculation unit 37 calculates a drift information value r indicating the frequency drift amount by performing a difference calculation with respect to the offset information value q before M samples, and then outputs the drift information value r to the outside as a sampling result. Since the drift information value r is calculated using the offset information value q excluding the influence of the transmission path jitter as described above, it is not affected by the transmission path jitter.

  FIG. 4 shows details of the frequency control information calculation unit 10. The frequency control information calculation unit 10 includes an adder 41, a digital filter calculation unit 42, and a limiter 43.

  The adder 41 performs an addition operation of the weight timing phase comparison signal m from the weight coefficient adjustment unit 9 and the weight latch count phase comparison signal o from the weight coefficient adjustment unit 13 to thereby add the phase comparison signal (m_o). Is supplied to the digital filter operation unit 42.

The digital filter calculation unit 42 generates a control signal s0 by performing digital filter calculation processing on the added phase comparison signal (m_o), and then supplies the control signal s0 to the limiter 43. The limiter 43 limits the control signal s0 to a range of [(−LIMIT) ≦ s0 ≦ (LIMIT-1)] including both boundary values by using a given LIMIT value 44. Is output to the D / A converter 16.
[Description of operation]
Next, the operation of the timing information collecting apparatus configured as described above will be described. When the power is turned on, the free-running oscillator 3 generates a free-running clock d having a nominal frequency f_osc [Hz], and the oscillator counter 4 counts the free-running clock d and outputs a free-running clock count value e. . When the data reception unit 1 receives the input data a, the reception data b is output, and the timing information detection and extraction unit 2 extracts the clock information (count value corresponding to the nominal frequency) of the transmission source from the reception data b, and the timing information data Output as value c.

  In order to simplify the description, if only the first three data of the timing information data value c are described and are sequentially c1, c2, and c3 in time series, the timing information detection / extraction unit 2 has c1 , C2, c3 extraction instantaneous detection timing signals f1, f2, f3 are output. The reception timing stamping latch unit 5 latches the values of the free-running clock count value g with the detection timing signals f1, f2, and f3, and the respective values are g1, g2, and g3.

  The nominal frequency adaptation unit 6 multiplies g1, g2, and g3 by a nominal frequency ratio [f_secd / f_osc] to calculate free-running clock count values h1, h2, and h3. For example, when the nominal frequency f_secd held by the timing information data value c is 27 MHz and the nominal frequency f_osc held by the free-running clock d generated by the free-running oscillator 3 is 162 MHz, the coefficient is multiplied by 1/6. Therefore, if a plurality of coefficients are multiplied, a general-purpose configuration equivalent to the case of having a plurality of free-running oscillators 3 can be realized by a single free-running oscillator 3. When the free-running clock count value h is updated to h1, h2, and h3, the change point detection unit 15 generates a latch timing signal w that tells the instantaneous timing at which the value has changed, and supplies it to the reproduction clock output unit D.

Timing information data values c1, c2, and c3, previous value difference values k1, k2, and k3, and latch count values i1, i2, and i3 fed back from the reproduction clock output unit D are input to the frequency control unit C. . The phase comparator 8 obtains timing phase comparison signals l1 and l2 by the calculation shown in the equation (1).

l1 = (c2-c1)-(i2-i1), l2 = (c3-c2)-(i3-i2) (1)
The weighting factor adjusting unit 9 generates a weighting timing phase comparison signal m by multiplying the timing phase comparison signal l by an appropriate weighting factor α1, and then supplies the weighting timing phase comparison signal m to the frequency control information calculation unit 10.

  On the other hand, the previous value difference calculation unit 7 generates the previous value difference values k1 and k2 and supplies them to the phase comparator 12 every time the free-running clock count value h is updated to h1, h2, and h3. Further, the previous value difference calculation unit 11 generates the previous value difference values j1 and j2 every time the latch count value i is updated to i1, i2, and i3, and then supplies them to the phase comparator 12.

  The phase comparator 12 performs a phase comparison operation between the previous value difference value k and the previous value difference value j, generates a latch count phase comparison signal n, and then supplies it to the coefficient adjustment unit 13. Since the phase comparison between the previous value difference value k and the previous value difference value j can be equated with the phase comparison between the free-running clock count value h and the latch count value i, the latch count phase comparison signal n is expressed by equation (2). It can be calculated by calculation.

n1 = (h2-h1)-(i2-i1), n2 = (h3-h2)-(i3-i2) ... (2)
The weighting factor adjusting unit 13 multiplies the latch count phase comparison signal n by an appropriate weighting factor α2 to generate a weighting latch count phase comparison signal o, and then supplies it to the frequency control information calculation unit 10.

  In the present invention, the weighting factor adjusting unit 9 and the weighting factor adjusting unit 13 respectively apply appropriate weighting to the timing phase comparison signal l and the latch counter phase comparison signal n to generate a control amount of the VCXO 17, thereby generating transmission line jitter. Even in a large environment, the received clock can be recovered by PLL control.

  The frequency control information calculation unit 10 inputs the weighted timing phase comparison signal m and the weighted latch count phase comparison signal o to the adder 41 (see FIG. 4), and the added phase comparison signal (m_o) as shown in Expression (3). calculate.

m_o = m + o = (α1 × l) + (α2 × n) (3)
Here, the coefficient values α1, α2 (α1 + α2 = 1) are set by the weighting coefficient adjusting unit 9 and the weighting coefficient adjusting unit 13, respectively. Appropriate coefficient values α1 and α2 can be controlled by the transmission path jitter amount and the transmission interval time of the timing information data value c.

  As an example, when the transmission channel jitter amount is ± 1.5 [msec] and the transmission interval time of the timing information data value c is 100 [msec], α1 = 1/2048 and α2 = 2047/2048 can be posted.

  The digital filter operation unit 42 performs digital signal processing on the time series data of the addition phase comparison signal (m_o) to generate a control signal s0. That is, every time the timing information detection and extraction unit 2 extracts the timing information data value c, the addition phase comparison signal (m_o) is accumulated, and the accumulated addition value sum and the addition phase comparison signal (m_o) at that time are obtained. Find the control signal s0. The addition phase comparison signal (m_o) can be a positive / negative value, and thus the cumulative addition value sum can also be a positive / negative value. In accordance with the positive and negative values, the value of the control signal s0 increases and thereby negative feedback is applied to the voltage controlled crystal oscillator (VCXO) 17, and the frequency of the reproduction synchronization clock u can be controlled.

  This calculation can be realized with arbitrary digital filter characteristics by a program calculation such as DSP or CPU. FIG. 5 is a flowchart showing an example of the program calculation. Assuming that (m_o), coeff, cont, and sum are variables and abs (m_o) is the absolute value of (m_o), the contents of the calculation performed here are as follows.

if (abs (m_o)> = 6), coeff = 512
if (abs (m_o) <6), coeff = 256
if (abs (m_o) <5), coeff = 128
if (abs (m_o) <4), coeff = 64
if (abs (m_o) <3), coeff = 32
if (abs (m_o) <2), coeff = 16
if (abs (m_o) <1), coeff = 8
if (sum> 0), cont = cont + coeff * (m_o) -16
if (sum <0), cont = cont + coeff * (m_o) +16
if (sum = 0), cont = cont + coeff * (m_o)
so = cont
In FIG. 5, first, initial values of variables sum and cont are set to 0 (step S1 in FIG. 5). When the addition phase comparison signal (m_o) is input from the adder 41 (step S2), it is added to the coefficient (cumulative addition value) sum (step S3). Next, the absolute value of the addition phase comparison signal (m_o) is converted into an integer, and the upper limit is limited by, for example, 6 (step S4).

  The coefficient coeff is calculated by performing a power-of-2 operation using the value obtained by adding 3 to abs (m_o) thus obtained as an exponent (step S5). The reason why the power-of-two operation is performed is to reduce the convergence time of the control rather than linearly changing the coefficient coeff. Finally, a coefficient (control amount) cont is calculated from the sign of the cumulative addition value sum obtained in step S3 and the coefficient coeff (step S6).

  With respect to the control amount so obtained as described above, the limiter 43 limits the value to a value within the allowable range (a range of [(-LIMIT) ≦ so ≦ (LIMIT-1)] including both boundary values). The frequency control signal s is calculated.

  In the first embodiment, the reproduction clock output unit D is provided with the VCXO 17, and the frequency control signal s obtained by the above method is input, so that the reception side performs clock reproduction and outputs the reproduction synchronization output clock u. In addition, timing information is collected.

  In the reproduction clock output unit D, the frequency control signal s is converted into an analog frequency control signal t which is an analog value by the D / A converter 16 and then supplied to the voltage controlled crystal oscillator (VCXO) 17. The VCXO 17 controls the oscillation frequency by the frequency control signal t to generate the reproduction synchronization output clock u, and then supplies it to the oscillator counter 18 for output to the outside.

The oscillator counter 18 counts the number of reproduction synchronization output clocks u to generate a reproduction synchronization output clock count value v, and then supplies the count to the latch function unit 19. The latch function unit 19 holds and outputs the instantaneous value when the latch timing signal w is input from the change point detection unit 15 to the reproduction synchronization output clock count value v and generates the latch count value i. The data are supplied to the sampling unit 14, the phase comparator 8, and the previous value difference calculation unit 11, respectively. The supply to the phase comparator 8 and the previous value difference calculation unit 11 is feedback for generating the frequency control signal s, and the processing in the frequency control unit C described above is repeated.

  Now, the operation of the timing information collection unit 14 will be described separately for transmission line jitter information, frequency offset information, and frequency drift information.

  The jitter information value p collected as the first timing information is collected as the difference between the transmission interval of the timing information data value c transmitted by the transmitting device and the arrival interval of arrival at the receiving device. The difference between the transmission interval and the arrival interval occurs due to transmission path jitter, which is a fluctuation amount of transmission delay in the transmission path.

Timing information data values c because it is also a value that indicates the transmission time in the transmission apparatus, the transmission interval is extracted timing information data values before values <br/> difference obtained by the pre-value difference calculation according to equation (4) c Is given by the signal (d_c).

d_c1 = c2-c1, d_c2 = c3-c2 (4)
On the other hand, the arrival interval at the receiving device is given by the previous value difference signal (d_i) obtained by the previous value difference calculation by the equation (5) of the latch count value i.

d_i1 = i2-i1, d_i2 = i3-i2, ... (5)
The jitter information value p indicating the transmission path jitter is calculated by the difference according to the equation (6) between the arrival interval and the transmission interval.

p1 = d_i1−d_c1, p2 = d_i2−d_c2 (6)
Here, if the clock that collects the arrival interval does not synchronize with the clock that collects the transmission interval, the clock count value is frequency-asynchronous even if the condition that the transmission line jitter is zero and the arrival interval is equal to the transmission interval is satisfied. Different values are shown due to the deviation. Since this is output as an error value of the transmission line jitter as a result, it is necessary to increase the sampling accuracy by counting with the clock synchronized clock.

  The offset information collected as the second timing information indicates how much the frequency of the transmission side clock that counts the timing information data value c has a deviation from the reference clock frequency provided on the reception side. Is a value obtained by collecting The frequency deviation can be collected by counting the difference in the number of oscillations of each clock within a certain time. Therefore, the frequency offset information includes the updated increase value of the clock information (timing information data value c) on the transmission side and the free-running clock d matched with the clock frequency on the transmission side as a reference for sampling at regular intervals. Measurement is possible by comparing the updated increment value of the count value.

  For example, for a clock with a nominal frequency of 27 MHz, if there is a frequency offset of 10 ppm, this is an amount that produces a difference of 270 clocks per second. Further, when the arrival time is shifted by 1 msec due to the influence of the transmission path jitter, a shift of 27000 clocks occurs. This is equal to the difference in the number of clocks caused by the time of 100 seconds when the frequency offset is 10 ppm. Even if a clock with phase synchronization established with phase synchronization of 0 is sampled, a frequency offset of 1000 ppm is erroneously sampled due to the influence of transmission jitter of 1 msec. In order to suppress this to 1 ppm erroneous sampling, sampling for a long time of 1000 seconds is required. This is because counting of the number of clocks on the transmission side to be collected is set to 1 second at the transmission source, whereas on the receiving side to be collected, the number of clocks of 1 second + 1 msec is counted.

  Therefore, when the offset information is measured by the receiving device via the transmission line, a large collection error occurs unless it is collected in consideration of the influence of the transmission line jitter. In order to eliminate the influence of transmission jitter at the time of sampling, the number of clocks of the reproduction synchronization output clock u that is phase-synchronized with the clock on the transmission side to be sampled, that is, the clock of the timing information data value c is reproduced on the reception side is counted. To do. In this way, sampling can be performed simultaneously with counting the number of clocks as a reference provided on the receiving side. In light of the previous example, both clocks are counted for 1 second + 1 msec time, and the number of clocks is counted only for a time that includes transmission jitter equally, thereby canceling the influence of transmission jitter.

  In principle, the clock of the VCXO 17 and the clock of the free-running oscillator 3 can be measured and collected at an arbitrary timing on the receiving side. As an example of the arbitrary timing, the detection timing of the timing information data value c is used as the counting timing. It is set.

  The subtractor 36 (FIG. 3) calculates the offset information value q indicating the frequency offset amount by calculating the difference between the count values of the sampling reference clock and the clock to be sampled. The number of sampling reference clocks is calculated as a difference signal (dn_k) by calculating a difference between the free-running clock count value h and N samples before. The number of clocks to be collected is calculated as a difference signal (dn_i) by performing a difference calculation with respect to the latch count value i before N samples.

As an example, it is assumed that timing information data value c is detected is transmitted every 3 3 msec, set the sampling interval of the frequency offset amount to about 5 seconds. In this case, the clock increment is compared with the self-running clock count value h, the latch count value i, and the respective N = 151 count values that were stamped when the timing information data value c arrived. Conversion from the offset information value q to the frequency offset is performed by converting the difference between the counter values into the deviation frequency according to the sampling time.

  The drift information collected as the third timing information is the amount of time variation of the frequency offset. The M difference calculation unit 37 (FIG. 3) collects the drift information value r by performing a difference calculation between the offset information value q and the positive integer M samples before. It is assumed that the frequency drift amount is sampled at approximately one minute intervals under the same condition example as above. In this case, the drift information value r is collected by calculating the difference between the offset information values q of M = 1818. The conversion from the drift information output value r to the frequency drift is performed by converting the drift information value r into the frequency drift amount per unit time by dividing the drift information value r by the sampling time.

  FIG. 2 is a block diagram showing Embodiment 2 of the timing information collecting apparatus of the present invention. The timing information collection device does not generate the reproduction synchronization clock u as in the first embodiment, and calculates the latch count value i corresponding to the latch count value i related to the reproduction synchronization clock u by a simulation operation.

For this reason, the reproduction clock output unit D in the first embodiment is replaced with a pseudo reproduction clock output unit E. The timing information output unit A, the free-running clock generation unit B, and the frequency control unit C remain the same as in the first embodiment. However, as in the first embodiment, there is no supply of the free-running clock count value h from the nominal frequency adaptation unit 6 of the free-running clock generation unit B to the change point detection unit 15 of the recovered clock output unit D. The previous value difference value k is supplied from the previous value difference calculation unit 7 of the frequency control unit C to the reproduction clock output unit E.

The reproduction clock output unit E receives the previous value difference value k and generates a latch count value i based on the frequency control signal s from the frequency control unit C. As in the first embodiment, the latch count value i is supplied to the timing information output unit A and the frequency control unit C, and is used for collecting timing information and generating the frequency control signal s. The reproduction clock output unit E includes a normalization unit 20, a multiplier 22, an adder 23, and a previous value delay unit 24.

  The normalization unit 20 divides the digital value of the frequency control signal s supplied from the frequency control information calculation unit 10 by a given LIMIT value 21 that is the upper limit value of the absolute value as in Expression (7). Thus, the normalized frequency control signal x is generated by normalization and supplied to the multiplier 22.

x = s / LIMIT (7)
Here, the given LIMIT value 21 is a value related to the calculation accuracy, and is set to 32,768, for example, when 16-bit accuracy is ensured. Of the 16 bits, 1 bit is a sign and 15 bits is a numerical value.

The multiplier 22 includes a normalized frequency control signal x, a maximum deviation setting value 25 for setting a maximum frequency deviation amount, and a previous value difference value k supplied from the previous value difference calculation unit 7 of the frequency control unit C. And the pseudo VCXO increase control number y is generated, and then supplied to the adder 23. The maximum deviation set value 25 gives the maximum frequency deviation of the pseudo VCXO, and is slightly (3
It is a value with a margin). For example, if the transmitter clock accuracy is 30 [ppm], 100 [ppm]
Set. This is a set value that allows a variation in frequency deviation of ± 100 [ppm] when the normalized frequency control signal x changes in the range of [−1 ≦ x ≦ + 1].

  Now, when the free-running clock count value h is updated to h1, h2, and h3, the sample values k1 and k2 of the previous value difference value k are given by Expression (8), and the calculation in the multiplier 22 is performed by Expression (9). It becomes as follows. x1 and x2 are time series sample values of the normalized frequency control signal x.

k1 = (h2-h1), k2 = (h3-h2) ... (8)
y1 = (maximum deviation set value x1 · k1), y2 = (maximum deviation set value · x2 · k2) · · · (9)
The adder 23 generates a pseudo VCXO output hold value, that is, a latch counter value i by adding the pseudo VCXO increase control number y, the previous value difference value k, and the previous value delay hold signal z, and then a timing information collecting unit. 14 is supplied to the phase comparator 8, the previous value difference calculation unit 11, and the previous value delay holding unit 24. The previous value delay holding unit 24 delays the latch counter value i by one sample to generate a predelay holding signal z, and then supplies it to the adder 23.

The adder 23 calculates the latch counter value i by performing the operations shown in the equations (10) and (11). Assuming that the sample values of the latch counter value i are I1, I2, I3, and the sample values of the free-running clock count value h after the conversion of the nominal frequency are h1, h2, h3,
I2 = INT [I1 + k1 + y1] = INT [I1 + (1+ (maximum deviation setting value) ・ (x1) ・ (h2-h1)] = INT [I1 +
(h2-h1) + (maximum deviation setting value x1 · (h2-h1))] ... (10)
I3 = INT [I2 + k2 + y1] = INT [I2 + (1 + (maximum deviation setting value) · (x2) · (h3-h2)] = INT [I2 +
(h3-h2) + (Maximum deviation set value x2 (h3-h2))] ... (11)
Here, INT [] is an operation for rounding down the value of []. When calculating I2 and I3,
I1 and I2 are used, respectively, which are values supplied by the previous value delay holding unit 24.

In the second embodiment, the above-described pseudo VCXO simulation operation is repeated to update the value of the latch counter value I and supply it to the timing information output unit A to collect timing information.
[Industrial applicability]
As a typical industrial application of the present invention, PCR clock recovery, PCR clock jitter sampling, and PCR frequency offset sampling are performed on an MPEG-2 transport stream received through an environment with relatively large network jitter. Post PCR frequency drift collection.

The block diagram which shows Example 1 of the timing information collection device of this invention The block diagram which shows Example 2 of the timing information collection device of this invention The block diagram which shows an example of the timing information collection part in the timing information collection device of this invention The block diagram which shows an example of the frequency control information calculating part in the timing information collection device of this invention Flow chart showing processing contents of digital filter operation unit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data reception part 2 Timing information detection extraction part 3 Self-running oscillator 4,18 Oscillator counter 5 Reception timing stamping latch part 6 Nominal frequency adaptation part 7,11 Previous value difference calculation part 8,12 Phase comparator 9,13 Weight coefficient Adjustment unit 10 Frequency control information calculation unit 14 Timing information collection unit 15 Change point detection unit 16 D / A converter 17 Voltage controlled crystal oscillator (VCXO)
DESCRIPTION OF SYMBOLS 19 Latch function part 20 Normalization part 21, 41 LIMIT value 22 Multiplier 23, 41 Adder 24 Previous value delayer 25 Maximum deviation setting value 31, 32 Previous value difference calculating part 33, 36 Subtraction part 34, 35 N difference Calculation unit 37 M difference calculation unit 42 Digital filter calculation unit 43 Limiter A Timing information output unit B Free-running clock generation unit C Frequency control unit D Reproduction clock output unit E Pseudo reproduction clock output unit

Claims (9)

In the timing information collection device that collects the timing information of the input data received from the transmission line,
A clock output unit for generating a latch count value related to a recovered clock synchronized with a transmission source clock whose information is embedded in the input data as a timing information data value;
A free-running clock that is asynchronous with the transmission source clock is oscillated, the frequency of the free-running clock is corrected, and the free-running clock count value that is adapted to the nominal frequency of the transmission-source clock and the free-running clock count value A free-running clock generator for calculating the previous value difference value;
The timing information data value is detected and extracted from the input data, and the jitter information value, the offset information value, and the drift information value are collected from the timing information data value, the latch count value, and the free-running clock count value, A timing information output unit for outputting a detection timing signal indicating a detection instant of the timing information data value;
Subtracting the previous value difference of the latch count value from the previous value difference of the timing information data value and subtracting the previous value difference of the latch count value from the previous value difference of the free-running clock output value, A timing information collecting apparatus, comprising: a frequency control unit that calculates a frequency control signal by a value obtained by multiplying a subtraction result by a weighting factor and supplies the frequency control signal to the clock output unit. The timing information output unit includes:
A data receiver that receives the input data and outputs the received data as received data;
Detecting and extracting the timing information data value by inputting the received data, and a timing information detection and extraction unit for supplying the detection timing signal to the free-running clock generation unit;
The timing information data value, the latch counter value, and the free-running clock count value are calculated to comprise the jitter information value, the offset information value, and the drift information value. The timing information collection device according to claim 1. The self-running clock generation unit
A free-running oscillator that generates a free-running clock that is not synchronized with a transmission source clock related to the timing information data value;
An oscillator counter that counts the free-running clock generated by the free-running oscillator and generates a free-running clock count value;
A reception timing stamping latch unit that latches and holds the free-running clock count value at the moment of receiving the detection timing signal, and generates a latch free-running clock count value;
The latch free-running clock count value is calculated by multiplying the ratio of the nominal frequency related to the timing information data value with respect to the nominal oscillation frequency of the oscillator counter to calculate the free-running clock count value. A timing information collection unit, a nominal frequency adaptation unit that supplies the frequency control unit and the clock output unit, and
2. The first previous value difference calculation unit that generates the previous value difference value of the free-running clock count value each time the free-running clock count value is updated. 2. The timing information collecting device according to 2. The frequency control unit
A first phase comparator that subtracts the latch count value from the timing information data value to generate a timing phase comparison signal;
A first weighting factor adjusting unit that performs weighting operation on the timing phase comparison signal to generate a weighting timing phase comparison signal;
A second value that generates a previous value difference value of the latch count value each time the latch count value is updated.
Previous value difference calculation unit of
A second phase comparator that generates a latch count phase comparison signal by subtracting the previous value difference value of the latch count value from the previous value difference value of the free-running clock count value ;
A second weighting factor adjustment unit that performs a weighting operation on the latch count phase comparison signal to generate a weight latch count phase comparison signal;
The frequency control information calculation unit configured to generate a frequency control signal based on the weight timing phase comparison signal and the weight latch count phase comparison signal and supply the frequency control signal to the clock output unit. The timing information collection device according to claim 3. The clock output unit
A change point detector that generates a latch timing signal that tells the instantaneous timing when the free-running clock count value is updated and the value has changed;
A D / A converter that generates an analog frequency control signal by converting a digital value of the frequency control signal into an analog value;
VCXO for generating a reproduction synchronization output clock by controlling the oscillation frequency by the analog frequency control signal,
An oscillator counter that counts the number of clocks of the reproduction synchronization clock to generate a reproduction synchronization clock count value;
The latch function unit configured to generate and output the latch count value by holding and outputting the instantaneous value to which the latch timing signal is input with respect to the reproduction synchronization clock count value. 4. The timing information collecting device according to 4. The clock output unit
A normalization unit that normalizes and generates a normalized frequency control signal by dividing the digital value of the frequency control signal by a LIMIT value related to a given calculation accuracy that is an upper limit value of an absolute value;
The latch is executed by multiplying the normalized frequency control signal, a maximum deviation setting value for setting a maximum frequency deviation amount, and a previous value difference value supplied from the first previous value difference calculation unit. A multiplier for generating a pseudo VCXO increase control number as a counter value;
A previous value <br/> delay holding unit for generating a previous value delayed hold signal by one sample delayed with respect to the latch counter value,
Addition for generating the pseudo VCXO output holding value by adding the pseudo VCXO increase control number, the previous value difference value supplied from the first previous value difference calculation unit, and the previous value delay holding signal. The timing information collection device according to claim 1, wherein the timing information collection device comprises: The timing information collecting unit
A first previous value difference calculation unit for calculating a first previous value difference signal by performing a previous value difference calculation of the timing information data value;
Second before calculating the second prefix differential signal by performing prefix differential calculating said latch count value
A value difference calculation unit;
A first subtraction unit for calculating a jitter information value indicating the jitter amount by subtracting the first prefix differential signal from the second prefix differential signals,
A first N difference calculation unit that calculates a first difference signal by performing a difference calculation on the latch count value before N (positive integer) samples;
A second N difference calculation unit for calculating a second difference signal by performing a difference calculation with respect to N samples before the free-running clock count value;
A second subtraction unit that calculates an offset information value indicating a frequency offset amount by subtracting the first difference signal from the second difference signal;
3. The M (positive integer) difference calculation unit that calculates a drift information value indicating a frequency drift amount by calculating a difference between the offset information value and M samples before. Timing information collection device. The frequency control information calculation unit
An adder that generates an addition phase comparison signal by performing an addition operation of the weight timing phase comparison signal and the weight latch count phase comparison signal;
A digital filter arithmetic unit that generates a control signal by performing digital filter arithmetic processing on the addition phase comparison signal;
A limiter that generates the frequency control signal by limiting the control signal to a boundary value using a given LIMIT value and outputs the signal to the D / A converter. Item 5. The timing information collection device according to item 4. A program recording medium recording a program executed in the digital filter arithmetic unit according to claim 8, wherein the program is
Each time the timing information detection and extraction unit extracts the timing information data value, the cumulative phase comparison signal is accumulated to calculate a cumulative addition value;
A procedure for converting the absolute value of the addition phase comparison signal into an integer and limiting the upper limit;
A procedure for calculating a control coefficient obtained by performing a power-of-two operation with an index obtained by adding a predetermined number to the addition phase comparison signal obtained by the above procedure;
A program recording medium comprising: a procedure for calculating a control amount related to the control signal from the sign of the cumulative addition value and the coefficient.

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