JP2004096678A - Service clock transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To highly accurately reproduce a service clock which has been inputted to a transmitting side apparatus in a receiving side apparatus. <P>SOLUTION: The transmitting side apparatus 101 to which the service clock and a common clock have been inputted operates setting data by grasping comparatively rough second variations of the common clock and the service clock to reduce fine first variations of the common clock and the service clock which have been adjusted by adjusting frequencies and phases with operated digital setting data, and outputs the first variations and the setting data while containing them in clock data. A receiving side apparatus 102 to which the common clock and clock data have been inputted recovers and outputs the service clock by controlling an oscillation frequency by grasping comparatively rough variations of the common clock and the oscillation frequency to match fine third variations of the frequency and phase adjusted common clock and oscillation frequency with the first variations according to the setting data. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to electronic communication, and more particularly to an improvement in a system for transmitting a service clock.
[0002]
[Prior art]
An example of a conventional service clock transmission system is described in Non-Patent Document 1 issued in 1993. As shown in FIG. 17, this conventional service clock transmission system includes a transmitting device 1701, a receiving device 1702, and an ATM network 1703.
[0003]
The transmitting device 1701 receives the service clock and the network clock, and outputs a residual time stamp (hereinafter, RTS). The receiving device 1702 receives the network clock and the RTS and outputs a service clock. Here, the network clock is input from the ATM network 1703 to the transmitting device 1701 and the receiving device 1702, and the RTS is transmitted via the ATM network 1703.
[0004]
FIG. 18 shows a transmitting device of a conventional service clock transmission system. The transmitting side device 1701 of the conventional service clock transmission system includes a frequency dividing device 1801, a multiplying device 1802, a counter device 1803, and a latch device 1804. The frequency divider 1801 receives the service clock fs, and outputs a clock obtained by dividing fs (hereinafter, fs / N). The multiplication device 1802 receives the network clock fn and outputs a clock fnx obtained by multiplying the network clock fn. The counter device 1803 increases the count by one in one cycle of fnx, and outputs a counter. The latch device 1804 measures the period of fs / N using the counter from the counter device 1803, encodes the measured value into the RTS, and outputs it.
[0005]
FIG. 19 shows a receiving side device of a conventional service clock transmission system. The receiving side device 1702 of the service clock transmission system of the conventional example includes a FIFO device 1901, a multiplying device 1902, a counter device 1903, a comparing device 1904, and another multiplying device 1905. The FIFO device 1901 receives the service clock fs / N from the RTS and the comparison device 1904 and, when the service clock fs / N is input, outputs the input RTS. The frequency multiplier 1902 receives the network clock fn and outputs a clock fnx obtained by multiplying the network clock fn. The counter device 1903 increases the count by one in one cycle of fnx, and outputs a counter. The comparison device 1904 generates fs / N at the timing when the data obtained by decoding the RTS matches the count from the counter device 1903. The frequency multiplier 1905 receives fs / N and outputs a service clock fs.
[0006]
[Non-patent document 1]
ITU-T. I. 363, "B-ISDN ATM Adaptation Layer (All) Specification" (ADAPTATION LAYER (ALL) SPECIFICATION), International Telecommunication Union (ITU), 1993
[0007]
[Problems to be solved by the invention]
However, the conventional system described above has the following problems.
[0008]
The first problem is that the service clock input to the transmitting device cannot be reproduced with high accuracy in the receiving device.
[0009]
The reason is that if the cycle of fs / N is expressed as Ts and the cycle of fnx is expressed as tnx, generally, Ts is not an integral multiple of tnx, and the edges of the signal of fs / N and the signal of fnx are shifted. This is because the relationship between the service clock fs and the network clock fn cannot be accurately grasped with the RTS that is an integer value, and therefore, the service clock cannot be reproduced with high accuracy by the receiving device that has transmitted the RTS. This is in 1998, IEEE TRANSACTION ON COMMUNICATIONS, VOL46, NO. 1. The service clock output by the receiving apparatus includes a jitter called “Waiting time jitter”, which is disclosed in “Determining Parameters to Minimize Jitter Generation in the SRTS Method” published in JANUARY. Hereinafter, a mechanism for generating these jitters will be described.
[0010]
Generally, it can be expressed as Ts / tnx = M + p / q + ε. Here, M is an integer, p and q are mutually prime integers, ε is an irrational number, and p / q + ε is smaller than 1. Assuming that p / q + ε is 0, the RTS is always constant (M) and no jitter occurs. However, this assumption implies that Ts / tnx is an integer value, which is not realistic. Next, assuming that ε is 0, the values of the RTS form a sequence in which, of the q times transmitted, p times are M + 1 and q−p times are M. For example, if q = 3, p = 1,... M, M + 1, M, M, M + 1, M, M, M + 1, M,. In this case, fs / N on the receiving side periodically fluctuates (with a relatively short cycle (q cycle)), and jitter occurs. In many cases, the jitter having a relatively short cycle can be removed by a general PLL (Phase Locked Loop). However, this assumption also means that Ts / tnx is a rational number, and is not realistic. Next, assuming that ε is not 0, since ε is an irrational number, it can be expressed as ε = 1 / q1 + 1 / q2 + 1 / q3 +. At this time, the value of the RTS becomes M + 1 once for q1 times, and M + 1 once for q2 times, and similarly, a jitter (of a relatively long cycle (q1 cycle, q2 cycle,...)) Occurs.
[0011]
A second problem is that the time difference between the clock reproducing the service clock input to the transmitting device and the service clock input to the transmitting device cannot be controlled in the receiving device.
[0012]
The reason is that the RTS does not include the time information, and the ATM cell including the RTS information has a variable transmission delay when transmitted through the ATM network. Is difficult to use as time information in the receiving-side device.
[0013]
[Object of the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a service clock transmission system that can accurately reproduce a service clock input to a transmitting device in a receiving device. Another object of the present invention is to provide a service clock transmission system capable of controlling a time difference between a clock faithfully reproducing a service clock input to a transmitting device and a service clock input to a transmitting device in a receiving device. Is to provide.
[0014]
[Means for Solving the Problems]
A service clock transmission system according to the present invention includes a transmitting-side device including a frequency phase adjusting unit, a precision clock comparing unit, a standard clock comparing unit, and a digital setting data calculating unit. Means, frequency phase adjusting means, precision clock comparing means, standard clock comparing means, and oscillation frequency control data calculating means.
[0015]
In the transmitting device, the frequency / phase adjusting means outputs a first frequency / phase adjusted common clock according to the given digital setting data, and the precision clock comparing means outputs the first frequency / phase adjusted common clock and the service The first clock fluctuation, which is a fine clock fluctuation with respect to the clock, is measured. The standard clock comparing means measures the second clock fluctuation, which is a relatively coarse clock fluctuation between the common clock and the service clock, and sets the digital setting. The data calculating means grasps the first clock fluctuation and the second clock fluctuation, calculates the digital setting data so that the first clock fluctuation becomes as small as possible, gives the digital setting data to the frequency phase adjusting means, and provides the first clock fluctuation. The data representing the fluctuation and the digital setting data are included in the clock data and transmitted to the receiving device, In the receiving side device, the frequency control oscillating means oscillates according to the given oscillation frequency control data, and the frequency phase adjusting means according to the digital setting data included in the clock data and transmitted, the second frequency phase adjusted common Output a clock, and the precision clock comparing means measures a third clock fluctuation which is a minute clock fluctuation between the second frequency phase adjusted common clock and the clock oscillated by the frequency control oscillator, and outputs a standard clock. The comparing means measures a fourth clock fluctuation which is a relatively coarse clock fluctuation between the common clock and the clock generated by the frequency control oscillating means, and the oscillation frequency control data calculating means measures the third clock fluctuation and the fourth clock fluctuation. The fourth clock fluctuation is grasped, and the clock that matches the first clock fluctuation and the third clock fluctuation is described above. It calculates the oscillation frequency control data to oscillate at a wavenumber controlled oscillation means, to perform the operations of providing a frequency control oscillation means. As a result, the service clock input to the transmitting device can be reproduced with high accuracy in the receiving device.
[0016]
Further, the service clock transmission system according to the present invention is characterized in that the transmission-side device includes a transmission-side input / output timing adjustment unit, and the reception-side device includes a reception-side input / output timing adjustment unit.
[0017]
In the transmitting device, the transmitting input / output timing adjusting means performs data transmission with the precision clock comparing means in the transmitting device in synchronization with a sample clock obtained by dividing or multiplying the common clock. Data transmission with the digital setting data calculation means is performed asynchronously with the sample clock, and the reception-side input / output timing adjustment means performs data transmission with the precision clock comparison means in the reception-side apparatus by using a common clock. The operation is performed in synchronization with the frequency-divided or multiplied sample clock, and the data transmission with the oscillation frequency control data calculation means in the receiving device is performed asynchronously with the sample clock. Thus, the digital setting data calculation means and the oscillation frequency control data calculation means can operate asynchronously with the sample clock.
[0018]
Also, the service clock transmission system according to the present invention includes a first temporary storage unit, a delay unit, a second temporary storage unit, and a FIFO type storage unit in the transmission-side input / output timing adjustment unit. It is characterized by.
[0019]
The first temporary storage means receives the digital setting data and an update counter which is updated each time the digital setting data is calculated by the digital setting data calculating means from the digital setting data calculating means, and receives the sample clock every time the sample clock is input. The delay means outputs the data obtained by combining the digital setting data and the update counter and the digital setting data, the sample clock is delayed by a predetermined time, and the second temporary storage means outputs the update counter and the digital setting data. The data and the first clock storage data are input from the first temporary storage means, the first clock fluctuation data is input, the transmission-side precise clock comparison data composed of these data is held, and the sample clock output delayed by the delay means is output. Is input, outputs the precise clock comparison data on the transmission side and outputs the FIFO type The means holds the transmission-side precision clock comparison data and the order in which the transmission-side precision clock comparison data are output from the second temporary storage means, and in accordance with a request signal that is asynchronous with the sample clock, The operation of outputting the precise clock comparison data is performed. Thus, the writing of the digital setting data and the reading of the data of the first clock fluctuation are performed accurately in synchronization with the sample clock, and the correspondence between the written digital setting data and the data of the first clock fluctuation can be clearly grasped. To do.
[0020]
Also, the service clock transmission system according to the present invention includes a first FIFO type storage unit, a delay unit, a temporary storage unit, and a second FIFO type storage unit in the reception side input / output timing adjustment unit. It is characterized by:
[0021]
The first FIFO type storage means receives the transmission-side precision clock comparison data, and stores the transmission-side precision clock comparison data and the digital setting data in the transmission-side precision clock comparison data each time the sample clock is inputted. The precision clock comparison data is output in accordance with the input order, the delay means delays the sample clock by a predetermined time and outputs the sample clock, and the temporary storage means inputs the transmission-side precision clock comparison data from the first FIFO type storage means. At the same time, the data of the third clock fluctuation is input, the reception-side precise clock comparison data composed of these data is held, and when the sample clock output delayed by the delay means is input, the reception-side precision clock comparison is performed. Data, and the second FIFO-type storage means stores the receiving-side precision clock output from the temporary storage means. Holds the order in which the reception side precisely clock comparison data is input as comparison data in accordance with a request signal which is asynchronous with the sample clock, it executes the operation of outputting the reception side precisely clock comparison data. Thus, the writing of the digital setting data and the reading of the data of the third clock fluctuation are performed accurately in synchronization with the sample clock, and the correspondence between the written digital setting data and the data of the third clock fluctuation can be clearly grasped. To do.
[0022]
Also, the service clock transmission system according to the present invention includes a first temporary storage unit, a delay unit, a second temporary storage unit, and a FIFO type storage unit in the transmission-side input / output timing adjustment unit, The receiving side input / output timing adjusting means includes a first FIFO type storing means, a delaying means, a temporary storing means, and a second FIFO type storing means, and the frequency accuracy measuring means is provided in the receiving side device. It is characterized by having.
[0023]
The first temporary storage means in the transmission-side input / output timing adjustment means includes a digital setting data and an update counter which is updated each time the digital setting data is calculated by the digital setting data calculation means and a pulse signal each time a pulse signal is input. Holds the transmitting side pulse counter to be updated, and outputs digital setting data and data obtained by combining the updating counter and the transmitting side pulse counter and digital setting data each time the sample clock is input, and outputs the transmitting side input / output timing. The delay means in the adjustment means delays and outputs the sample clock for a fixed time, and the second temporary storage means in the transmission-side input / output timing adjustment means stores the transmission-side pulse counter, the update counter, and the digital setting data in the aforementioned manner. The data is input from the first temporary storage means and the first clock fluctuation data is input. When the sample clock output after being delayed from the delay unit is input, the transmission-side precise clock comparison data is output, and the transmission-side input / output timing adjustment unit is stored. The FIFO type storage means holds the transmission-side precision clock comparison data and the order in which the transmission-side precision clock comparison data are output from the second temporary storage means, and is asynchronous with the sample clock. According to the request signal, the transmission-side precise clock comparison data is output, the clock data including the transmission-side pulse counter is transmitted, and the first FIFO type storage means in the reception-side input / output timing adjustment means stores the transmission-side precision clock comparison data. Data is input and the receiving-side pulse counter is updated each time the transmitting-side precision clock comparison data and the pulse signal are input. Each time the sample clock is input, the transmission-side precision clock comparison data is compared with the transmission-side precision clock comparison data, the data obtained by combining the reception-side pulse counter, and the digital setting data in the transmission-side precision clock comparison data. The data is output in accordance with the input order, the delay means in the reception-side input / output timing adjustment means outputs the sample clock after delaying the sample clock by a fixed time, and the temporary storage means in the reception-side input / output timing adjustment means transmits the sample clock. Data obtained by combining the side precision clock comparison data and the reception side pulse counter is input from the first FIFO type storage means, the third clock fluctuation data is input, and the reception side precision clock comparison data composed of these is held. When the delayed sample clock is input from the delay means, the receiving-side precision clock ratio The second FIFO type storage means in the reception-side input / output timing adjustment means receives the reception-side precision clock comparison data and the reception-side precision clock comparison data output from the temporary storage means. In accordance with the request signal, which is asynchronous with the sample clock, the receiving-side precision clock comparison data is output according to the request signal. From the receiving-side pulse counter in the receiving-side precision clock comparison data, the time difference between the common clock of the transmitting device and the common clock of the receiving device is measured for a long time, and the common clock of the transmitting device and the receiving device are compared. An operation of measuring the frequency accuracy of the common clock is executed. This makes it possible to detect a difference between the common clock of the transmitting device and the common clock of the receiving device.
[0024]
In addition, the service clock transmission system according to the present invention includes an external pulse comparison unit and a pulse control unit in a transmission-side device, and an external pulse comparison unit, a pulse control unit, and a service clock in a reception-side device. And delay control means.
[0025]
The external pulse comparing means in the transmitting device compares the external reference pulse with the transmitting common clock pulse, outputs the comparison result as transmitting reference pulse difference data, and outputs clock data including the transmitting reference pulse difference data. The transmission, the pulse control means in the transmitting device controls the output time of the transmitting common clock pulse, and the external pulse comparing means in the receiving device compares the external reference pulse with the receiving common clock pulse. The comparison result is output as reception-side reference pulse difference data, the pulse control means in the reception-side device controls the output time of the reception-side common clock pulse, and the service clock delay control means in the reception-side device outputs Reference pulse difference data, reception-side reference pulse difference data, a transmission-side pulse counter in the reception-side precise clock comparison data, The time difference between the service clock input to the transmitting device and the service clock generated by the receiving device is measured from the receiving-side pulse counter in the receiving-side precise clock comparison data, and a part of the precise clock comparison data is duplicated. Alternatively, by setting discarding, the operation of controlling the time lag between the service clock input to the transmitting device and the service clock generated by the receiving device is executed. This makes it possible to control the delay of the service clock generated by the receiving device from the service clock input to the transmitting device.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0027]
FIG. 1 shows a service clock transmission system as a first embodiment of the present invention.
[0028]
In FIG. 1, a transmission side device 101 receives a service clock and a common clock, and outputs clock data which will be described in detail later. The receiving device 102 receives the common clock and the clock data and outputs a service clock. The common clock supply device 103 supplies a common clock to the transmitting device 101 and the receiving device 102.
[0029]
In FIG. 1, when the service clock and the common clock are given to the transmission-side apparatus 101, the transmission-side apparatus 101 uses the common clock to transmit data necessary for the reception-side apparatus 102 to recover the service clock. It is generated as data and transmitted to the receiving device 102.
[0030]
When receiving the common clock and the clock data, the receiving device 102 recovers the service clock from the common clock and the clock data and outputs the service clock.
[0031]
The common clock supply device 103 of FIG. 1 can use a network synchronization supply device or the like in a digital network, and can use a network synchronization signal supplied by the network synchronization supply device as a common clock, which is well known to those skilled in the art. Therefore, the detailed configuration is omitted.
[0032]
FIG. 2 shows the details of the transmitting apparatus 101 in FIG. In FIG. 2, the transmitting-side apparatus 101 includes a service clock converting unit 201, a common clock converting unit 202, a precision clock comparing unit 203, a standard clock comparing unit 204, a transmitting-side input / output timing adjusting unit 206, a digital setting data calculating unit 207 ( Hereinafter, the processor comprises a processor 207) and a frequency / phase adjusting unit 208.
[0033]
Hereinafter, an operation will be described in which the transmitting apparatus 101 to which the service clock and the common clock are input generates clock data, which will be described in detail later, and transmits the generated clock data to the receiving apparatus 102.
[0034]
The service clock converter 201 receives the service clock and outputs a clock (hereinafter, SrvClk) generated from the service clock. The common clock converter 202 receives a common clock, and generates a clock (hereinafter, RefClk) generated from the common clock, a clock whose frequency is 1 / N of RefClk (hereinafter, sample clock), and a transmission-side common clock in the present invention. A pulse having a frequency of 1 Hz generated from RefClk (hereinafter, 1 pps (common)), which is a pulse, is output.
[0035]
The precision clock comparison means 203 receives the SrvClk and the first frequency-phase adjusted common clock, and measures the tendency of fine (fine or precise) phase fluctuation between the SrvClk and the first frequency-phase adjusted common clock, In the present invention, data representing the phase variation as digital data of the first clock variation (hereinafter, transmission-side PhaseData) is generated, and the transmission-side PhaseData is output to the transmission-side input / output timing adjustment unit 206.
[0036]
The transmission-side input / output timing adjustment means 206 latches the transmission-side PhaseData at the timing of input of the sample clock, embeds the transmission-side PhaseData in the transmission-side precise clock comparison data described in detail later, and responds to the request of the processor 207. Output to the processor 207.
[0037]
On the other hand, the SrvClk, the sample clock, and 1 pps (common) are input to the standard clock comparison means 204, and the tendency of relatively coarse (rough) phase fluctuation of SrvClk and RefClk is measured. Is output to the processor 207 as standard clock comparison data described in detail later.
[0038]
The processor 207 grasps a tendency of fine phase fluctuation and a tendency of relatively coarse phase fluctuation of SrvClk and RefClk from the input transmission-side precise clock comparison data and standard clock comparison data, and sets the transmission-side PhaseData to 0. In the present invention, a parameter DDS-TW to be provided to the precision clock comparing means 203, which is digital setting data in the present invention, is calculated and output to the transmission-side input / output timing adjusting means 206 (function as digital setting data calculating means). ).
[0039]
The transmission-side input / output timing adjustment unit 206 receives the DDS-TW from the processor 207 and outputs the DDS-TW to the frequency / phase adjustment unit 208 according to the timing of the sample clock.
[0040]
The frequency / phase adjusting means 208 internally sets the input DDS-TW, and outputs a first frequency / phase adjusted common clock changed by the DDS-TW.
[0041]
The processor 207, which has received the transmission-side precise clock comparison data from the transmission-side input / output timing adjustment unit 206, combines the transmission-side reference pulse difference data and the transmission-side precision clock comparison data to generate clock data, which is transmitted to the reception-side device 102. I do.
[0042]
FIG. 4 shows details of the service clock conversion means 201 in FIG. In FIG. 4, the service clock conversion unit 201 includes a physical layer interface (hereinafter, PHY) 401, a jitter removal and frequency conversion device 403.
[0043]
Hereinafter, an operation in which the service clock conversion unit 201 to which the service clock is input generates and outputs SrvClk will be described.
[0044]
The PHY 401 receives a service clock, extracts a clock signal, and outputs the clock signal. The jitter removal and frequency conversion device 403 receives the clock signal, performs jitter removal and frequency conversion processing, generates and outputs SrvClk.
[0045]
FIG. 4 shows details of the common clock converter 202 in FIG. In FIG. 4, the common clock conversion means 202 includes a PHY 402, a jitter removal / frequency conversion device 404, a frequency divider 409 (hereinafter, 1 / N), and a 1 pps generator 410.
[0046]
Hereinafter, an operation in which the common clock conversion unit 202 to which the common clock is input generates and outputs 1 pps (common) according to RefClk and the sample clock will be described.
[0047]
The PHY 402 receives a common clock, extracts a clock signal, and outputs the clock signal. The jitter removal and frequency conversion device 404 receives the clock signal, performs jitter removal and frequency conversion processing, and generates and outputs RefClk. 1 / N409 receives RefClk, divides RefClk, generates and outputs a sample clock. When the sample clock is input and the frequency of the sample clock is f (sample clock), the 1 pps generator 410 receives 1 pps once every f (sample clock) input of the sample clock in accordance with the input timing of the sample clock. (Common) is output.
[0048]
FIG. 4 shows details of the precision clock comparing means 203 in FIG. In FIG. 4, the precision clock comparison means 203 includes a direct digital synthesizer (hereinafter, DDS) 405, a phase comparison device 407, and an analog / digital converter (hereinafter, A / D) 408.
[0049]
Hereinafter, the operation of generating and outputting the transmission-side PhaseData by the precise clock comparing unit 203 to which the SrvClk and the first frequency-phase adjusted common clock are input will be described.
[0050]
The DDS 405 receives SrvClk, generates and outputs a comparison clock converted by a fixed DDS-TW. The phase comparison device 407 compares the phase of the input comparison clock with the phase of the first frequency-phase adjusted common clock, and outputs the phase difference data as an analog signal. The A / D 408 converts the phase difference data input as an analog signal into a digital signal, and outputs the digital signal as PhaseData on the transmission side.
[0051]
FIG. 4 shows details of the standard clock comparing means 204 in FIG. In FIG. 4, the standard clock comparing means 204 includes a 1 pps generator 411 and a 1 pps difference detector 412.
[0052]
Hereinafter, an operation in which the standard clock comparing unit 204 to which SrvClk, the measurement clock (here, RefClk is diverted) and 1 pps (common) are input, outputs the data of the second clock fluctuation will be described.
[0053]
When the SrvClk is input and the frequency of the SrvClk is f (SrvClk), the 1 pps generator 411 outputs 1 pps (service) once in accordance with the input timing of the SrvClk every time the SrvClk is input f (SrvClk) times. . The 1 pps difference detector 412 receives 1 pps (service) and 1 pps (common) and a measurement clock, detects how many times the measurement clock is input between 1 pps (service) and 1 pps (common), Is output as clock fluctuation data.
[0054]
FIG. 4 shows details of the transmission-side input / output timing adjustment means 206 in FIG. In FIG. 4, the transmission-side input / output timing adjustment means 206 includes a register 414, a FIFO 415, and a register 416.
[0055]
In the following, the transmission-side input / output timing adjustment means 206 to which the sample clock, 1 pps (common), the DDS-TW, the update counter, and the transmission-side PhaseData are input, sets the transmission-side PhaseData to the timing at which the sample clock is input via the delay element. The operation of latching the transmission side PhaseData in the transmission side precision clock comparison data, outputting the data to the processor 207 in response to a request from the processor 207, and outputting the DDS-TW to the DDS 406 in accordance with the timing of the sample clock will be described. I do.
[0056]
The register 414 receives the DDS-TW and 1 pps (common) and a sample clock, and stores the DDS-TW and the data composed of three sets of the transmission-side pulse counter, the update counter, and the DDS-TW shown in FIG. And outputs according to the input timing of the sample clock.
[0057]
In FIG. 7, in S71, the process waits until a sample clock is input. In S71, when the sample clock is input, the process proceeds to S72, and it is determined whether 1 pps (common) is input simultaneously. In S72, if 1 pps (common) is input simultaneously, the process proceeds to S73. If 1 pps (common) is not input simultaneously, the process proceeds to S74. In S73, the transmission-side pulse counter is incremented. In S74, the updated DDS-TW and three sets of data are output according to the above-described procedure, and the process proceeds to S71.
[0058]
The FIFO 415 receives the data of three sets of the transmission counter, the update counter, and the DDS-TW shown in FIG. 6 and the transmission PhaseData in accordance with the timing determined by the sample clock via the delay element, and is input as shown in FIG. The transmission-side precise clock comparison data is accumulated and output in response to a request from the processor 207.
[0059]
The operation of the transmitting apparatus 101 will be described with reference to FIG.
[0060]
In FIG. 4, when a service clock is given to the PHY 401, a clock signal is extracted from the service clock in the PHY 401, the jitter is removed and the frequency is converted in the frequency converter 403, and the signal is output as SrvClk. . On the other hand, when the common clock is given to the PHY 402, the clock signal is extracted from the common clock in the PHY 402, the jitter is removed and the frequency is converted in the frequency converter 404, and the PHY 402 outputs the signal as RefClk.
[0061]
Here, SrvClk and RefClk are processed so that the signals have nominally the same frequency, but since the service clock and the common clock are generally generated from different clocks, the frequency accuracy, jitter, wander, drift, phase Note that the characteristics such as noise are different.
[0062]
SrvClk and RefClk are input to DDS 405 and DDS 406, respectively, and are processed into comparison clocks based on DDS-TW. Here, the DDS-TW of the DDS 406 is such that the comparison clock output from the DDS 405 and the comparison clock (first frequency phase adjusted common clock) output from the DDS 405 have frequency accuracy, jitter, wander, drift, Adjustments are made so that characteristics such as phase noise are equivalent. The calculation of the DDS-TW of the DDS 406 is performed by the processor 207 by grasping the tendency of relatively coarse phase fluctuation and the tendency of fine phase fluctuation.
[0063]
The tendency of relatively coarse phase fluctuation is grasped as follows. The SrvClk is input to a 1 pps generator 411, converted into a 1 pps signal (service), and input to a 1 pps difference detector 412. RefClk, on the other hand, is input to the frequency divider 409 and is used as a sample clock. The sample clock is input to the 1 pps generator 410, is set to 1 pps (common), and is input to the 1 pps difference detector 412. The 1 pps difference detector 412 to which 1 pps (service) generated from SrvClk and 1 pps (common) generated from RefClk are input, further receives a measurement clock diverted from RefClk, and receives 1 pps (service) and 1 pps (service). (Common) interval is measured by a measurement clock and output to the processor 207 as standard clock comparison data. The processor 207 uses this standard clock comparison data to grasp the tendency of relatively coarse phase fluctuation.
[0064]
On the other hand, the tendency of minute phase fluctuation is grasped as follows. The SrvClk is input to the DDS 405, converted into a comparison clock according to a given DDS-TW, and output to the phase comparison device 407. On the other hand, RefClk is input to the DDS 406, converted into a comparison clock according to the DDS-TW given from the processor 207 via the register 414, and output to the phase comparison device 407. The phase comparison device 407 to which the comparison clock output from the DDS 405 and the comparison clock output from the DDS 406 are input outputs the phase difference data to the analog-to-digital converter 408, and the analog-to-digital converter 408 to which the phase difference data is input. Performs analog-to-digital conversion on the phase difference data at the timing of the sample clock, and outputs the data to the register 416 as Phase Data on the transmission side. On the other hand, the register 414 outputs the transmission-side pulse counter, the update counter, and the DDS-TW to the register 416 according to the sample clock. The register 416 associates the transmission-side PhaseData, the transmission-side pulse counter, the update counter, and the DDS-TW with the FIFO 415 in accordance with the sample clock via the delay element, and writes the data as the transmission-side precise clock comparison data shown in FIG. Holds the transmission-side precise clock comparison data input according to the clock. The processor 207 reads the transmission-side precise clock comparison data from the FIFO 415 as needed, and grasps a tendency of minute phase fluctuation.
[0065]
In this way, the processor 207 that has grasped the tendency of the relatively coarse phase fluctuation and the tendency of the fine phase fluctuation recalculates the DDS-TW by reflecting these trends, and increments the update counter by one (increment). , To the register 414 (function as digital setting data calculation means).
[0066]
Further, the processor 207 outputs the transmission-side precise clock comparison data as clock data to the reception-side device. Here, the writing of the DDS-TW from the register 414 to the DDS 406 is synchronized with the sample clock, and the writing from the register 416 to the FIFO 415 is synchronized with the sample clock via the delay element. Note that writing the DDS-TW to 414 and reading the transmit-side precision clock comparison data from FIFO 415 to processor 207 are not synchronized to the sample clock and can be performed at any suitable timing for processor 207.
[0067]
FIG. 3 shows the details of the receiving apparatus 102 in FIG. In FIG. 3, the receiving device 102 includes a frequency control oscillating unit 301, a common clock converting unit 302, a precision clock comparing unit 303, a receiving side input / output timing adjusting unit 304, a standard clock comparing unit 305, an oscillating frequency control data calculating unit, It comprises a processor 307 corresponding to frequency accuracy measuring means and a frequency phase adjusting means 1308.
[0068]
Hereinafter, an operation in which the receiving-side apparatus 102 to which the common clock and the clock data are input generates and outputs a service clock will be described.
[0069]
The frequency control oscillator 301 receives the oscillation frequency control data and outputs a clock (hereinafter, SrvClk) generated from the oscillation frequency control data and a service clock. The common clock conversion unit 302 receives a common clock, and generates a clock (hereinafter referred to as RefClk) generated from the common clock, a clock whose frequency is 1 / N of RefClk (hereinafter referred to as a sample clock), and a frequency generated from RefClk of 1 Hz. (Hereinafter, 1 pps (common)) is output.
[0070]
The precision clock comparison means 303 receives the SrvClk and the second frequency-phase-adjusted common clock, and measures the tendency of fine phase fluctuation between the SrvClk and the second frequency-phase-adjusted common clock. It generates data (hereinafter, “Receive-side PhaseData”) representing the phase change as digital data of the clock change, and outputs the Receive-side PhaseData to the receive-side input / output timing adjustment unit 304.
[0071]
The receiving side input / output timing adjusting means 304 latches the receiving side PhaseData at the timing of input of the sample clock, embeds the receiving side PhaseData in the receiving side precise clock comparison data described in detail later, and responds to the request of the processor 307. Output to the processor 307.
[0072]
On the other hand, the standard clock comparing means 305 receives the measurement clock obtained by diverting SrvClk and RefClk and 1 pps (common), measures the tendency of relatively coarse phase fluctuation between SrvClk and RefClk, and in the present invention, the fourth clock The data is output to the processor 307 as standard clock comparison data as fluctuation data.
[0073]
The processor 307 grasps the tendency of fine phase fluctuation and the tendency of relatively coarse phase fluctuation of SrvClk and RefClk from the input precision clock comparison data and standard clock comparison data, and obtains continuous data of the receiving-side PhaseData. The oscillation frequency control data to be supplied to the oscillating means 301 is calculated and output to the oscillating means 301 with the aim of matching the continuous data of the transmission side PhaseData (function as the oscillating frequency control data calculating means).
[0074]
The receiving-side input / output timing adjustment unit 304 receives the clock data from the processor 307 and outputs the DDS-TW included in the clock data to the frequency / phase adjustment unit 308 in accordance with the timing of the sample clock. The frequency / phase adjusting unit 308 internally sets the input DDS-TW, and outputs a second frequency-phase adjusted common clock changed by the DDS-TW.
[0075]
In addition, the processor 307, to which the receiving-side precise clock comparison data is input, determines whether the data of the receiving-side precision clock comparison data whose reception-side pulse counter has changed is the data of the reception-side precision clock comparison data that has changed. Is observed, and if the number of data in the meantime changes suddenly, it is determined that an abnormality has occurred in 1 pps (common) of the transmitting device and the receiving device (function as frequency accuracy measuring means) .
[0076]
FIG. 5 shows details of the oscillation means 301 in FIG. In FIG. 5, the oscillating unit 301 includes a voltage controlled oscillator 501, a frequency converter 504, and a frequency converter 505.
[0077]
Hereinafter, an operation in which the oscillating unit 301 to which the oscillation frequency control data is input generates and outputs a service clock and SrvClk will be described.
[0078]
The voltage controlled oscillator 501 receives the oscillation frequency control data and outputs a clock signal. The frequency conversion device 504 receives the clock signal, performs a frequency conversion process, generates and outputs a service clock. The frequency converter 505 receives the clock signal, performs a frequency conversion process, generates and outputs SrvClk.
[0079]
FIG. 5 shows details of the common clock converter 302 in FIG. In FIG. 5, the common clock conversion means 302 includes a PHY 502, a jitter removal / frequency conversion device 503, 1 / N511, and a 1 pps generation device 512.
[0080]
Hereinafter, an operation in which the common clock conversion unit 302 to which the common clock is input generates and outputs RefClk, the sample clock, and 1 pps (common) will be described.
[0081]
The PHY 502 receives a common clock, extracts a clock signal, and outputs the clock signal. The jitter removal and frequency conversion device 503 receives the clock signal, performs jitter removal and frequency conversion processing, generates and outputs RefClk. 1 / N511 receives RefClk, divides RefClk, generates and outputs a sample clock. When the sample clock is input and the frequency of the sample clock is f (sample clock), the 1 pps generator 512 is synchronized with the input timing of the sample clock once every f (sample clock) input. Output 1 pps (common).
[0082]
FIG. 5 shows details of the precision clock comparing means 303 in FIG. In FIG. 5, the precision clock comparison means 303 includes a DDS 506, a phase comparison device 508, and an A / D 510.
[0083]
Hereinafter, the operation of generating and outputting the receiving-side PhaseData by the precise clock comparing unit 303 to which the SrvClk and the second frequency-phase adjusted common clock are input will be described.
[0084]
The DDS 506 receives SrvClk as input, generates and outputs a comparison clock converted by a fixed DDS-TW. The phase comparison device 508 compares the phases of the two types of input clocks and outputs the phase difference data as an analog signal. The A / D 510 converts the phase difference data input as an analog signal into a digital signal, and outputs the digital signal as PhaseData on the receiving side.
[0085]
FIG. 5 shows details of the standard clock comparing means 305 in FIG. In FIG. 5, the standard clock comparing means 305 includes a 1 pps generator 513 and a 1 pps difference detector 514.
[0086]
Hereinafter, an operation in which the standard clock comparing unit 305 to which SrvClk, the measurement clock, and 1 pps (common) are input, outputs the standard clock comparison data will be described.
[0087]
When the SrvClk is input and the frequency of the SrvClk is f (SrvClk), the 1pps generator 513 outputs 1 pps (service) once in accordance with the input timing of the SrvClk every time the SrvClk is input f (SrvClk) times. . The 1 pps difference detector 514 receives the measurement clocks of 1 pps (service) and 1 pps (common), detects how many times the measurement clock has been input between 1 pps (service) and 1 pps (common), and outputs the standard clock. Output as comparison data.
[0088]
FIG. 5 shows the details of the receiving-side input / output timing adjusting means 304 in FIG. In FIG. 5, the receiving-side input / output timing adjusting unit 304 includes a FIFO 516, a register 517, and a FIFO 518.
[0089]
Hereinafter, the receiving-side input / output timing adjusting means 304, which receives the sample clock, 1 pps (common), the transmission-side precise clock comparison data, and the receiving-side PhaseData, sets the receiving-side PhaseData to the timing at which the sample clock is input via the delay element. , And the receiver-side PhaseData is included in the receiver-side precise clock comparison data, output to the processor 307 in response to a request from the processor 307, and the DDS included in the transmitter-side precision clock comparison data is synchronized with the timing of the sample clock. An operation of outputting −TW to the frequency phase adjusting unit 308 (DDS 507) will be described.
[0090]
The FIFO 516 receives the precision clock comparison data, outputs the DDS-TW included in the precision clock comparison data to the DDS 507 in accordance with the input timing of the sample clock, and converts the precision clock comparison data with the data attached to the receiving side pulse counter. , According to the input timing of the sample clock. The FIFO 518 receives the transmission-side precision clock comparison data, the data including the reception-side pulse counter, and the reception-side PhaseData according to the timing determined by the sample clock via the delay element, and receives the reception-side pulse counter and the transmission-side precision data illustrated in FIG. Data composed of clock comparison data and reception-side PhaseData (hereinafter, reception-side precise clock comparison data) is accumulated and output in response to a request from the processor 307. The register 517 receives the data obtained by attaching the reception-side pulse counter to the reception-side PhaseData and the transmission-side precise clock comparison data, and the sample clock via the delay element, and inputs the data immediately before the sample clock via the delay element is input. The data obtained by attaching the reception-side pulse counter to the transmission-side precision clock comparison data and the reception-side PhaseData are output at the timing when the sample clock is input.
[0091]
The operation of the receiving device 102 will be described with reference to FIG.
[0092]
In FIG. 5, when the oscillation frequency control data is given to the voltage controlled oscillator 501, a clock is output in the voltage controlled oscillator 501 in accordance with the oscillation frequency control data, the frequency is converted in the frequency conversion device 504, and as a service clock. The frequency is converted by the frequency converter 505 and output as SrvClk.
[0093]
On the other hand, when the common clock is supplied to the PHY 502, the clock signal is extracted from the common clock in the PHY 502, the jitter is removed and the frequency is converted in the frequency converter 503, and the PHY 502 outputs the signal as RefClk. SrvClk and RefClk are input to DDS 506 and DDS 507, respectively, and are processed into comparison clocks based on DDS-TW.
[0094]
Here, the calculation of the oscillation frequency control data is performed by the processor 307. The relatively coarse phase fluctuation tendency on the transmitting side and the fine phase fluctuation tendency on the transmitting side are calculated by the processor 307, respectively. And the tendency of fine phase fluctuation on the receiving side.
[0095]
The tendency of relatively coarse phase fluctuation on the transmitting side is grasped by verifying a large change in the value of DDS-TW included in the clock data transmitted from the transmitting side device. The transmission side grasps the tendency of the minute phase fluctuation using the transmission side PhaseData included in the clock data transmitted from the transmission side device.
[0096]
The tendency of relatively coarse phase fluctuation on the receiving side is grasped as follows. SrvClk is input to a 1 pps generator 513, converted into a 1 pps signal (service), and input to a 1 pps difference detector 514. On the other hand, RefClk is input to the frequency dividing device 511 and is used as a sample clock. The sample clock is input to the 1 pps generating device 512, is set to 1 pps (common), and is input to the 1 pps difference detector 514. The 1 pps difference detector 514 to which 1 pps (service) generated from SrvClk and 1 pps (common) generated from RefClk are input, further receives a measurement clock diverted from RefClk, and receives 1 pps (service) and 1 pps (service). (Common) interval is measured by a measurement clock and output to the processor 307 as standard clock comparison data. The processor 307 uses the standard clock comparison data to grasp a relatively coarse tendency of phase fluctuation on the receiving side.
[0097]
The tendency of the minute phase fluctuation on the receiving side is grasped as follows. The SrvClk is input to the DDS 506, converted into a comparison clock in accordance with a given DDS-TW, and output to the phase comparison device 508. On the other hand, RefClk is input to the DDS 507, converted to a comparison clock via the FIFO 516 according to the DDS-TW given from the processor 307, and output to the phase comparison device 508. The phase comparison device 508 to which the comparison clock output from the DDS 506 and the comparison clock output from the DDS 507 are input outputs the phase difference data to the analog-to-digital converter 510, and the analog-to-digital converter 510 to which the phase difference data is input. Performs analog-to-digital conversion on the phase difference data at the timing of the sample clock, and outputs the data to the register 517 as PhaseData on the receiving side. On the other hand, the FIFO 516 outputs the reception-side pulse counter and the transmission-side precise clock comparison data to the register 517 in accordance with the sample clock. The register 517 stores the input PhaseData on the receiving side and data (hereinafter, receiving-side precise clock comparison data) relating the transmitting-side precision clock comparison data and the receiving-side 1 pps, and stores the data in accordance with the sample clock via the delay element. Output to The processor 307 appropriately reads out the reception-side precise clock comparison data from the FIFO 518 and grasps a tendency of minute phase fluctuation.
[0098]
In this way, the processor 307 determines the tendency of relatively coarse phase fluctuation on the transmission side, the tendency of fine phase fluctuation on the transmission side, the tendency of relatively coarse phase fluctuation on the reception side, and the fine phase fluctuation on the reception side. The trend of relatively coarse phase fluctuations on the transmitting side and the tendency of fine phase fluctuations on the transmitting side are, respectively, the tendency of relatively coarse phase fluctuations on the receiving side and the fine trend on the receiving side. The oscillation frequency control data is recalculated so as to match the tendency of the phase fluctuation, and is output to the frequency control oscillation means 301 (function of the oscillation frequency control data calculation means).
[0099]
In addition, the processor 307, to which the receiving-side precise clock comparison data is input, determines whether the data of the receiving-side precision clock comparison data whose reception-side pulse counter has changed is the data of the reception-side precision clock comparison data that has changed. Is observed, and if the number of data in the meantime changes suddenly, it is determined that an abnormality has occurred in the common clock of the transmitting device and the receiving device (function as frequency accuracy measuring means).
[0100]
Here, the writing of the DDS-TW from the FIFO 516 to the DDS 507, the writing of the transmission-side precise clock comparison data from the FIFO 516 to the register 517, and the writing of 1 pps of the receiving side are synchronized with the sample clock, and the writing from the register 517 to the FIFO 518 is The sample clock is synchronized with the delayed clock, and the writing of the DDS-TW from the processor 307 to the FIFO 516 and the reading of the receiving-side precision clock comparison data from the FIFO 518 to the processor 307 are not synchronized with the sample clock. Note that it can be implemented at any suitable timing for processor 307.
[0101]
FIG. 11 shows a service clock transmission system as a second embodiment of the present invention.
[0102]
In FIG. 11, a transmission side device 1101 receives a service clock, an external reference pulse, and a common clock, and outputs clock data described in detail later. The receiving device 1102 receives the common clock, the external reference pulse, the clock data, and the service clock delay control data, and outputs a service clock. The common clock supply device 1103 supplies a common clock to the transmitting device 1101 and the receiving device 1102. The reference pulse supply device 1104 supplies an external reference pulse to the transmitting device 1101 and the receiving device 1102.
[0103]
In FIG. 11, when a service clock, an external reference pulse, and a common clock are given to the transmitting device 1101, the transmitting device 1101 uses the external reference pulse and the common clock to recover the service clock in the receiving device 1102. Is generated as clock data and transmitted to the receiving-side apparatus 1102.
[0104]
When receiving the external reference pulse, the common clock, the clock data, and the service clock delay control data, the receiving device 1102 recovers the service clock from the external reference pulse, the common clock, and the clock data, and outputs the service clock according to the service clock delay control data. I do.
[0105]
As the common clock supply device 1103 in FIG. 11, a network synchronization supply device or the like in a digital network can be used, and a network synchronization signal supplied from the network synchronization supply device can be used as a common clock, which is well known to those skilled in the art. Therefore, the detailed configuration is omitted.
[0106]
As the reference pulse supply device 1104 in FIG. 11, a GPS receiver or the like can be used, and 1 pps supplied by the GPS receiver can be used as the reference pulse, which is well known to those skilled in the art. Is omitted.
[0107]
FIG. 12 shows details of the transmission-side device 1101 in FIG. In FIG. 12, a transmitting side apparatus 1101 includes a service clock converting unit 1201, a common clock converting unit 1202, a precision clock comparing unit 1203, a standard clock comparing unit 1204, an external reference pulse measuring unit 1205, a transmitting side input / output timing adjusting unit 1206, It comprises digital setting data calculation means 1207 (hereinafter, processor 1207) and frequency / phase adjustment means 1208.
[0108]
Hereinafter, an operation will be described in which the transmitting apparatus 1101 to which the service clock, the common clock, and the external reference pulse are input generates clock data, which will be described in detail later, and transmits the generated clock data to the receiving apparatus 1102.
[0109]
The service clock converter 1201 receives the service clock and outputs a clock (hereinafter, SrvClk) generated from the service clock. The common clock conversion unit 1202 receives a common clock and a pulse control signal, and generates a clock (hereinafter, RefClk) generated from the common clock and a clock whose frequency is 1 / N of RefClk (hereinafter, sample clock). A clock having a frequency of 1 Hz (hereinafter, 1 pps (common)) generated from RefClk, which is a transmission-side common clock pulse, is output according to the pulse control signal.
[0110]
The precision clock comparing means 1203 receives the SrvClk and the first frequency-phase adjusted common clock, and measures the tendency of fine phase fluctuation between the SrvClk and the first frequency-phase adjusted common clock. It generates data (hereinafter, transmission-side PhaseData) representing phase fluctuations as clock fluctuation data, and outputs the transmission-side PhaseData to the transmission-side input / output timing adjustment unit 1206.
[0111]
The transmission-side input / output timing adjustment means 1206 latches the transmission-side PhaseData at the timing when the sample clock is input, embeds the transmission-side PhaseData in the transmission-side precise clock comparison data described in detail later, and responds to the request of the processor 1207. Output to the processor 1207.
[0112]
On the other hand, the standard clock comparing means 1204 receives SrvClk, the sample clock, and 1 pps (common), measures the tendency of relatively coarse phase fluctuation between SrvClk and RefClk, and uses the result as the second clock fluctuation data in the present invention. Are output to the processor 1207 as standard clock comparison data, which will be described in detail later.
[0113]
The processor 1207 grasps the tendency of fine phase fluctuation and the tendency of relatively coarse phase fluctuation of SrvClk and RefClk from the input transmission-side precise clock comparison data and standard clock comparison data, and sets the transmission-side PhaseData to 0. In the present invention, a parameter DDS-TW to be provided to the precision clock comparing means 1203, which is digital setting data in the present invention, is calculated and output to the transmission-side input / output timing adjusting means 1206 (function as digital setting data calculating means). ).
[0114]
The transmission-side input / output timing adjustment unit 1206 receives the DDS-TW from the processor 1207 and outputs the DDS-TW to the frequency / phase adjustment unit 1208 in accordance with the timing of the sample clock.
[0115]
The frequency / phase adjusting unit 1208 internally sets the input DDS-TW, and outputs a first frequency / phase adjusted common clock changed by the DDS-TW.
[0116]
The external reference pulse measuring means 1205 receives an external reference pulse (hereinafter, 1 pps (external)), 1 pps (common) and a sample clock, and measures a timing difference between 1 pps (external) and 1 pps (common). The data is output to the processor 1207 as transmission-side reference pulse difference data.
[0117]
The processor 1207 that has received the transmission-side reference pulse difference data from the external reference pulse measurement unit 1205 and the transmission-side precision clock comparison data from the transmission-side input / output timing adjustment unit 1206 receives the transmission-side reference pulse difference data and the transmission-side precision pulse comparison data. The clock comparison data is synthesized to generate clock data, which is transmitted to the reception-side apparatus 1102. Further, the processor 1207, which has received the transmission-side reference pulse difference data, outputs a pulse control signal to the common clock conversion unit 1202 and controls the timing of 1 pps (common) (function as a pulse control unit).
[0118]
FIG. 14 shows details of the service clock conversion means 1201 in FIG. In FIG. 14, a service clock conversion unit 1201 includes a physical layer interface (hereinafter, PHY) 1401 and a jitter removal / frequency conversion device 1403.
[0119]
Hereinafter, an operation in which the service clock conversion unit 1201 to which the service clock is input generates and outputs SrvClk will be described.
[0120]
The PHY 1401 receives a service clock, extracts a clock signal, and outputs the clock signal. The jitter removal and frequency conversion device 1403 receives the clock signal, performs jitter removal and frequency conversion processing, generates and outputs SrvClk.
[0121]
FIG. 14 shows details of the common clock conversion means 1202 in FIG. In FIG. 14, the common clock converter 1202 includes a PHY 1402, a jitter removal / frequency converter 1404, a frequency divider 1409 (hereinafter 1 / N), and a 1 pps generator 1410.
[0122]
Hereinafter, the operation of generating and outputting 1 pps (common), RefClk, and a sample clock according to the pulse control signal by the common clock conversion unit 1202 to which the common clock and the pulse control signal are input will be described.
[0123]
The PHY 1402 receives a common clock, extracts a clock signal, and outputs the clock signal. The jitter removal and frequency conversion device 1404 receives the clock signal, performs jitter removal and frequency conversion processing, generates and outputs RefClk. 1 / N 1409 receives RefClk, divides RefClk, generates and outputs a sample clock. When the sample clock is input and the frequency of the sample clock is f (sample clock), the 1 pps generator 1410 receives the sample clock input timing and pulse control once every f (sample clock) input. A pulse (1 pps (common)) is output according to the signal.
[0124]
FIG. 14 shows details of the precision clock comparing means 1203 in FIG. In FIG. 14, the precision clock comparison means 1203 is composed of a direct digital synthesizer (hereinafter, DDS) 1405, a phase comparison device 1407, and an analog / digital converter (hereinafter, A / D) 1408.
[0125]
Hereinafter, the operation of generating and outputting the transmission-side PhaseData by the precision clock comparing unit 1203 to which the SrvClk and the first frequency-phase adjusted common clock are input will be described.
[0126]
The DDS 1405 receives SrvClk, generates and outputs a comparison clock converted by a fixed DDS-TW. The phase comparison device 1407 compares the phase of the input comparison clock with the phase of the first frequency-phase adjusted common clock, and outputs the phase difference data as an analog signal. The A / D 1408 converts the phase difference data input as an analog signal into a digital signal, and outputs the digital signal as Phase Data on the transmission side.
[0127]
FIG. 14 shows details of the standard clock comparing means 1204 in FIG. In FIG. 14, the standard clock comparing means 1204 includes a 1 pps generator 1411 and a 1 pps difference detector 1412.
[0128]
Hereinafter, an operation in which the standard clock comparing unit 1204 to which SrvClk, the measurement clock (here, RefClk is diverted) and 1 pps (common) are input will output the data of the second clock fluctuation.
[0129]
When the SrvClk is input and the frequency of the SrvClk is f (SrvClk), the 1 pps generator 1411 generates a pulse (1 pps (service)) once in accordance with the input timing of the SrvClk every time the SrvClk is input f (SrvClk) times. Is output. The 1 pps difference detector 1412 receives the measurement clocks of 1 pps (service) and 1 pps (common), detects how many times the measurement clock has been input between 1 pps (service) and 1 pps (common), Is output as clock fluctuation data.
[0130]
FIG. 14 shows details of the external reference pulse measuring means 1205 in FIG. In FIG. 14, the external reference pulse measuring means 1205 includes a 1 pps difference detector 1413.
[0131]
Hereinafter, an operation in which the external reference pulse measuring unit 1205, to which 1 pps (external), the sample clock, and 1 pps (common) are input, outputs the transmission-side reference pulse difference data will be described.
[0132]
The 1 pps difference detector 1413 receives an external reference pulse (1 pps (external)), 1 pps (common) and a measurement clock, and determines how many times the measurement clock is input between 1 pps (external) and 1 pps (common). Detected and output as transmission-side reference pulse difference data.
[0133]
FIG. 14 shows details of the transmission-side input / output timing adjusting means 1206 in FIG. In FIG. 14, the transmission-side input / output timing adjustment unit 1206 includes a register 1414, a FIFO 1415, and a register 1416.
[0134]
Hereinafter, the transmission-side input / output timing adjustment means 1206, which receives the sample clock, 1 pps (common), the DDS-TW, the update counter, and the transmission-side PhaseData, sets the transmission-side PhaseData to the timing at which the sample clock is input via the delay element. The following describes the operation of latching the transmission-side PhaseData in the transmission-side precise clock comparison data, outputting the data to the processor 1207 in response to a request from the processor 1207, and outputting the DDS-TW to the DDS 1406 in accordance with the timing of the sample clock. I do.
[0135]
The register 1414 receives the DDS-TW, 1 pps (common), and a sample clock, and stores the DDS-TW and the data composed of three sets of the transmission-side pulse counter, the update counter, and the DDS-TW shown in FIG. And outputs according to the input timing of the sample clock.
[0136]
In FIG. 7, in S71, the process waits until a sample clock is input. In S71, when the sample clock is input, the process proceeds to S72, and it is determined whether 1 pps (common) is input simultaneously. In S72, if 1 pps (common) is input simultaneously, the process proceeds to S73. If 1 pps (common) is not input simultaneously, the process proceeds to S74. In S73, the transmission-side pulse counter is incremented. In S74, the updated DDS-TW and three sets of data are output according to the above-described procedure, and the process proceeds to S71.
[0137]
The FIFO 1415 receives the data of three sets of the transmission counter, the update counter, and the DDS-TW shown in FIG. 6 and the transmission PhaseData in accordance with the timing determined by the sample clock via the delay element, and is input as shown in FIG. The transmission-side precision clock comparison data is accumulated and output in response to a request from the processor 1207.
[0138]
The operation of the transmitting apparatus 1101 will be described with reference to FIG.
[0139]
In FIG. 14, when a service clock is provided to a PHY 1401, a clock signal is extracted from the service clock in the PHY 1401, the jitter is removed and the frequency is converted in the frequency converter 1403, and the signal is output as SrvClk. . On the other hand, when the common clock is provided to the PHY 1402, a clock signal is extracted from the common clock in the PHY 1402, the jitter is removed and the frequency is converted in the frequency conversion device 1404, and the signal is output as RefClk.
[0140]
Here, SrvClk and RefClk are processed so that the signals have nominally the same frequency, but since the service clock and the common clock are generally generated from different clocks, the frequency accuracy, jitter, wander, drift, phase Note that the characteristics such as noise are different.
[0141]
SrvClk and RefClk are input to DDS 1405 and DDS 1406, respectively, and processed into comparison clocks based on DDS-TW. Here, the DDS-TW of the DDS 1406 is such that the comparison clock output from the DDS 1405 and the comparison clock (first frequency-phase adjusted common clock) output from the DDS 405 have frequency accuracy, jitter, wander, drift, Adjustments are made so that characteristics such as phase noise are equivalent. The calculation of the DDS-TW of the DDS 1406 is performed by the processor 1207 by grasping the tendency of relatively coarse phase fluctuation and the tendency of fine phase fluctuation.
[0142]
The tendency of relatively coarse phase fluctuation is grasped as follows. The SrvClk is input to a 1 pps generator 1411, converted into a 1 pps signal (service), and input to a 1 pps difference detector 1412. On the other hand, RefClk is input to the frequency dividing device 1409 and is used as a sample clock. The sample clock is input to the 1 pps generator 1410, is set to 1 pps (common), and is input to the 1 pps difference detector 1412. The 1 pps difference detector 1412 to which 1 pps (service) generated from SrvClk and 1 pps (common) generated from RefClk are input, further receives a measurement clock diverted from RefClk, and receives 1 pps (service) and 1 pps (service). (Common) interval is measured by a measurement clock and output to the processor 1207 as standard clock comparison data. The processor 1207 uses this standard clock comparison data to grasp the tendency of relatively coarse phase fluctuation.
[0143]
On the other hand, the tendency of minute phase fluctuation is grasped as follows. The SrvClk is input to the DDS 1405, converted into a comparison clock according to a given DDS-TW, and output to the phase comparison device 1407. On the other hand, RefClk is input to the DDS 1406, converted into a comparison clock according to the DDS-TW given from the processor 1207 via the register 1414, and output to the phase comparison device 1407. The phase comparator 1407 to which the comparison clock output from the DDS 1405 and the comparison clock output from the DDS 1406 are input outputs the phase difference data to the analog-to-digital converter 1408, and the analog-to-digital converter 1408 to which the phase difference data is input. Performs analog-to-digital conversion on the phase difference data at the timing of the sample clock, and outputs the result to the register 1416 as Phase Data on the transmission side. On the other hand, the register 1414 outputs the transmission-side pulse counter, the update counter, and the DDS-TW to the register 1416 according to the sample clock. The register 1416 associates the transmission-side PhaseData, the transmission-side pulse counter, the update counter, and the DDS-TW with the FIFO 1415 in accordance with the sample clock via the delay element, and writes the data as the transmission-side precise clock comparison data shown in FIG. Holds the transmission-side precise clock comparison data input according to the clock. The processor 1207 appropriately reads the transmission-side precise clock comparison data from the FIFO 1415, and grasps a tendency of minute phase fluctuation.
[0144]
In this way, the processor 1207 that has grasped the tendency of the relatively coarse phase fluctuation and the tendency of the fine phase fluctuation increases the update counter by one (increment), recalculates the DDS-TW, and outputs it to the register 1414 ( Function as digital setting data calculation means).
[0145]
The processor 1207, which has received the transmission-side reference pulse difference data from the 1pps detector 1413, combines the transmission-side precise clock comparison data and the transmission-side reference pulse difference data to generate clock data, and outputs the clock data to the reception-side device. Further, the processor 1207, which has received the transmission-side reference pulse difference data, outputs a pulse control signal to the common clock conversion unit 1202 and controls the timing of 1 pps (common) (function as a pulse control unit).
[0146]
Here, the DDS-TW write from the register 1414 to the DDS 1406 is synchronized with the sample clock, and the write from the register 1416 to the FIFO 1415 is synchronized with the sample clock via the delay element, while the processor 1207 sends the register 1414 Note that the writing of the DDS-TW to the processor and the reading of the transmit-side fine clock comparison data from the FIFO 1415 to the processor 1207 are not synchronized with the sample clock, and can be performed at any timing suitable for the processor 1207.
[0147]
FIG. 13 shows details of the receiving-side apparatus 1102 in FIG. In FIG. 13, the receiving-side apparatus 1102 includes a frequency control oscillating unit 1301, a common clock converting unit 1302, a precision clock comparing unit 1303, a receiving-side input / output timing adjusting unit 1304, a standard clock comparing unit 1305, an external reference pulse measuring unit 1306, It comprises an oscillation frequency control data calculation means, a frequency accuracy measurement means, a service clock delay control means, a processor 1307 corresponding to a pulse control means, and a frequency phase adjustment means 1308.
[0148]
Hereinafter, an operation in which the receiving-side apparatus 1102, to which the common clock, the external reference pulse, the clock data, and the service clock delay control data are input, generates and outputs a service clock will be described.
[0149]
The frequency control oscillator 1301 receives the oscillation frequency control data, and outputs a clock (hereinafter, SrvClk) and a service clock generated from the oscillation frequency control data. The common clock conversion unit 1302 receives the common clock, and receives a clock (hereinafter referred to as RefClk) generated from the common clock, a clock whose frequency is 1 / N of RefClk (hereinafter referred to as a sample clock), and a frequency generated from RefClk of 1 Hz. (Hereinafter, 1 pps (common)) is output. The precision clock comparing means 1303 receives the SrvClk and the second frequency-phase adjusted common clock, and measures the tendency of fine phase fluctuation between the SrvClk and the second frequency-phase adjusted common clock. It generates data (hereinafter, “Receiver PhaseData”) representing digitally representing phase fluctuations as clock fluctuation data, and outputs the Receiver PhaseData to the receiver-side input / output timing adjustment unit 1304.
[0150]
The receiving-side input / output timing adjusting means 1304 latches the receiving-side PhaseData at the timing of input of the sample clock, embeds the receiving-side PhaseData in the receiving-side precise clock comparison data described in detail later, and responds to the request of the processor 1307. Output to the processor 1307.
[0151]
On the other hand, the standard clock comparing unit 1305 receives a measurement clock obtained by diverting SrvClk and RefClk and 1 pps (common), measures the tendency of relatively coarse phase fluctuation between SrvClk and RefClk, and uses the fourth clock in the present invention. The data is output to the processor 1307 as standard clock comparison data as fluctuation data.
[0152]
The processor 1307 grasps the tendency of fine phase fluctuation and the tendency of relatively coarse phase fluctuation of SrvClk and RefClk from the input precision clock comparison data and standard clock comparison data, and obtains continuous data of the receiving side PhaseData. Oscillation frequency control data to be supplied to the oscillating means 1301 is calculated with the aim of matching continuous data of the transmission-side PhaseData on a time axis shifted by a time indicated by service clock delay data to be described in detail later. (Function as oscillation frequency control data calculation means).
[0153]
The receiving-side input / output timing adjustment unit 1304 receives clock data from the processor 1307 and outputs the DDS-TW included in the clock data to the frequency / phase adjustment unit 1308 in accordance with the timing of the sample clock. The frequency / phase adjusting unit 1308 internally sets the input DDS-TW, and outputs a second frequency / phase adjusted common clock changed by the DDS-TW.
[0154]
The external reference pulse measuring means 1306 receives the external reference pulse (1 pps (external)), 1 pps (common), and a sample clock, and measures a timing difference between 1 pps (external) and 1 pps (common), and later details Is output to the processor 1307 as reception-side reference pulse difference data.
[0155]
The processor 1307, which has received the receiving-side reference pulse difference data from the external reference pulse measuring means 1306 and has received the receiving-side precise clock comparison data from the receiving-side input / output timing adjusting means 1304, receives the receiving-side reference pulse difference data and the transmitting-side device. The service clock delay data is measured as the time difference between the service clock input to the transmitting device and the service clock generated by the receiving device using the reference pulse difference data included in the clock data transmitted from the transmitting device. Then, a part of the receiving-side precise clock comparison data is duplicated or discarded to control the delay of the service clock (function as service clock delay control means).
[0156]
Also, the processor 1307, to which the receiving-side precise clock comparison data is input, determines whether the transmission-side pulse counter of the receiving-side precise clock comparison data has changed and the data of the receiving-side precision clock comparison data that has changed the receiving-side pulse counter. Is observed, and if the number of data in the meantime changes suddenly, it is determined that an abnormality has occurred in 1 pps (common) of the transmitting device and the receiving device (function as frequency accuracy measuring means) .
[0157]
Further, the processor 1307, to which the receiving-side reference pulse difference data is input, outputs a pulse control signal to the common clock conversion unit 1302 and controls the timing of 1 pps (common) (function as a pulse control unit).
[0158]
FIG. 15 shows details of the oscillation means 1301 in FIG. In FIG. 15, the oscillating means 1301 includes a voltage controlled oscillator 1501, a frequency converter 1504, and a frequency converter 1505.
[0159]
Hereinafter, an operation in which the oscillating unit 1301 to which the oscillation frequency control data is input generates and outputs a service clock and SrvClk will be described.
[0160]
The voltage controlled oscillator 1501 receives the oscillation frequency control data and outputs a clock signal. The frequency conversion device 1504 receives the clock signal, performs a frequency conversion process, generates and outputs a service clock. The frequency converter 1505 receives the clock signal, performs a frequency conversion process, generates and outputs SrvClk.
[0161]
FIG. 15 shows details of the common clock conversion means 1302 in FIG. In FIG. 15, the common clock conversion means 1302 includes a PHY 1502, a jitter removal / frequency conversion device 1503, 1 / N 1511, and a 1 pps generation device 1512.
[0162]
Hereinafter, the operation of generating and outputting RefClk, a sample clock, and 1 pps (common) by the common clock conversion unit 1302 to which the common clock and the pulse control signal are input will be described.
[0163]
The PHY 1502 receives a common clock, extracts a clock signal, and outputs the clock signal. The jitter removal and frequency conversion device 1503 receives the clock signal, performs jitter removal and frequency conversion processing, and generates and outputs RefClk. 1 / N 1511 receives RefClk, divides RefClk, generates and outputs a sample clock. When the sample clock is input and the frequency of the sample clock is f (sample clock), the 1 pps generator 1512 adjusts the input timing of the sample clock once every f (sample clock) input. A pulse (1 pps (common)) is output according to the pulse control signal.
[0164]
FIG. 15 shows details of the precision clock comparing means 1303 in FIG. In FIG. 15, the precision clock comparing unit 1303 includes a DDS 1506, a phase comparing device 1508, and an A / D 1510.
[0165]
Hereinafter, the operation of generating and outputting the receiving-side PhaseData by the precise clock comparing unit 1303 to which the SrvClk and the second frequency-phase adjusted common clock are input will be described.
[0166]
The DDS 1506 receives SrvClk, generates and outputs a comparison clock converted by a fixed DDS-TW. The phase comparison device 1508 compares the phases of the two types of input clocks and outputs the phase difference data as an analog signal. The A / D 1510 converts the phase difference data input as an analog signal into a digital signal, and outputs the digital signal as PhaseData on the receiving side.
[0167]
FIG. 15 shows details of the standard clock comparing means 1305 in FIG. In FIG. 15, the standard clock comparing means 1305 includes a 1 pps generator 1513 and a 1 pps difference detector 1514.
[0168]
Hereinafter, an operation in which the standard clock comparing unit 1305 to which SrvClk, the measurement clock, and 1 pps (common) are input, outputs standard clock comparison data will be described.
[0169]
When the SrvClk is input and the frequency of the SrvClk is f (SrvClk), the 1 pps generator 1513 outputs a pulse (1 pps (service)) once every time SrvClk is input f (SrvClk) times according to the input timing of the SrvClk. Is output. The 1 pps difference detector 1514 receives the measurement clocks of 1 pps (service) and 1 pps (common), detects how many times the measurement clock is input between 1 pps (service) and 1 pps (common), and detects the standard clock. Output as comparison data.
[0170]
FIG. 15 shows details of the external reference pulse measuring means 1306 in FIG. In FIG. 15, the external reference pulse measuring means 1306 is constituted by a 1 pps difference detector 1515.
[0171]
Hereinafter, an operation in which the external reference pulse measuring means 1306 to which 1 pps (external), the measurement clock, and 1 pps (common) are input, outputs the receiving-side reference pulse difference data will be described.
[0172]
The 1 pps difference detector 1515 receives an external reference pulse (1 pps (external)), 1 pps (common) and a sample clock, and detects how many times the measurement clock is input between 1 pps (external) and 1 pps (common). Then, the data is output as receiving-side reference pulse difference data.
[0173]
FIG. 15 shows details of the reception-side input / output timing adjustment unit 1304 in FIG. In FIG. 15, the receiving-side input / output timing adjusting unit 1304 includes a FIFO 1516, a register 1517, and a FIFO 1518.
[0174]
Hereinafter, the receiving-side input / output timing adjusting means 1304, which receives the sample clock, 1 pps (common), the transmission-side precise clock comparison data, and the receiving-side PhaseData, sets the receiving-side PhaseData to the timing at which the sample clock is input via the delay element. , And the receiver-side PhaseData is included in the receiver-side precise clock comparison data, output to the processor 1307 in response to a request from the processor 1307, and the DDS included in the transmitter-side precision clock comparison data is synchronized with the timing of the sample clock. An operation of outputting −TW to the frequency phase adjusting unit 1308 (DDS1507) will be described.
[0175]
The FIFO 1516 receives the precision clock comparison data, outputs the DDS-TW included in the precision clock comparison data to the DDS 1507 in accordance with the input timing of the sample clock, and outputs the data obtained by attaching the reception side pulse counter to the precision clock comparison data. , According to the input timing of the sample clock.
[0176]
The FIFO 1518 receives the transmission-side precision clock comparison data and the data including the reception-side pulse counter and the reception-side PhaseData according to the timing determined by the sample clock via the delay element, and receives the reception-side pulse counter and the transmission-side precision data shown in FIG. Data composed of clock comparison data and reception-side PhaseData (hereinafter, reception-side precise clock comparison data) is accumulated and output in response to a request from the processor 1307.
[0177]
The register 1517 receives the data obtained by attaching the reception-side pulse counter to the reception-side PhaseData and the transmission-side precise clock comparison data, and the sample clock via the delay element, and inputs the data immediately before the sample clock via the delay element is input. The data obtained by attaching the reception-side pulse counter to the transmission-side precision clock comparison data and the reception-side PhaseData are output at the timing when the sample clock is input.
[0178]
The operation of the receiving-side apparatus 1102 will be described with reference to FIG.
[0179]
In FIG. 15, when oscillation frequency control data is supplied to a voltage controlled oscillator 1501, a clock is output in the voltage controlled oscillator 1501 in accordance with the oscillation frequency control data, and a frequency conversion is performed in a frequency conversion device 1504 to serve as a service clock. The frequency is converted and the frequency is converted in the frequency conversion device 1505 and output as SrvClk.
[0180]
On the other hand, when the common clock is supplied to the PHY 1502, a clock signal is extracted from the common clock in the PHY 1502, the jitter is removed and the frequency is converted in the frequency converter 1503, and the PHY is output as RefClk. SrvClk and RefClk are input to DDS1506 and DDS1507, respectively, and are processed into comparison clocks based on DDS-TW.
[0181]
Here, the calculation of the oscillation frequency control data is performed by the processor 1307, where the tendency of the relatively coarse phase fluctuation on the transmission side and the tendency of the fine phase fluctuation on the transmission side correspond to the relatively coarse phase fluctuation on the reception side, respectively. And the tendency of fine phase fluctuation on the receiving side.
[0182]
The tendency of relatively coarse phase fluctuation on the transmitting side is grasped by verifying a large change in the DDS-TW included in the clock data transmitted from the transmitting side device.
[0183]
The transmission side grasps the tendency of the minute phase fluctuation using the transmission side PhaseData included in the clock data transmitted from the transmission side device.
[0184]
The tendency of relatively coarse phase fluctuation on the receiving side is grasped as follows. SrvClk is input to a 1 pps generator 1513, converted into a 1 pps signal (service), and input to a 1 pps difference detector 1514. On the other hand, RefClk is input to the frequency divider 1511 to be used as a sample clock, and the sample clock is input to the 1 pps generator 1512, is set to 1 pps (common), and is input to the 1 pps difference detector 1514. The 1 pps difference detector 1514 receiving 1 pps (service) generated from SrvClk and 1 pps (common) generated from RefClk is further input with a measurement clock diverted from RefClk, and receives 1 pps (service) and 1 pps (service). (Common) interval is measured by a measurement clock and output to the processor 1307 as standard clock comparison data. The processor 1307 uses this standard clock comparison data to grasp the tendency of relatively coarse phase fluctuation on the receiving side.
[0185]
The tendency of the minute phase fluctuation on the receiving side is grasped as follows. The SrvClk is input to the DDS 1506, converted into a comparison clock in accordance with a given DDS-TW, and output to the phase comparison device 1508. On the other hand, the RefCk is input to the DDS 1507, converted into a comparison clock via the FIFO 1516 according to the DDS-TW given from the processor 1307, and output to the phase comparison device 1508. The phase comparator 1508 to which the comparison clock output from the DDS 1506 and the comparison clock output from the DDS 1507 are input outputs the phase difference data to the analog-to-digital converter 1510, and the analog-to-digital converter 1510 to which the phase difference data is input. Performs analog-to-digital conversion on the phase difference data at the timing of the sample clock, and outputs the data to the register 1517 as PhaseData on the receiving side. On the other hand, the FIFO 1516 outputs the reception-side pulse counter and the transmission-side precise clock comparison data to the register 1517 according to the sample clock. The register 1517 stores the input reception-side PhaseData and data (hereinafter, reception-side precision clock comparison data) in which the transmission-side precision clock comparison data and the reception-side pulse counter are associated with each other. Output to FIFO1518. The processor 1307 appropriately reads the reception-side precise clock comparison data from the FIFO 1518, and grasps a tendency of minute phase fluctuation.
[0186]
In this way, the processor 1307 generates a relatively coarse phase fluctuation tendency on the transmission side, a fine phase fluctuation tendency on the transmission side, a relatively coarse phase fluctuation tendency on the reception side, and a fine phase fluctuation on the reception side. The tendency of relatively coarse phase fluctuations on the transmitting side and the tendency of fine phase fluctuations on the transmitting side are, respectively, the tendency of relatively coarse phase fluctuations on the receiving side and the minute tendency on the receiving side. The oscillation frequency control data is recalculated so as to match the tendency of the phase fluctuation, and is output to the frequency control oscillation means 1301 (function of the oscillation frequency control data calculation means).
[0187]
The processor 1307, which has received the receiving-side reference pulse difference data from the external reference pulse measuring unit 1306 and the receiving-side precise clock comparison data from the receiving-side input / output timing adjusting unit 1304, receives the receiving-side reference pulse difference data and the receiving-side precision clock comparing data. The service clock delay data is measured using the transmission-side reference pulse difference data included in the clock data transmitted from the transmission-side device included in the clock comparison data, and the service clock delay is controlled (service clock delay control). Function as a means).
[0188]
Also, the processor 1307, to which the receiving-side precise clock comparison data is input, determines whether the transmission-side pulse counter of the receiving-side precise clock comparison data has changed and the data of the receiving-side precision clock comparison data that has changed the receiving-side pulse counter. Is observed, and if the number of data in the meantime changes suddenly, it is determined that an abnormality has occurred in the common clock of the transmitting device and the receiving device (function as frequency accuracy measuring means).
[0189]
Further, the processor 1307, to which the receiving-side reference pulse difference data is input, outputs a pulse control signal to the common clock conversion unit 1302 and controls the timing of 1 pps (common) (function as a pulse control unit).
[0190]
Here, the DDS-TW writing from the FIFO 1516 to the DDS 1507, the transmission-side precise clock comparison data from the FIFO 1516 to the register 1517, and the writing of 1 pps from the receiving side are synchronized with the sample clock. Writing from the register 1517 to the FIFO 1518 is sampled. The DDS-TW writing from the processor 1307 to the FIFO 1516 and the reading of the receiving-side precise clock comparison data from the FIFO 1518 to the processor 1307 are not synchronized with the sample clock, and are synchronized with the delayed clock. It can be performed at any timing suitable for the user.
[0191]
In the transmitting device and the receiving device, 1 pps (common) that is a common clock pulse may be generated in synchronization with an external reference pulse.
[0192]
【The invention's effect】
As described above, the present invention has the following effects.
[0193]
A first effect of the present invention is that a service clock input to a transmission-side device can be reproduced with high accuracy in a reception-side device.
[0194]
The first reason is that the service-side clock and the common clock are input to the transmitting side device, and the first frequency-phase-adjusted common clock and the service clock that are frequency-phase-adjusted based on the calculated digital setting data are finely divided. In order to reduce the clock fluctuation of the first clock fluctuation, the second clock fluctuation between the common clock and the service clock is grasped to calculate the digital setting data, and the first clock fluctuation and the digital setting data are included in the clock data. The receiving device receives the common clock and clock data, and adjusts the frequency and phase in accordance with the digital setting data. In order to match the fluctuation, the relatively coarse The system is configured to grasp the fourth clock fluctuation, control the oscillation frequency, recover and output the service clock, so that the receiving device can reproduce the service clock input to the transmitting device with high accuracy. Is obtained.
[0195]
The second reason is that data input / output to the means for calculating digital setting data and the means for calculating oscillation frequency control data are performed asynchronously with the sample clock, and the requirement for isochronous calculation speed is relaxed. This is because the effect of obtaining
[0196]
The third reason is that the writing of the digital setting data and the reading of the data of the first clock fluctuation can be performed accurately in synchronization with the sample clock, and the written digital setting data and the data of the first clock fluctuation can be written. This is because the effect of being able to clearly understand the correspondence between the two is obtained.
[0197]
The fourth reason is that the writing of the digital setting data and the reading of the data of the third clock variation can be performed accurately in synchronization with the sample clock, and the written digital setting data and the data of the third clock variation can be written. This is because the effect of being able to clearly understand the correspondence between the two is obtained.
[0198]
The fifth reason is that an effect of detecting a difference between the common clock of the receiving device and the common clock of the receiving device can be obtained.
[0199]
A second effect of the present invention resides in that a time difference between a clock that faithfully reproduces a service clock input to a transmitting device in a receiving device and a service clock input to a transmitting device can be measured and controlled.
[0200]
The reason is that the transmitting side device compares the external reference pulse input from outside the transmitting side device with the transmitting side common clock pulse generated by dividing or multiplying the common clock, and as clock signal data as the transmitting side reference pulse difference data. Control the output time of the transmission-side common clock pulse, and the reception-side device compares the external reference pulse with the reception-side common clock pulse generated by dividing or multiplying the common clock. A service clock input to the transmitting device and a service clock generated by the receiving device from the reference pulse difference data on the transmitting side and the reference pulse difference data on the receiving side by controlling the output time of the receiving side common clock pulse as the difference data. By measuring the time lag with respect to and duplicating or discarding part of the precision clock comparison data, Since the time lag between the service clock input to the receiving device and the service clock generated by the receiving device is controlled, the service clock generated by the receiving device is calculated from the service clock input to the transmitting device. This is because the effect that the delay of the data can be controlled can be obtained.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a service clock transmission system according to a first embodiment of the present invention;
FIG. 2 is a configuration diagram of a transmission side device according to the first embodiment.
FIG. 3 is a configuration diagram of a receiving-side device according to the first embodiment.
FIG. 4 is a configuration diagram showing details of a transmission-side device in the first embodiment.
FIG. 5 is a configuration diagram showing details of a reception-side device in the first embodiment.
FIG. 6 is a view for explaining data generated in a register of the transmitting device according to the first embodiment.
FIG. 7 is a flowchart showing a procedure for generating data in a register of the transmitting apparatus according to the first embodiment.
FIG. 8 is a view for explaining transmission-side precise clock comparison data in the first embodiment.
FIG. 9 is a view for explaining clock data in the first embodiment.
FIG. 10 is a view for explaining receiving-side precision clock comparison data in the first embodiment.
FIG. 11 is a configuration diagram of a service clock transmission system according to a second embodiment of the present invention;
FIG. 12 is a configuration diagram of a transmission side device according to the second embodiment.
FIG. 13 is a configuration diagram of a receiving-side device according to the second embodiment.
FIG. 14 is a configuration diagram illustrating details of a transmission-side device according to the second embodiment.
FIG. 15 is a configuration diagram showing details of a reception-side device according to the second embodiment.
FIG. 16 is a view for explaining clock data in the second embodiment.
FIG. 17 is a configuration diagram of a service clock transmission (SRTS) system according to a conventional example.
FIG. 18 is a configuration diagram of a transmission-side device in a service clock transmission (SRTS) system according to the conventional example.
FIG. 19 is a configuration diagram of a receiving side device in the service clock transmission (SRTS) system according to the conventional example.
[Explanation of symbols]
101: transmitting side device
102 ... Reception-side device
103: Common clock supply device
201: Service clock conversion means
202: Common clock conversion means
203: precision clock comparison means
204: standard clock comparing means
206 ... Transmission-side input / output timing adjustment means
207: Digital setting data calculation means (processor)
208: frequency phase adjusting means
301: frequency control oscillation means
302 ... Common clock conversion means
303 ... Precision clock comparison means
304: receiving side input / output timing adjusting means
305: Standard clock comparison means
307: oscillation frequency control data calculation means, frequency accuracy measurement means (processor)
308 ... frequency phase adjusting means
1101 ... Sending device
1102 ... Receiver device
1103: Common clock supply device
1104: External reference pulse supply device
1201 ... Service clock conversion means
1202 ... Common clock conversion means
1203 ... Precision clock comparison means
1204: Standard clock comparing means
1205 ... External reference pulse measuring means
1206: Transmission-side input / output timing adjustment means
1207 Digital setting data calculation means, pulse control means (processor)
1208 frequency frequency adjusting means
1301 frequency control oscillation means
1302 ... Common clock conversion means
1303: Precision clock comparison means
1304: receiving side input / output timing adjusting means
1305: Standard clock comparing means
1306 ... External reference pulse measuring means
1307: Oscillation frequency control data calculation means, frequency accuracy measurement means, service clock delay control means, pulse control means (processor)
1308 frequency phase adjusting means

Claims (11)

A transmitting device that receives the common clock and the service clock, generates clock data used in recovering the service clock in the receiving device, and transmits the clock data to the receiving device;
A service clock transmission system having the receiving device receiving the clock data and the common clock and recovering a service clock,
The transmitting device,
Frequency phase adjusting means for outputting a first frequency phase adjusted common clock in which the frequency phase of the common clock has been adjusted according to the given digital setting data,
Precision clock comparing means for measuring a first clock fluctuation which is a fine clock fluctuation between the first frequency phase adjusted common clock and the service clock,
Standard clock comparing means for measuring a second clock fluctuation that is a relatively coarse clock fluctuation between the common clock and the service clock;
Digital setting data calculating means for grasping the first clock fluctuation and the second clock fluctuation, calculating the digital setting data so that the first clock fluctuation is as small as possible, and providing the digital setting data to the frequency phase adjusting means. With
The data representing the first clock fluctuation and the digital setting data are included in the clock data, and are transmitted to the receiving device.
The receiving device,
Frequency phase adjusting means for outputting a second frequency phase adjusted common clock in which the frequency phase of the common clock is adjusted according to the digital setting data included and transmitted in the clock data,
Frequency control oscillation means capable of controlling the oscillation frequency,
Precision clock comparing means for measuring a third clock fluctuation which is a fine clock fluctuation between the second frequency phase adjusted common clock and the clock oscillated by the frequency control oscillating means,
Standard clock comparing means for measuring a fourth clock fluctuation which is a relatively coarse clock fluctuation between a common clock and a clock generated by the frequency control oscillation means,
Recognizing the third clock fluctuation and the fourth clock fluctuation, and oscillating frequency control data for causing the frequency control oscillating unit to oscillate a clock that matches the first clock fluctuation and the third clock fluctuation. A service clock transmission system comprising: an oscillating frequency control data calculating means for calculating and providing the oscillating frequency control data to the frequency control oscillating means. The transmitting device,
Data transmission with the precision clock comparing means in the transmitting device is performed in synchronization with a sample clock obtained by dividing or multiplying the common clock, and data transmission with the digital setting data calculating means in the transmitting device is performed by the sample clock. 2. The service clock transmission system according to claim 1, further comprising a transmission-side input / output timing adjustment unit that performs the operation asynchronously with the transmission clock. The receiving device,
Data transmission with the precision clock comparing means in the receiving device is performed in synchronization with the sample clock obtained by dividing or multiplying the common clock, and data transmission with the oscillation frequency control data calculating means in the receiving device is performed. 3. The service clock transmission system according to claim 1, further comprising a reception-side input / output timing adjustment unit that performs the operation asynchronously with the sample clock. The transmission-side input / output timing adjustment means,
Digital setting data and an update counter that is updated each time the digital setting data is calculated by the digital setting data calculating means are input from the digital setting data calculating means, and each time a sample clock is input, the digital setting data is updated. First temporary storage means for outputting the data and the digital setting data in combination with the update counter,
Delay means for delaying and outputting the sample clock for a predetermined time;
The update counter and the digital setting data are inputted from the first temporary storage means, and the data of the first clock fluctuation are inputted, and the update counter, the digital setting data and the first clock fluctuation are inputted. Holding the transmission-side precision clock comparison data composed of data, and when a sample clock output delayed with respect to the delay means is input, second temporary storage means for outputting the transmission-side precision clock comparison data;
The transmission-side precision clock comparison data output from the second temporary storage means and the order in which the transmission-side precision clock comparison data is input are held, and the transmission-side precision clock comparison data is asynchronous with the sample clock. 4. The service clock transmission system according to claim 2, further comprising first-in-first-out (hereinafter, FIFO) type storage means for outputting precision clock comparison data. The reception-side input / output timing adjustment means,
The transmission-side precision clock comparison data is input, and each time the sample clock is input, the transmission-side precision clock comparison data and the digital setting data in the transmission-side precision clock comparison data are converted to the transmission-side precision clock comparison data. First FIFO type storage means for outputting in accordance with the order
Delay means for delaying and outputting the sample clock for a predetermined time;
The transmission-side precise clock comparison data is input from the first FIFO type storage means and the third clock variation data is input, and the reception-side precision clock comparison data and the third clock variation data are received. Temporary storage means for holding the side precision clock comparison data, and receiving the sample clock output delayed with respect to the delay means and outputting the reception side precision clock comparison data;
The receiving-side precision clock comparison data, which holds the receiving-side precision clock comparison data output from the temporary storage means and the order in which the receiving-side precision clock comparison data is input, and is in accordance with a request signal that is asynchronous with the sample clock, The service clock transmission system according to any one of claims 2 to 4, further comprising a second FIFO-type storage unit that outputs a clock signal. The transmission-side input / output timing adjustment means,
The digital setting data and the digital setting data calculating means hold an update counter that is updated each time the digital setting data is calculated and a transmission-side pulse counter that is updated each time a pulse signal is input. First temporary storage means for outputting digital setting data, digital setting data, and data obtained by combining the digital setting data, the update counter, and the transmission-side pulse counter each time;
Delay means for delaying and outputting the sample clock for a predetermined time;
A transmission-side pulse counter, an update counter, and digital setting data are input from the first temporary storage means, and data of a first clock fluctuation is input, and the transmission-side pulse counter, update counter, and digital setting data are input. , And a second clock that outputs transmission-side precision clock comparison data when a sample clock output delayed from the delay unit is input. Temporary storage means,
The transmission-side precision clock comparison data stored in the transmission-side precision clock comparison data and the order in which the transmission-side precision clock comparison data are output from the second temporary storage unit are held in accordance with a request signal that is asynchronous with the sample clock. 4. The service clock transmission system according to claim 2, further comprising a FIFO type storage unit for outputting data. The reception-side input / output timing adjustment means,
Holds the transmission-side precise clock comparison data and holds the transmission-side precision clock comparison data and the reception-side pulse counter that is updated each time a pulse signal is input, and compares the transmission-side precision clock comparison each time a sample clock is input. First FIFO type storage means for outputting the data obtained by combining the data and the pulse counter on the receiving side and the digital setting data in the precision clock comparison data on the transmission side in accordance with the order in which the precision clock comparison data on the transmission side is input;
Delay means for delaying and outputting the sample clock for a fixed time;
Data obtained by combining the transmission-side precision clock comparison data and the reception-side pulse counter is input from the first FIFO type storage means, and the third clock fluctuation data is input. Holds receiving-side precision clock comparison data composed of data obtained by combining a receiving-side pulse counter and data of a third clock fluctuation, and receives a sample clock output delayed from the delay means, The temporary storage means for outputting the side precision clock comparison data, and the receiving precision clock comparison data output from the temporary storage means and the order in which the reception precision clock comparison data are input are held, and are asynchronous with the sample clock. A second FIFO type storage means for outputting reception-side precise clock comparison data in accordance with a certain request signal. International clock transmission system according to any one of claims 2, 3 and 6, characterized in that. 8. The service clock transmission system according to claim 4, wherein the clock data includes transmission-side precise clock comparison data. The clock data includes the transmission-side pulse counter,
The receiving device,
From the transmission-side pulse counter in the reception-side precision clock comparison data and the reception-side pulse counter in the reception-side precision clock comparison data, the time lag between the common clock of the transmission-side device and the common clock of the reception-side device is increased. 9. The service clock according to claim 6, further comprising frequency accuracy measuring means for measuring a period and measuring the frequency accuracy of the common clock of the transmitting device and the common clock of the receiving device. Transmission system. The transmitting device,
External pulse comparing means for comparing an external reference pulse input from outside the transmitting apparatus with a transmitting common clock pulse generated by dividing or multiplying the common clock, and outputting a comparison result as transmitting reference pulse difference data; ,
Pulse control means for controlling the output time of the transmission side common clock pulse,
The clock data includes the transmission-side reference pulse difference data,
The receiving device,
External pulse comparing means for comparing the external reference pulse with a receiving-side common clock pulse generated by dividing or multiplying the common clock, and outputting the comparison result as receiving-side reference pulse difference data;
Pulse control means for controlling the output time of the receiving side common clock pulse,
From the transmission-side reference pulse difference data, the reception-side reference pulse difference data, the transmission-side pulse counter in the reception-side precision clock comparison data, and the reception-side pulse counter in the reception-side precision clock comparison data, to the transmission-side device The time difference between the input service clock and the service clock generated by the receiving device is measured, and a part of the precision clock comparison data is duplicated or discarded and set, so that the service clock input to the transmitting device is set. 10. The service clock transmission system according to claim 6, further comprising service clock delay control means for controlling a time lag between the service clock generated by the reception side device and a service clock generated by the reception side device. The service clock transmission system according to claim 10, wherein the common clock pulse is generated in synchronization with an external reference pulse.

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