JPH03101329A - Clock synchronizing system - Google Patents

Abstract

PURPOSE:To reduce the probability of an overflow to a minimum by giving an initial value for compensation-setting counted values at the time of standard count to intermediate values to respective counters on a transmission-side and a reception-side, both of which count sampling clock information. CONSTITUTION:The initial values for compensation-setting the counted values at the time of standard count to the intermediate values are given to the counters 3 and 5. Namely, the initial values of the counters 3 and 5 are set to the values for compenstating the counted values at the time of standard count, which do not have the errors of oscillators 1 and 4, to the intermediate values of the counters. Consequently, the counted values at the time of standard count are returned to the intermediate values. Thus, the probability of the overflow is reduced to a minimum since a dynamic range becomes the largest.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for sending sampling clock information from the transmitting side to the receiving side in a coding transmission device such as a video transmission device to match the sampling clock frequency of both sides. The input signal is data-encoded using a sampling clock, the sampling clock is counted by a counter using a second oscillator that provides a transmission line clock as a reference, and the generated sampling clock information is multiplexed with the transmission data. The transmission line counter is extracted from the transmission data, the sampling clock information is separated, and the sampling clock by the third oscillator having the same frequency as the first oscillator is counted with a counter using the transmission line clock as a reference. In the clock synchronization method in which the third oscillator is synchronized by the difference with the sampling clock information, the purpose of always maximizing the dynamic range of both counters is to set the count value during standard counting to an intermediate value for both counters. It is configured to give an initial value for setting the correction.

[Industrial application field]

The present invention relates to a clock synchronization method, and more particularly to a method for sending sampling clock information from a transmitting side to a receiving side in a coding transmission device such as a video transmission device to match the sampling clock frequencies of both devices.

FIG. 3 shows a video transmission device as a coding transmission device, in which a video signal is converted into a digital signal by an A/D converter 31, further encoded by an encoding section 32, and then stored in a buffer memory (BM) 33. Temporarily store it in .

Up to this point, processing is performed based on the sampling clock generated by the sampling clock generation section 36.

Reading from the buffer memory 33 is performed according to the transmission line clock based on the oscillator 37, and is multiplexed with the sampling clock information and audio data from the sampling clock generation section 36 in the multiplexing section (MUX) 34, and the transmission section ( O3) It is sent to the transmission line from 35 in a form including the transmission line clock.

On the receiving side, a receiving section 41 receives the data, a filter 42 extracts the transmission line clock, a separating section (DMUX) 43 separates the video data, audio data, and sampling clock information, and then extracts the sampling clock based on this sampling clock information. A reproducing section 47 regenerates the sampling clock, and based on this sampling clock, the buffer memory 44, the decoding section 45, and the D/A converter 46 perform processing exactly opposite to that on the transmitting side to reproduce the video signal.

In this way, the transmission line clock is transmitted, but only the information about the sampling clock is transmitted, so it is necessary to transmit and reproduce it without error.

[Conventional technology]

A conventional method for transmitting sampling clock information will be briefly described. First, a transmission line clock is appropriately frequency-divided to obtain a constant time interval. Then, the number of sampling clocks of the transmitting device that occurred during that time is transmitted to the receiving side as clock information. On the receiving side, the frequency of the transmission line clock extracted from the transmission line is divided to obtain the same time interval as on the transmitting side, and the number of sampling clocks on the receiving side that occur during this time is counted. By controlling the sampling clock on the receiving side so that the count value on the receiving side matches the count value transmitted from the transmitting side, the sampling frequency on the receiving side is made to match that on the transmitting side.

FIG. 4 shows a specific example of a circuit that generates such sampling clock information (corresponding to the sampling clock generation section 36 in FIG. 3), in which the transmission line clock 32.
Consider an example in which a 7,159 MHz sampling clock is synchronized with a 7,159 MHz video transmission device.

In this case, the transmission line clock of oscillator 2 is divided into 1 by frequency divider 11 (frequency division ratio 1002) and frequency divider 12 (frequency division ratio 1024).
The frequency is divided by 026048 and applied to the counter 3 as a 31.25 Hz load signal. Note that the output of the frequency divider 11 (32
KHz) is used as the audio sampling clock.

The clock CK of the counter 3 has the frequency of the oscillator 1, which is 28.
636MHz is divided by frequency divider 13 (frequency division ratio 2) and frequency divider 14 (
This is a sampling clock for video processing (encoding) with a frequency of 7.159 MHz divided by a frequency division ratio of 2). Note that the output (14 MHz) of the frequency divider 13 serves as a video sampling clock for the A/D converter.

Therefore, the counter 3 counts the 7.159 MHz sampling clock at intervals of the 31.25 Hz load signal, latches it with a flip-flop (FF) 15, multiplexes it as sampling clock information based on the oscillator I, and transmits it. do.

In this case, the count value is (37EEO) (this is the standard value for the rated frequency of the oscillator), but as clock information, the upper bit r37
B is considered to be a fixed value considering the frequency accuracy of the clock. Therefore, from the standpoint of efficiency, only the lower 8 bits of this count value are transmitted.

On the receiving side, as shown in FIG. 5, this sampling clock information is extracted as shown in FIG. The oscillator 4 having the same frequency as the oscillator 1 shown in FIG.

On the other hand, the transmission line clock extracted from the transmitted data is the fourth
Frequency divider 24 provided corresponding to frequency divider 11 and 12 in the figure
．． 25 (both have the same frequency division ratio) and is given as a load signal to the counter 5.

Therefore, when the value counted within the period of the load signal of this counter 5 is different from the sent sampling clock information, the oscillator 4 is controlled by the difference, and PLL control is performed so that the two match. becomes.

[Problem to be solved by the invention]

Such sampling clock information indicates that the valid count values are (37EOO), I~(37EFF) n
(In other words, r371J does not count (00) M~
(FF), 8 bits), and if the frequency of the oscillator 1.4 fluctuates beyond this range, the 8-bit clock frequency information will overflow and correct clock information cannot be transmitted.

Therefore, in order for this 8-bit counter to tolerate the maximum frequency fluctuation of the input signal (maximum dynamic range), the number of frequency counts at the rated value must be (OOh ~ (FF)).
It is necessary to set it to exactly the middle value (7F)H of ++.

On the other hand, the clock count period of 31.25 Hz
In order to obtain this, it is necessary to divide the frequency by <1026048 as described above. Realizing this with a dedicated counter would require an increase in hardware, so in reality, as shown in Figures 4 and 5, other transmission line clocks (for example, sampling clocks for audio signals) required for the system are required. It is created by dividing a low-speed clock that depends on the transmission line clock.

For this reason, it is no longer possible to freely select the count period, and even in the above example, the standard count value at the rated value is (E
O) H, which gives the maximum dynamic range as shown in Figure 6(a) (7F) H
Since it is shifted further to the right, there is a problem in that when the error of the oscillator shifts to the right, it immediately overflows. For this reason, in practice, conditions have been attached to the frequency accuracy of the input signal to prevent overflow.

Therefore, in the present invention, data encoding of an input signal is performed using a sampling clock generated by a first oscillator, and sampling is generated by counting one sampling clock using a counter with reference to a second oscillator that provides a transmission line clock. Clock information is multiplexed on transmission data, and on the receiving side, the transmission line clock is extracted from the transmission data, the sampling clock information is separated, and a third oscillator having the same frequency as the first oscillator is generated based on the transmission line clock. In a clock synchronization method in which a sampling clock from an oscillator is counted by a counter and the third oscillator is synchronized based on the difference with the sampling clock information, the purpose is to always maximize the dynamic range of both counters.

[Means to solve the problem]

In order to achieve the above object, in the clock synchronization method according to the present invention, as shown in principle in FIG.
, 5 are given initial values for correcting and setting the count value during standard counting to an intermediate value.

[For production]

Conventionally, the initial value of counter 3.5 is "0". Therefore, in the present invention, the initial value of the counter 35 is set to a value for correcting the count value during standard counting without error of the oscillator 1.4 to the intermediate value of the counter.

As a result, the count value during standard counting is returned to the intermediate value, and the dynamic range is maximized, so the probability of overflow is minimized.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the clock synchronization method according to the present invention, in which (a) shows the counter 3 on the transmitting side;
b) shows the counter 5 on the receiving side.

In this embodiment, the audio sampling clock is selected to be 32 Hz as in the conventional example, and the frequency is further divided by 1024 to 31 Hz.
．． Load signals for counters 3 and 5 with an interval of 25 Hz,
At the interval of this load signal, clocks of sampling clock information 7.159 Mtlz are counted.

As a result, as mentioned above, the sampling clock information at the rated value (standard time) would be (EO)H if left as is, but in this embodiment, the initial value of counters 3 and 5 is (9c
) If M is inserted, the clock information becomes (EO)E(9C)M = (7F)M, as shown in FIG. 6(b), and the dynamic range becomes maximum.

In addition, since the clock frequency information is usually used with high accuracy, the transmission interval (sampling interval) may be long. Therefore, as in the conventional example, the transmission lock is divided by a large frequency and an appropriate transmission interval is set. However, having a dedicated frequency divider to obtain this large frequency division ratio will increase the hardware, so it is preferable to use a frequency divider provided for another purpose.

〔Effect of the invention〕

As described above, in the clock synchronization method according to the present invention, each counter on the transmitting side and the receiving side that counts sampling clock information is given an initial value for correcting and setting the count value during standard counting to an intermediate value. This configuration maximizes the dynamic range of each counter and minimizes the probability of overflow without the need to add special hardware.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the clock synchronization method according to the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, and Fig. 3 is a general coding method for multiplexing and transmitting sampling clock information. 4 is a diagram showing a sampling clock information generating section in the conventional clock synchronization method. FIG. 5 is a diagram showing a sampling clock information reproducing section in the conventional clock synchronization method. FIG. 6 is a diagram for explaining the dynamic range of the counters of the present invention and the conventional example. In Figure 1, 1, 2. 4...Oscillator, 3.5...Counter. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Data encoding of the input signal is performed using the sampling clock generated by the first oscillator (1), and the sampling clock is counted by the counter (3) based on the second oscillator (2) that provides the transmission line clock. The sampling clock information is multiplexed on the transmission data, and on the receiving side, the transmission line clock is extracted from the transmission data, the sampling clock information is separated, and the transmission line clock is used as a reference to make the transmission line clock the same as the first oscillator (1). A third oscillator of frequency (4
) is counted by a counter (5) and the third oscillator (4) is synchronized based on the difference between the sampling clock information and the sampling clock information. A clock synchronization method characterized by providing an initial value for correcting and setting a count value to an intermediate value.