JPH05244113A - Data transmission device - Google Patents

Abstract

PURPOSE:To surely obtain a stable reproducing sampling clock by using stuff information used for a frequency adjusting function of a synchronizing network, for reproducing a frame pulse. CONSTITUTION:Frequency information 17 is supplied to a reproducing sampling clock generating circuit 27, and from this reproducing sampling clock generating circuit 27, a reproducing sampling clock 9 is outputted. By this reproducing sampling clock 9, video encoded data 8 is read out of a video encoded data separating circuit 7. Also, the reproducing sampling clock 9 is supplied to a reproducing frequency information generating circuit 28, and reproducing frequency information 18 is generated. In this circuit 28, an output of a VC pulse generating circuit 15 is used as a clock for generating a period for latching a counter output of the reproducing sampling clock 9 to latch registers 24, 25. The VC pulse generating circuit 15 outputs a pulse for showing the head position of VC data, and from outputs of a stuff detecting circuit 10 and a pointer control circuit 11, the value of an AU pointer is generated as a pulse position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device for transmitting asynchronous data using a synchronous network, and more particularly to a data transmission device for unidirectional transmission of coded data such as image signals and audio signals.

[0002]

2. Description of the Related Art With the development of the information-oriented society, the signals to be transmitted are changing from analog signals to digital signals, and the transmission media are diversifying and speeding up. In addition, as the amount of information increases, the transmission method is also being multiplexed and hierarchized.
As a result, in order to establish a synchronous network on a global scale, CC
ITT (International Telegraph and Telephone Consultation Advisory Committee) proposed a new synchronous interface under the name of SDH (Synchronous Digital Hierarchy), which has a structure capable of flexibly synchronizing and multiplexing various high-speed service signals and signals of existing speed, and has been standardized. It was Currently, each country is promoting the digital hierarchy of the communication network based on this SDH, and the establishment of a synchronous network on a global scale is progressing.

When transmitting asynchronous data through a synchronous network, the stability of the sampling clock when reproducing the transmitted data on the receiving side is the stability and characteristics of the reproduced data after D / A (digital / analog) conversion. Have a great influence on. For this reason,
The development of a method with excellent reproduction frequency tracking and stability has been performed conventionally.

One of them is a frequency reproduction system by transferring frequency information. This method is a method of generating and reproducing frequency information based on a transmission line synchronization clock that can be commonly used by both the transmitting device and the receiving device.

However, in the case of one-way transmission of asynchronous data, a dedicated transmission line cannot be drawn to supply the transmission line synchronization clock to the transmitter. Therefore, a method is conceivable in which the transmission clock of the transmission device is generated by a free-running oscillator and the transmission clock is regenerated by the reception device using the frequency adjustment function on the synchronous network side. In this method, since the transmitting device and the receiving device are synchronized with each other on the basis of the transmission clock, the frequency reproduction method can be used.

[0006]

By the way, in this case,
The data received by the receiving device from the synchronous network is stuffed by frequency adjustment by the synchronous network. From here, the staff information is analyzed and destuffed, and the VC data is converted into S.
Separated from TM (Synchronous Transport Module) frame data. When the clock having the cycle of the destuffed VC data as the cycle of the frame pulse is reproduced, the transmission clock output from the oscillator on the transmitter side is reproduced. In the reproduction of the transmission clock, the VC data cycle varies due to destuffing, and therefore the frequency of the transmission clock having the cycle as this also varies.
In order to smooth and stabilize this frequency fluctuation, a PLL (Phase Locked Loop) circuit has been conventionally used.
Also, after this, the sampling clock is regenerated by the regenerated transmission clock, but the PLL circuit was also used here.

As described above, in the conventional case, the destuffed VC is
Separate PLL circuits are required for frequency reproduction twice, that is, reproduction of a frame pulse from data and reproduction of a sampling clock by frequency information, and the finally reproduced sampling clock has a frequency of two PLL circuits. It was influenced by stability. Therefore, there is a problem in that the reproduced data after D / A conversion may be unstablely supplied.

The present invention has been made in view of the above problems, and an object thereof is to provide a data transmission device capable of reliably and stably reproducing one-way data sent by using a synchronous network. ..

[0009]

SUMMARY OF THE INVENTION The present invention utilizes an synchronous network to synchronize S and Asynchronous data and frequency information.
A data transmission device for transmitting TM frame data from a transmission device to a reception device, wherein the reception device terminates section overhead from STM frame data received from a synchronous network and generates a frame pulse indicating the head position of the STM frame. Overhead termination circuit and the STM
An AU pointer terminating circuit for terminating the AU pointer information from the frame data, and S based on the AU pointer information.
A VC data separation circuit for destuffing TM frame data and separating VC data; a frequency information termination circuit for terminating the frequency information multiplexed by the transmitter from the VC data separated by this VC data separation circuit; A
A VC pulse generation circuit that generates a pulse indicating the start position of the VC data according to the U pointer information, a VC pulse division circuit that divides the pulse output from this VC pulse generation circuit, and a VC pulse division circuit that generates this pulse A reproduction frequency information generation circuit that counts the number of reproduction sampling clocks in each cycle and outputs the difference in the number of clocks in each cycle as reproduction frequency information, and reduces the difference between the frequency information and the reproduction frequency information. And a regenerated sampling clock generation circuit for generating the regenerated sampling clock.

In this data transmission device, in the reception device, section overhead data is read from the STM frame data input from the synchronization network by the overhead termination circuit, and the AU pointer is read by the AU pointer termination circuit. After that, the STM frame data is VC
The VC data supplied to the data separation circuit is terminated. From the VC data separated by this VC data separation circuit, the frequency information multiplexed by the transmitter is terminated in the frequency information termination circuit. Further, in the VC pulse generation circuit, a pulse indicating the head position of the VC data is generated according to the AU pointer information. The pulse output from this VC pulse generating circuit is divided into 1 / N in the VC pulse dividing circuit. Further, the reproduction frequency information generation circuit counts the number of reproduction sampling clocks in this frequency division cycle and outputs the difference in the number of clocks for each cycle as reproduction frequency information. Then, the reproduction sampling clock generating circuit oscillates so as to reduce the difference between the frequency information and the reproduction frequency information, and generates a reproduction sampling clock.

Specifically, the transmitting device generates a transmission clock oscillator for generating a transmission clock and a frame pulse indicating the start position of the STM frame data in synchronization with the transmission clock output from the transmission clock oscillator. A frame pulse generator circuit, a frame pulse divider that divides the frame pulse output from the frame pulse generator circuit, and the number of clocks of asynchronous data is counted by the cycle generated by this frame pulse divider, A frequency information generation circuit that outputs the difference in the number of clocks for each as frequency information, a multiplexing circuit that multiplexes the frequency information and asynchronous data output from this frequency information generation circuit into an STM frame, and the output from this multiplexing circuit ST done
An overhead insertion circuit that inserts section overhead data into the M frame data in synchronization with the transmission clock and inserts the section overhead data at a timing designated by the frame pulse.

With such a configuration, in the data transmission apparatus of the present invention, the stuff information used for the frequency adjusting function of the synchronous network can be added, and it is necessary to use the PLL circuit for reproducing the frame pulse. Absent. Further, when the reproduction sampling clock is generated, the deviation of the VC pulse in byte units due to destuffing is reduced to 1 / N by the VC pulse divider, and then input to the PLL circuit. For this reason, the influence of destuffing is sufficiently smoothed, and a stable regenerated sampling clock can be obtained reliably.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, it is premised that the one-way transmission of the video coded data by the synchronous network is performed by the frequency reproduction method.

When transmitting asynchronous data in one direction, it may not be possible to draw a dedicated transmission line for supplying the transmission line synchronization clock to the transmitting device, as described above. Therefore, a method is conceivable in which the transmission clock of the transmission device is generated by a free-running oscillator and the transmission clock is regenerated by the reception device using the frequency adjustment function on the synchronous network side.
FIG. 3 shows the system configuration viewed from the basic operation clock in this system.

On the transmitter side, the NTSC signal 46 is encoded by the video signal encoding unit 47, this encoded data is multiplexed by the video code data multiplexing unit 48, and the overhead data is inserted by the overhead insertion circuit 49. To do. The data in which the overhead data is inserted is multiplexed data, and the multiplexed data is transmitted to the receiving device side via the synchronous network 53. The synchronous network 53 is a DCS (Digital
Clock Supply) 51, 52, and these DCS51,
D which supplies the transmission line clock (f _DCS ) to each 52
And a CS clock oscillator 54.

Overhead of the multiplexed data transmitted via the synchronous network is terminated at an overhead termination section 55, and VC (virtual container) data is terminated at a VC termination section 56. Further, the video code data separating unit 57 separates the video code data from the multiplexed data, and the separated video code data is decoded in the video signal decoding unit 58 to reproduce NTS.
It is output as a C signal 59.

The frequency reproduction method requires that the same clock be provided between the transmitter and the receiver. Normally, the transmission line clock of the synchronous network is used. However, when data is transmitted in one direction like the transmission of the broadcast image signal in FIG. 3, the transmission path clock (f _DCS ) of the synchronous network 53 cannot be supplied to the transmitter. Since the STM frame data is supplied to the receiving device by the transmission line clock (f _DCS ) of the synchronous network, there is no common clock for transmission and reception which is a prerequisite for the frequency reproduction method.

Then, by utilizing the frequency adjusting function of the stuff control of the synchronous network 53, the transmission clock (f _OSC ) which is the output of the transmission clock oscillator 50 of the transmitter.
May be reproduced by the receiving device. In this case, the difference between the frequencies of the transmission path clock and the transmission clock is adjusted by the stuffing control of the AU pointer by the DCSs 51 and 52 of the synchronous network and transmitted to the receiving device. The receiving device can regenerate the transmission clock by analyzing and destuffing the stuff information of the AU pointer.

FIG. 1 is a block diagram of the data transmission device of this embodiment.
It is a block diagram showing the more concrete structure by the side of a receiver. FIG. 2 is a block diagram showing a specific configuration on the transmitter side.

First, the structure of the transmitter will be described.

The transmitter comprises a transmission clock oscillator 44 which generates a transmission clock. The transmission clock oscillator 44 is connected to the frame pulse generation circuit 43, the overhead insertion circuit 33, and the timing generation circuit 41, and sends a transmission clock to these circuits to synchronize with the transmission device side.

The frame pulse generation circuit 43 generates a frame pulse indicating the start position of the STM frame data in synchronization with this transmission clock. The frame pulse generation circuit 43 is connected to the frame pulse divider 42 that divides the frame pulse by 1 / N. The frame pulse frequency divider 42 is connected to the frequency information generation circuit 39.

The frequency information generating circuit 39 includes a counter 35, and the sampling clock 30 is input to the counter 35. This counter 35 has latch registers 36, 3
7 are connected in series. These latch registers 3
6 and 37 are both connected to the subtractor 38, and the count value of the counter 35 is latched at the 1 / N cycle generated by the frame pulse frequency divider 42, and the difference value between the two is used as frequency information 40 to generate the frequency information 40. The data is output to the information multiplexing circuit 32.

On the other hand, the video coded data 29 is input to the video coded data multiplexing circuit 31 in synchronization with the sampling clock 30. A timing generation circuit 41 is connected to the video coded data multiplexing circuit 31, and read timing data synchronized with the transmission clock 45 is multiplexed. The multiplexed coded data is sent to the frequency information multiplexing circuit 3
2 and the overhead insertion circuit 33, the STM frame data 34 is sent to the synchronous network transmission line.

The frequency information multiplexing circuit 32 receives the difference in the count number of the sampling clock for each 1 / N period of the frame pulse as frequency information 40 from the frequency information generating circuit 39, and outputs the multiplexed video coded data. It is to be further multiplexed. The overhead insertion circuit 33 further inserts overhead data into the video coded multiplexed data in which the frequency information is multiplexed, and outputs this as STM frame data.

In the synchronous network transmission line, the DCSs 51 and 52 are used for synchronization as shown in FIG. Stuff information for frame synchronization is added to the STM frame data 34, and the STM frame data 34 is transmitted to the receiving device side while synchronizing with each transmission path.

On the other hand, the structure of the receiving apparatus is as follows.

The STM frame data 34 transmitted from the synchronous network transmission line is input to the overhead termination circuit 3 in synchronization with the synchronous network transmission line clock 2. The STM frame data 34 is VC after the section overhead information is read by the overhead termination circuit 3.
It is output to the pulse generation circuit 15 and the AU pointer termination circuit 4.

The AU pointer terminating circuit 4 reads the AU pointer information of the overhead portion multiplexed in the STM frame data 34. This AU pointer information is
It is sent to the stuff detection circuit 10 and the pointer control circuit 11, respectively. The stuff detection circuit 10 detects the positive stuff and the negative stuff which are multiplexed in the STM frame data 34 based on the AU pointer information, and these stuffs are used as the positive stuff detection signal 13 and the negative stuff detection signal 12, respectively, as the VC pulse generation circuit 15 and the VC. It is output to the data separation circuit 5. On the other hand, the pointer control circuit 11 reads out the pointer information in the STM frame data 34, and outputs this pointer information to the VC data separation circuit 5.

A output from the AU pointer termination circuit 4
The U pointer information is also sent to the VC data separation circuit 5. In the VC data separation circuit 5,
STM frame data 34 synchronized with the transmission line clock 2
Therefore, the destuffing is performed based on the positive stuff detection signal 13 and the negative stuff detection signal 12, and the VC data is separated from the STM frame data 34 based on the pointer information from the pointer control circuit 11.

In the VC pulse generation circuit 15, the section overhead data read by the overhead termination circuit 3 and the positive stuff detection signal 13 and the negative stuff detection signal 12 are destuffed from the transmission line clock 2 to obtain V.
A timing pulse indicating the start position of the C data is generated.

A VC pulse frequency dividing circuit 16 is connected to the VC pulse generating circuit 15. The VC pulse dividing circuit 16 divides the timing pulse output from the VC pulse generating circuit 15 by 1 / N, and then sends the timing pulse to the latch registers 24 and 25 of the reproduction frequency information generating circuit 28. This 1 / N division reduces the shift in bit units due to destuffing to 1 / N,
The bit-wise shift due to destuffing is smoothed.

The VC data separated from the STM frame data 34 is input to the frequency information termination circuit 6. In the frequency information termination circuit 6, the frequency information 17 multiplexed by the frequency information multiplexing circuit 32 on the transmitter side is read out,
This frequency information 17 is reproduced sampling clock generation circuit 27.
Sent to.

The VC data is then input to the video data separation circuit 7 at the timing generated by the video encoded data write timing generation circuit 14. In the video data separation circuit 7, the video data is separated from the VC data in synchronization with the clock output from the reproduction sampling clock generation circuit 27, and the video encoded data 8 is output.

Here, the reproduction sampling clock generation circuit 27
Is a subtracter 22 that takes the difference between the frequency information 17 and the reproduction frequency information 18, the integration circuit 19 that integrates the output of the subtractor 22, and the output D of the integration circuit 19 that performs digital / analog conversion. The / A circuit 20 and the VCO (voltage control oscillator) 21 are arranged in series. The output of the VCO 21 is sent to the video data separation circuit 7 and the reproduction frequency information generation circuit 28 as the reproduction sampling clock 9.

In the reproduction frequency information generation circuit 28, the reproduction sampling clock 9 is input to the counter 26. Latch registers 25 and 24 are connected in series to the counter 26, and the output of the counter 26 is latched at the timing of the output pulse of the VC pulse frequency dividing circuit 16. The latch registers 24 and 25 are respectively connected to the subtractor 23, and the frequency fluctuation is taken in the cycle of 1 / N of the VC pulse, and this is used as the reproduction frequency information 18.
The data is sent to the reproduction sampling clock generating circuit 27.

Next, the operation of the data transmission apparatus of this embodiment will be described.

First, in the transmitter, the sampling clock 30
The video signal sampled at the timing of A is D / A-converted to become video coded data 29, which is input to the video coded data multiplexing circuit 31 and multiplexed on the STM frame at the timing of the transmission clock 45.

The frequency of the sampling clock 30 is multiplexed as frequency information 40 in the STM frame in the frequency information generation circuit 39, and the overhead is inserted in the overhead insertion circuit 33 together with the video coded data to generate the STM frame data 34 as the synchronization network 53 ( 3).

Here, in the frequency information generating circuit 39, the sampling clock from the sampling clock input terminal 30 is counted by the counter 35, and the count number is latched by the latch registers 36 and 37. Register 36, 3
7 is supplied with a 1 / N cycle pulse of the frame pulse generated by the STM frame pulse frequency dividing circuit 42,
By calculating the difference between the values latched in this cycle by the subtractor 38, the frequency fluctuation value is converted into information.

In the receiving device, the STM frame data 34 input from the synchronous network 53 receives the overhead termination circuit 3
Frame synchronization with the AU pointer termination circuit 4.
The pointer is read out and supplied to the stuff detection circuit 10 and the pointer control circuit 11. These outputs are supplied to the VC data separation circuit 5 to separate the VC data from the STM frame data 34.

Next, the frequency information 17 is read from the separated VC data by the frequency information termination circuit 6. At the same time, the VC data is written in the video coded data separation circuit 7 in synchronization with the output timing of the timing generation circuit 14. The frequency information 17 is supplied to the regenerated sampling clock generation circuit 27, and this regenerated sampling clock generation circuit 27 is supplied.
The reproduced sampling clock 9 is output from. By the reproduction sampling clock 9, the video coded data 8 is read from the video coded data separation circuit 7.

The reproduced sampling clock 9 is also supplied to the reproduced frequency information generating circuit 28, where the reproduced frequency information 18 is generated. In this circuit 28, the counter output of the reproduction sampling clock 9 is transferred to the latch registers 24 and 25.
The output of the VC pulse generation circuit 15 is used as a clock for generating the period for latching the signal. The VC pulse generation circuit 15 outputs a pulse indicating the start position of VC data,
The value of the AU pointer is generated as a pulse position from the outputs of the stuff detection circuit 10 and the pointer control circuit 11.

FIG. 4 shows STM frame data 3 on the receiving side.
4 shows the relationship between 4 and the phase of VC data.

5A to 5D show the phase relationship between the frame pulse of the STM frame data 34 and the VC pulse. The AU pointer represents the position within the VC data with respect to the STM frame pulse position, and this value can be used to determine the beginning of the VC data. When there is no frequency difference between the transmission clock (f _OSC ) and the transmission path clock (f _DCS ), the phase is fixed as in the relationship between STMFP and VCFP in FIG. When there is a difference between the frequency of the transmission clock (f _OSC ) and the frequency of the transmission path clock (f _DCS ), the position of the VC pointer fluctuates as in the case of STMFF of FIG. The device transmit clock (f _OSC ) will be _recovered .

Therefore, it is understood that the frequency reproduction method is effective in the receiving device by using the VC pulse as the frame pulse of the transmitting device. Since the position of the VC pulse shifts in byte units due to stuffing by the synchronous network, it becomes a factor that deteriorates the frequency stability of the regenerated sampling clock in the receiving device. However, according to this embodiment, VC
Since the pulse is divided into 1 / N by the VC pulse division circuit 16, the effect of stuffing is sufficiently smoothed.

As described above, in the data transmission apparatus of this embodiment, the stuffing information used for the frequency adjusting function of the synchronous network is used for the reproduction of the frame pulse in the reception apparatus, so that the reproduction of the frame pulse is performed. PLL
There is no need to use a circuit. Further, when the regenerated sampling clock is generated, the VC pulse frequency divider circuit 16 reduces the deviation of the VC pulse in byte units to 1 / N, and thereafter, the regenerated sampling clock generation circuit 27 and the reproduction frequency information generation circuit 28. It is input to the PLL circuit configured by. For this reason, the influence of destuffing is sufficiently smoothed, and a stable regenerated sampling clock can be obtained reliably.

[0048]

As described above, according to the data transmission apparatus of the present invention, the stuff information used for the frequency adjusting function of the synchronous network is used for the reproduction of the frame pulse. There is no need to use a PLL circuit, and when generating a reproduction sampling clock, the VC pulse frequency divider circuit reduces the deviation of the VC pulse in byte units due to destuffing, and then regenerates the sampling clock generation circuit and reproduction. Since it is input to the PLL circuit including the frequency information generation circuit, the influence of destuffing is sufficiently smoothed, and a stable and stable regenerated sampling clock can be obtained. That is, when transmitting image information using a synchronous network conforming to the digital hierarchy, simple one-way transmission using the frequency adjustment function of the transmission line can be performed using the conventional frequency information reproduction method. There is an effect that it can be realized with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a receiving side of a data transmission device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a transmission side of the data transmission device of FIG.

FIG. 3 is a system configuration diagram viewed from a reference clock of a transmission unit and a reception unit.

FIG. 4 is a frame configuration diagram of STM frame data and VC data.

5A and 5B are diagrams for explaining timings during stuff control of frame pulses and VC pulses reproduced by the receiving unit in FIG.

[Explanation of symbols]

 2 transmission line clock 3 overhead termination circuit 4 AU pointer termination circuit 5 VC data separation circuit 6 frequency information termination circuit 7 video data separation circuit 8 video coded data 9 reproduction sampling clock 10 stuff detection circuit 11 pointer control circuit 12 negative stuff detection Signal 13 Positive stuff detection signal 14 Video coded data write timing generation circuit 15 VC pulse generation circuit 16 VC pulse division circuit 17 Frequency information 18 Reproduction frequency information 19 Integration circuit 20 D / A (digital / analog) circuit 21 VCO 22 , 23 Subtractor 24, 25 Latch register 26 Counter 27 Reproducing sampling clock generating circuit 28 Reproducing frequency information generating circuit 29 Video coded data 30 Sampling clock 31 Video coded data multiplexing circuit 32 Frequency information multiplexing circuit 33 Overhead Insertion circuit 34 STM frame data 35 Counters 36, 37 Latch register 38 Subtractor 39 Frequency information generation circuit 40 Frequency information 41 Video coded data read timing generation circuit 42 Frame pulse frequency divider 43 Frame pulse generator 44 Transmission clock oscillator 45 Transmission clock 51, 52 DCS 53 Synchronous network

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display part H04L 12/48

Claims (2)

[Claims] 1. A data transmission device for transmitting STM frame data in which asynchronous data and frequency information are multiplexed from a transmission device to a reception device by using a synchronization network, wherein the reception device receives from the synchronization network. An overhead termination circuit for terminating the section overhead from the STM frame data and generating a frame pulse indicating the head position of the STM frame; an AU pointer termination circuit for terminating the AU pointer information from the STM frame data;
A VC data separation circuit that destuffs STM frame data based on U pointer information and separates VC data;
A frequency information termination circuit for terminating the frequency information multiplexed by the transmitter from the VC data separated by the VC data separation circuit, and a VC according to the AU pointer information.
A VC pulse generation circuit that generates a pulse indicating the start position of data, a VC pulse division circuit that divides the pulse output from this VC pulse generation circuit by 1 / N, and a cycle that is generated by this VC pulse division circuit. And a reproduction frequency information generation circuit that counts the number of reproduction sampling clocks and outputs the difference in the number of clocks for each cycle as reproduction frequency information, and oscillates to reduce the difference between the frequency information and the reproduction frequency information. And a reproduction sampling clock generating circuit for generating the reproduction sampling clock. 2. A transmission clock oscillator for generating a transmission clock, and a frame pulse generation for generating a frame pulse indicating a start position of STM frame data in synchronization with a transmission clock output from the transmission clock oscillator. Circuit, a frame pulse divider for dividing the frame pulse output from this frame pulse generation circuit, and the number of clocks of asynchronous data in the cycle generated by this frame pulse divider, and the clock for each cycle A frequency information generation circuit that outputs the difference in the number as frequency information, a multiplexing circuit that multiplexes the frequency information and asynchronous data output from this frequency information generation circuit into an STM frame, and an STM output from this multiplexing circuit. In the frame data, section overhead data is synchronized with the transmission clock, The data transmission device according to claim 1, further comprising an overhead insertion circuit that inserts at a timing designated by a frame pulse.