JP2697371B2 - Staff multiplex communication receiving circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stuff multiplex communication receiving circuit using a stuff multiplex communication system.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional stuff multiplex communication receiving circuit (Fu Yamashita, Telecommunication Association, Easy Digital Transmission, 108p). Is a destuff control circuit, 3 is a voltage controlled oscillator, 4 is a phase comparator, 5 is a low-pass filter, and 6 is a buffer memory.

Next, the operation will be described. The clock generated from the transmission line data by the write clock generation circuit 1 composed of a tank circuit or the like is used by the destuff control circuit 2 when a stuff pulse is detected in a multiplexed signal frame or when a stuff pulse is added. In the information portion, transmission of a clock is prohibited, and a write clock (WC) is generated. The insertion position of the stuff pulse is predetermined, and whether or not the stuff pulse has been inserted at that position is notified by a stuff designation pulse having a specific bit pattern. The writing of the stuff pulse is inhibited by the circuit 2. Then, the write clock (WC) is sent to the phase comparator 4 and input to the buffer memory 6, and the synchronization signal from the separation gate is written to the buffer memory 6 at this clock timing.

On the other hand, the output clock from the voltage controlled oscillator 3 is input to a phase comparator 4, which detects the phase error of the input signal, and comprises a low-pass filter 5 and the voltage controlled oscillator 3. The PLL performs feedback control, generates a read clock (RC) having a smooth average frequency, inputs the read clock (RC) to the buffer memory 6, and reads a low-order group signal from the buffer memory 6.

[0005]

The problem to be solved is that the conventional stuff multiplex communication receiving circuit is constructed as described above, so that there are many bits in which no information is contained in one frame. Another problem is that the PLL cannot suppress jitter. That is, FIG. 2 is a diagram showing the relationship between the frame structure and the clock input to the PLL. When there are a large number of bits in which no information enters in one frame including the service bit, the write clock (W
2C, the frequency difference between the read clock (RC) is increased, and as shown in FIG. 2A, the missing portion of the write clock input to the PLL is increased, so that the jitter amplitude is increased and the PLL is increased. Therefore, there is a problem that the jitter cannot be suppressed.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has as its object to provide a stuff multiplex communication receiving circuit capable of minimizing the occurrence of jitter.

[0007]

A stuff multiplex communication receiving circuit according to the present invention comprises: a frequency dividing circuit for dividing a clock generated from transmission line data into one frame period; A variable frequency dividing circuit that variably divides the frequency of the output signal, a phase comparator that compares the output of the variable frequency dividing circuit with the output of the frequency dividing circuit, and a low-pass filter based on the output of the phase comparator. Means for feedback controlling the oscillation frequency of the voltage controlled oscillator via
A destuff control circuit for controlling a write clock to the buffer memory depending on the presence or absence of stuff.

[0008]

The clock generated from the transmission line data is frequency-divided into one frame period, and the clock from the voltage controlled oscillator constituting the PLL is variably frequency-divided depending on the presence or absence of stuff to generate one frame period. Is compared by a phase comparator to perform feedback control, so that even if there is a portion without information in one frame, it is not affected by this.

As prior art related to the present invention, there is an invention disclosed in Japanese Patent Laid-Open Publication No. Sho 64-71351, "Digital Phase Locked Loop" (hereinafter referred to as prior art). In this prior art, “a time range for feeding back a phase comparison signal by inputting the frame synchronization signal existence position information and the stuff bit presence / absence detection signal existence position information as input” is set. It is characterized by not being used as a signal. On the other hand, the present invention is characterized in that the phase comparison is always performed for each frame, and the cause of the jitter can be removed while ensuring the PLL lock.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a write clock generation circuit, 2 is a destuff control circuit, 3 is a voltage controlled oscillator, 4 is a phase comparator,
Is a low-pass filter, 6 is a buffer memory, 7 is a frequency divider, 8
Is a frequency division ratio variable circuit.

FIG. 2 is a diagram showing the relationship between the frame structure and the clock input to the PLL, as described above. Each frame is composed of N bits, of which M bits include information including a stuff byte. A certain portion, other hatched portions have no information including service bits, (B)
The clock of P in the circuit of this embodiment shown in FIG.
The clock input to LL is shown.

Next, the operation will be described. The clock generated from the transmission line data by the write clock generation circuit 1 composed of a tank circuit or the like is input to the buffer memory 6 as a write clock (WC), and is also transmitted to the destuff control circuit 2 and the frequency divider 7. Can be In the destuff control circuit 2, the write clock generation circuit 1
When the stuff is present, a write enable signal for M bits is generated, and when there is no stuff, a write enable signal for Mm bits is generated and sent to the buffer memory 6. Variable frequency divider 8
Notify to Further, the frequency divider 7, the clock sent from the write clock generating circuit 1 is divided by the number of bits of one frame N, generates a frame period clock (frequency f _f) for the write clock (WC) the phase It is sent to the comparator 4.

On the other hand, the output clock of the voltage controlled oscillator 3 is divided by the frequency dividing ratio variable frequency dividing circuit 8, and is divided by M when there is stuff, and when there is no stuff, by the presence or absence of stuff from the destuff control circuit 2. The signal is divided by Mm and sent to the phase comparator 4, where the phase error of the two signals is detected by the phase comparator 4, and feedback control is performed by the PLL composed of the low-pass filter 5 and the voltage-controlled oscillator 3. Is performed, a read clock (RC) having a smooth average frequency is generated and input to the buffer memory 6, and the low-order group signal is read from the buffer memory 6.

That is, assuming that the rate at which stuff is generated on the transmitting side is δ, and the write clock (WC) is f _W when the frame structure shown in FIG. 2 is used, m stuff bits are given at a time. , The information rate f _O on the transmitting side is expressed as f _O = ｛Mδ + (1−δ) (M
−m)｝ / N · f _W ... Equation (1), which is transformed into f _W / N = f _O / OMδ + (1−δ) (M−
m)｝ Equation (2) is obtained, and the left side of the equation (2) is obtained by dividing the write clock by N by the frequency divider 7.
The denominator on the right side of (2) is an average frequency division number when the frequency division ratio is varied by the frequency division ratio variable frequency dividing circuit 8 depending on the presence or absence of the stuff bit from the destuff control circuit 2, and this is the average frequency division number. A clock that is input to the PLL and matches the information speed f _O of the transmitting side is reproduced from the voltage controlled oscillator 3, and this clock is input to the buffer memory 6 as a read clock (RC), and the read from the buffer memory 6 is performed. Then, the clock reproduced by the voltage controlled oscillator 3 includes only the destuff jitter, and as shown in FIG.
The clock input to the PLL is not affected by a part without information such as a service bit.

[0015]

As described above, the stuff multiplex communication receiving circuit of the present invention divides the clock generated from the transmission line data into one frame period, and if the number of bits written to the buffer memory differs depending on the presence or absence of stuff. At the same time, there is no information in one frame by generating a read signal in synchronization with the phase of the clock generated from the transmission line by variably dividing the frequency of the clock from the voltage controlled oscillator constituting the PLL according to the presence or absence of stuff. There is an advantage that a stuff multiplex communication receiving circuit which is not affected by the presence of a part can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a frame structure and a clock input to a PLL.

FIG. 3 is a block diagram showing an example of a conventional stuff multiplex communication receiving circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write clock generation circuit 2 Destuff control circuit 3 Voltage controlled oscillator 4 Phase comparator 5 Low pass filter 6 Buffer memory 7 Divider circuit 8 Divider ratio variable circuit

Claims (1)

(57) [Claims] 1. A buffer memory is written with a clock generated using a signal received from transmission line data,
A stuff that generates a read signal by synchronizing a clock output from a voltage controlled oscillator constituting LL with a phase of a clock generated from the transmission line, reads the buffer memory with the read signal, and outputs a low-order group signal In a multiplex communication receiving circuit, a frequency dividing circuit for dividing a clock generated from the transmission line data into one frame period, and a variable frequency dividing circuit for variably dividing a clock from the voltage controlled oscillator depending on the presence or absence of a stuff. A phase comparator for comparing the phase of the output of the variable frequency divider with the output of the frequency divider, and feedback control of the oscillation frequency of the voltage-controlled oscillator via a low-pass filter based on the output of the phase comparator. And a destuff control circuit for controlling the output of the write clock to the buffer memory depending on the presence or absence of stuff. Staff multiplex communication reception circuit to be.