JP4789976B2 - Clock generation enable generation circuit and clock recovery circuit - Google Patents

Description

  In processing high-speed transmission signals in an optical transmission system or the like, when performing demapping for extracting client data from a digital signal transmitted in a frame format, a clock signal is regenerated from the digital signal. The present invention relates to a clock recovery enable generation circuit and a clock recovery circuit that generate an enable signal necessary to recover the clock signal.

  At present, in an optical transmission system, as described in Patent Document 1, for example, a time division multiplexing method is adopted, and a plurality of low-speed digital signals are transmitted in order to economically transmit a digital signal to a destination. Time-division multiplexing is used to form one high-speed digital signal (also referred to as a high-speed transmission signal), and this high-speed transmission signal is transmitted to an optical fiber.

  In order to time-division multiplex a plurality of low-speed digital signals, it is necessary that the frequencies of the low-speed digital signals are exactly the same, and therefore the frequencies of the low-speed digital signals are synchronized by a stuff synchronization method or the like. In the stuff synchronization method, a low-speed digital signal that is client data is mapped to a frame format according to a clock signal of a predetermined frequency on the transmission side, and information is used to synchronize the frequency of each low-speed digital signal at the time of this mapping. Stuff processing is performed to insert a stuff pulse having no component. On the receiving side, frame format signals are demapped to restore client data, and destuffing processing is performed to remove stuff pulses at the time of restoration.

  When performing demapping, generally, a clock signal for writing client data for N clocks in the line data is reproduced from line data for M clocks transmitted in the frame format, The client data in the line data is written to the buffer memory by the signal. The written client data is read and restored by the oscillation clock signal of the oscillator synchronized with the reproduction clock signal. However, M and N in the number of M clocks and the number of N clocks are positive integers and have a relationship of N <M.

  Further, when the recovered clock signal is recovered from the line data at the time of demapping, it is necessary to generate an enable signal EN having a ratio (N / M) of client data corresponding to N clocks to line data corresponding to M clocks. . The generation of the enable signal EN will be described.

  For example, when M = 32 and N = 29, an addition circuit (not shown) that performs addition every time a clock signal extracted from the preamble of the line data is supplied, and the addition result AD output from this addition circuit “29” is added to the value, and when the addition result AD exceeds “32”, the subtraction of “32” is repeated. At this time, the arithmetic processing operation is performed so that the enable signal EN is output only when the addition result AD exceeds “32”. The subtraction of “32” when the addition result AD exceeds “32” is such that, for example, the addition circuit adds “−32” to “32”.

  This arithmetic processing operation will be described with reference to the timing chart of FIG. However, it is assumed that the timings of the times t1 to t33 coincide with the supply timing of the clock signal for operation to the adder circuit.

  At time t1, it is assumed that the addition result AD = “0” and the enable signal EN is in an output state, that is, “H” level (hereinafter referred to as “H”). In this case, since the addition result AD obtained by adding “29” to “0” is “29”, it does not exceed “32”. Accordingly, at time t2, the enable signal EN is not output, that is, the “L” level (hereinafter referred to as “L”). At the same time t2, the addition result AD = “29”.

  Since the addition result AD obtained by adding “29” to the addition result AD = “29” is “58”, it exceeds “32”. Therefore, at time t3, the enable signal EN becomes “H”. Also, since “58” exceeds “32”, “32” is subtracted to become “26”. As a result, the addition result AD = “26” at the same time t3.

  Since the addition result AD obtained by adding “29” to this addition result AD = “26” is “55”, it exceeds “32”. Therefore, at time t4, the enable signal EN becomes “H”. Since “55” exceeds “32”, “32” is subtracted to become “23”. As a result, at the same time t4, the addition result AD = “23”.

Similarly, when the process is repeated, for example, at time t11, since the addition result AD = “2”, the addition result AD obtained by adding “29” to “2” is “31” and exceeds “32”. Absent. Therefore, at time t12, the enable signal EN becomes “L”, and the addition result AD = “31”. Thereafter, by repeating similarly, the enable signal EN can be output during the period of the clock signal of a total of 29 clocks out of the clock signals of 32 clocks as shown in the figure.
Japanese Patent No. 3529713

  As described above, when the enable signal EN is generated, the stuff amount varies from frame to frame. Therefore, if the ratio (N / M) of the client data for the N clocks to the line data for the M clocks is a constant value. Therefore, there is a problem that it is difficult to generate an enable signal EN that matches the ratio.

Furthermore, when the amount of line data is large, the number of bits required for the adder circuit increases according to the amount of data, so that the circuit scale also increases. In the above example, the line data is for 32 clocks, so that 32 = 2 ⁵ , that is, an adder circuit for performing a 5-bit addition process is required. As described above, since the adding circuit cannot be operated at high speed as the scale of the adding circuit increases, there is a problem that the enable signal EN cannot be generated at high speed.

  If the enable signal EN cannot be generated at a high speed, the reproduction clock signal for writing the client data cannot be reproduced at a high speed. As a result, the demapping processing speed exceeds the limit.

  In order to solve the above-described problems, an object of the present invention is to generate an enable signal that matches the ratio of client data to line data at high speed with a simple circuit configuration.

  To achieve the above object, an enable signal for a period of N clocks (N: positive integer, where N <M) is generated during an output period of M clocks (M: positive integer). The clock recovery enable generation circuit is configured as follows. That is, one addition process is performed every time one clock signal is supplied, and a predetermined first value is determined according to a case where the value after the addition process is a negative value and a case where the value is 0 or a positive value. An addition circuit for adding the first addition value obtained by the mathematical expression or the second addition value obtained by the second mathematical expression to the value after the previous addition processing to obtain an addition result, and an addition circuit for outputting the addition result The count operation is performed only during a period when the addition result of the positive value is positive, and the clock signal is divided by a predetermined number by this count operation, and the addition result of the addition circuit is a negative value when the count result is output. And a comparator that outputs an enable signal when the count value of the period or frequency division counter is equal to or greater than a predetermined value.

  More specifically, during clock output for M clocks (M: positive integer), for clock recovery, an enable signal for N clocks (N: positive integer, where N <M) is generated. In the enable generation circuit, one addition process is performed every time one clock signal is supplied. If the value after the addition process is a negative value, the first expression (MN) obtained by the first equation (MN) is obtained. Is added to the value after the addition process, and if the value after the addition process is 0 or a positive value, the second formula {M × (PQ) ÷ PN} ( However, P: an integer of 2 or more, Q: an integer of 0 or more, and the second addition value obtained by Q <P <M) is added to the value after the addition processing to obtain an addition result, and this addition result is output. And the counting operation is performed only during a period when the addition result of the adding circuit is a positive value. The frequency dividing counter that divides the clock signal by P and outputs the count value at this time, and enabled when the addition result of the adding circuit is a negative value or when the count value of the frequency dividing counter is Q or more A clock recovery enable generation circuit comprising: a comparator that outputs a signal.

According to this configuration, for example, when M = 32, N = 29, P = 8, and Q = 1, the first addition value obtained by the first equation (MN) is (32-29). ) = 3, and the second addition value obtained by the second mathematical expression {M × (PQ) ÷ PN} is {32 × (8-1) ÷ 8-29} = − 1. . Therefore, the addition circuit uses the first addition value “3” or the second addition value “−1”, so the number of bits required for the addition processing is 2 bits. In the conventional configuration, when M = 32, that is, 32 = ²⁵ , which is the number of bits necessary for the addition processing, is obtained from the number of clocks of line data = 32, and an addition circuit that performs this 5-bit addition processing is used. Therefore, in the present invention, a 2-bit adder circuit is sufficient, and the circuit scale can be greatly reduced as compared with the conventional 5-bit adder circuit.
Further, since the adder circuit can be made small, the adder circuit can be operated at high speed, and the enable signal can be generated at high speed. Therefore, the reproduction clock signal for writing the client data can also be reproduced at high speed, and as a result, the demapping processing speed can be increased.

  More specifically, the phase of the enable signal according to the phase-locked loop processing in which the enable signal output from the clock recovery enable generation circuit and the enable signal output from the clock recovery enable generation circuit are compared. And a phase-locked loop circuit that oscillates a clock signal that is also used as a comparison target.

  According to this configuration, the clock recovery circuit restores the client data for the N clocks from the frame-format line data for the M clocks during the output period of the enable signal obtained by the clock recovery enable generation circuit. To regenerate the clock signal. Therefore, the reproduction clock signal is reproduced according to the enable signal generated at a high speed, so that the reproduction clock signal can also be reproduced at a high speed, and as a result, the demapping processing speed can be increased. For this reason, a high-speed operation with a throughput of 40 Gbps can be realized.

  According to the present invention, a clock recovery enable generation circuit that generates an enable signal that matches the ratio of client data to line data at a high speed, and a recovered clock signal for demapping according to the enable signal generated at a high speed Can be reproduced at a high speed with a simple circuit configuration, thereby providing a clock regeneration circuit capable of increasing the demapping processing speed.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

  FIG. 2 is a block diagram showing the configuration of the clock recovery enable generation circuit according to the embodiment of the present invention. The clock regeneration enable generation circuit 10 includes an adder circuit 11, a frequency division counter 12, and a comparator 13.

  FIG. 3 is a block diagram showing a configuration of the clock recovery circuit 20 that recovers the clock signal CK3 in accordance with the enable signal EN1 generated by the clock recovery enable generation circuit 10. As shown in FIG. The clock recovery circuit 20 includes a phase comparison circuit 22 serving as a phase-locked loop circuit, an LPF (low-pass filter) 23, and a VCO (voltage controlled oscillator) 24.

  The clock recovery circuit 20 has client data as specific data for N clocks included in line data as reception data for M clocks transmitted in frame format from the transmission side described in the “background art”. 1 is a circuit for regenerating a reproduction clock signal CK3 for writing 1 to a buffer memory (not shown).

  The clock regeneration enable generation circuit 10 enables the ratio (N / M) of the client data corresponding to the N clocks to the line data corresponding to the M clocks, which is necessary when the clock recovery circuit 20 regenerates the recovered clock signal CK3. It is a circuit for generating a signal EN. The clock recovery enable generation circuit 10 may be included in the clock recovery circuit 20.

  The addition circuit 11 outputs an addition result AD1 (initial value is 0) as a value after addition processing obtained by performing addition processing every time the clock signal CK extracted from the line data preamble is supplied. If AD1 is a negative value, the first addition value obtained by the first equation (MN) is added to the addition result AD1, and if the addition result AD1 is “0” or a positive value, The addition result AD1 is added with the second addition value obtained by the second equation {M × (PQ) ÷ PN}, and the addition result is output as a new addition result AD1. . However, P is an integer greater than or equal to 2, Q is an integer greater than or equal to 0, and is an integer which satisfy | fills Q <P <M.

  The frequency dividing counter 12 performs a counting operation only during a period when the addition result AD1 is a positive value, divides the clock signal CK by P by this counting operation, and outputs the count value CK1 at this time.

  The comparator 13 outputs the enable signal EN1 to the clock recovery circuit 20 when the addition result AD1 is a negative value or when the count value CK1 is Q or more.

  The operation of the clock regeneration enable generation circuit 10 having such a configuration will be described with reference to the timing chart shown in FIG. However, it is assumed that the timings of the times t1 to t33 coincide with the supply timing of the clock signal CK to the adder circuit 11.

  Similarly to the background art described above, M = 32, N = 29, P = 8, and Q = 1. In this case, the first addition value obtained by the first equation (M−N) is (32−29) = 3, and is obtained by the second equation {M × (PQ) ÷ PN. The second added value is {32 × (8-1) ÷ 8-29} = − 1.

  At time t1, it is assumed that the addition result AD1 = “0” and the enable signal EN1 is “L” in a non-output state. In this case, since the addition result AD1 = “0”, the second addition value = “− 1” is added to the “0” at time t2, and the addition result AD1 = “− 1”. At this time, in the frequency division counter 12, the count operation is performed only during a period in which the addition result AD1 is a positive value. Therefore, the count operation is not performed and the count value CK1 is not output. Accordingly, since only “−1” of the addition result AD1 is input to the comparator 13, the enable signal EN1 becomes “H” in the output state. This is because the comparator 13 outputs the enable signal EN1 when the addition result AD1 is a negative value or when the count value CK1 is Q or more.

  Since the addition result AD1 becomes “−1” at time t2, the first addition value = “3” is added to “−1” at time t3, and the addition result AD1 = “2”. At this time, since the count operation is performed in the frequency dividing counter 12 whose count value CK1 is “0”, the count value CK1 becomes “1”. Therefore, since the addition result AD1 “2” and the count value CK1 “1” are input to the comparator 13, the enable signal EN1 remains “H”.

  Since the addition result AD1 becomes “2” at time t3, the second addition value = “− 1” is added to “2” at time t4, and the addition result AD1 = “1”. At this time, since the count operation is performed in the frequency dividing counter 12 having the count value CK1 of “1”, the count value CK1 becomes “2”. Accordingly, since the addition result AD1 “1” and the count value CK1 “2” are input to the comparator 13, the enable signal EN1 remains “H”.

  Similarly, the process is repeated. For example, when the addition result AD1 = “2” at time t11, the second addition value = “− 1” is added to “2” at time t12. As a result, the addition result AD1 = "1". At this time, since the count operation is performed in the frequency dividing counter 12 having the count value CK1 of “7”, the count value CK1 becomes “0”. Accordingly, since the addition result AD1 “1” and the count value CK1 “0” are input to the comparator 13, the enable signal EN1 becomes “L”.

  Thereafter, the processing is repeated in the same manner, so that the enable signal EN1 is in an output state of “H” during the period of the clock signal of 29 clocks in total in the clock signal of 32 clocks as shown in the figure.

  The enable signal EN1 is input to the phase comparison circuit 22 of the clock recovery circuit 20. The phase comparison circuit 22 compares the phases of the enable signal EN1 and the fed back recovered clock signal CK3, and the difference obtained as a result of the comparison is obtained. A signal is output to the LPF 23.

  Further, a voltage signal obtained by filtering the difference signal by the LPF 23 is supplied to the VCO 24, and a reproduction clock signal CK3 having a frequency corresponding to the voltage supply is output. With this reproduced clock signal CK3, 29 clocks of client data out of 32 clocks of line data are written into the buffer memory. Further, the client data written in the buffer memory is read and restored by the oscillation clock signal of the oscillator synchronized with the reproduction clock signal CK3.

  However, since the enable signal EN1 is high-speed, if the phase locked loop circuit of the clock recovery circuit 20 does not properly follow up, a frequency division counter is connected to the previous stage of the phase comparison circuit 22, and this frequency division counter enables the enable signal. The frequency of EN1 is divided to lower the frequency, and the enable signal with the frequency lowered is input to the phase comparison circuit 22. Further, a multiplier circuit may be connected to the subsequent stage of the VCO 24, and the recovered clock signal CK3 may be multiplied by the reciprocal of the frequency division ratio of the frequency divider counter and output.

  As described above, in the clock recovery enable generation circuit 10 according to the present embodiment, the ratio of the N clock number of client data to the M clock number of line data (N) required when the clock recovery circuit 20 reproduces the recovered clock signal CK3. / M) enable signal EN1 is generated by using the adder circuit 11, the frequency dividing counter 12, and the comparator 13.

  That is, the addition circuit 11 performs an addition process for each one clock signal CK extracted from the line data preamble, and if the addition result AD1 is a negative value, the first equation (M− N) is added to the addition result AD1, and if AD1 is 0 or a positive value, the second mathematical expression {M × (PQ) ÷ PN} (provided that , P: an integer of 2 or more, Q: an integer of 0 or more, and the second addition value obtained by Q <P <M) is added to the addition result AD1, and the addition result AD1 after the addition is output.

  The frequency dividing counter 12 performs a counting operation only during a period when the addition result AD1 is a positive value. By this counting operation, the clock signal CK is divided by P, and the count value CK1 at this time is output. The comparator 13 outputs the enable signal EN1 when the addition result AD1 is a negative value or when the count value CK1 is Q or more.

  As described above, when M = 32, N = 29, P = 8, and Q = 1, the first addition value obtained by the first equation (MN) is (32-29) = 3. Thus, the second addition value obtained by the second mathematical formula {M × (PQ) ÷ PN} is {32 × (8-1) ÷ 8-29} = − 1.

  Therefore, in the addition circuit 11, since the addition process using the first addition value “3” or the second addition value “−1” is performed, the number of bits necessary for the addition process is 2 bits. Compared to 5 bits, the circuit scale can be greatly reduced. Further, since the adder circuit 11 can be made small, the adder circuit 11 can be operated at high speed, and the enable signal EN1 can be generated at high speed with a simple circuit configuration. Therefore, the reproduction clock signal CK3 for writing client data can also be reproduced at high speed, and as a result, the demapping processing speed can be increased. In addition, high-speed operation with a throughput of 40 Gbps can be realized.

  The clock recovery circuit 20 is a clock for restoring client data for N clocks from line data in the frame format for M clocks during the output period of the enable signal EN1 obtained by the clock recovery enable generation circuit 10. Play the signal. Therefore, since the reproduction clock signal CK3 is reproduced according to the enable signal EN1 generated at high speed, the reproduction clock signal CK3 can also be reproduced at high speed, and as a result, the processing speed of demapping can be increased. For this reason, a high-speed operation with a throughput of 40 Gbps can be realized.

  The clock recovery enable generation circuit and the clock recovery circuit according to the present invention can be used to restore client data by demapping from line data transmitted in a frame format in an optical transmission system employing a time division multiplexing method. The present invention can be applied to a case where a clock signal for mapping is reproduced from line data.

It is a timing chart for demonstrating operation | movement of the conventional clock reproduction | regeneration enable production | generation process. 1 is a block diagram illustrating a configuration of a clock recovery enable generation circuit according to an embodiment of the present invention. FIG. It is a block diagram which shows the structure of the clock reproduction circuit using the enable signal of the enable generation circuit for clock reproduction | regeneration of the said embodiment. 6 is a timing chart for explaining an operation of an enable signal generation process by the clock regeneration enable generation circuit of the embodiment.

Explanation of symbols

10: Clock regeneration enable generation circuit 11: Addition circuit 12: Frequency division counter 13: Comparator 22: Phase comparison circuit 23: LPF
24: VCO
CK: Clock signal CK1: Count value AD1: Addition result EN1: Enable signal CK3: Regenerated clock signal

Claims (2)

In a clock regeneration enable generation circuit that generates an enable signal for a period of N clocks (N: positive integer, where N <M) during an output period of M clocks (M: positive integer).
Each time one clock of the clock signal is supplied, the addition process is performed one by one. If the value after the addition process is a negative value, the first addition value obtained by the first equation (M−N) is If the value after the addition process is 0 or a positive value, the second expression {M × (PQ) ÷ PN} (where P: 2 An addition circuit that adds the second addition value obtained by Q <P <M) with the integers above, Q: 0 or more to the value after the addition processing, and outputs the addition result;
A frequency dividing counter that performs a counting operation only during a period when the addition result of the adding circuit is a positive value, divides the clock signal by P by this counting operation, and outputs a count value at this time;
A comparator that outputs an enable signal when the addition result of the adder circuit is a negative value or when the count value of the frequency dividing counter is Q or more;
A clock recovery enable generation circuit comprising: The clock recovery enable generation circuit according to claim 1,
A phase-locked loop circuit that oscillates a clock signal that is also used as a phase comparison target with the enable signal in accordance with a phase-locked loop process that uses the enable signal output from the clock regeneration enable generation circuit as a phase comparison target;
A clock recovery circuit comprising:

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