JP5086014B2 - Data recovery method and data recovery circuit - Google Patents

Description

  The present invention relates to a data recovery method and a data recovery circuit for restoring serially transferred data.

  In recent years, USB (Universal Serial Bus), Serial ATA (Advanced Technology Attachment), IEEE1394, 1G / 10G Ethernet (registered trademark), InfiniBand to meet the demands of high-capacity and high-speed data transmission between devices, boards, and chips Various high-speed interface standards such as RapidIO, Fiber Channel, and PCI Express have been proposed and put into practical use. However, the trend toward higher speed and higher capacity is expected to increase in the future.

  Many of these interface standards employ a serial transfer method, and data is transmitted at a predetermined frequency. The transmitted data is superimposed with a clock of that frequency (embedded clock), and the data receiving unit detects this clock from the received data and restores the received data based on the detected clock signal.

  A circuit that performs these restoration operations is called a clock data recovery (hereinafter referred to simply as “CDR”) circuit. In a conventional CDR circuit, a PLL (Phase Locked Loop) circuit is generally used, and an oscillation signal (clock) of a VCO (Voltage Controlled Oscillator) included in the PLL is controlled to be synchronized with the phase of received data and used as a reproduction clock. It is done.

  The received data is accurately restored by latching the received data on the basis of the reproduction clock. However, when the data transfer speed is increased and, for example, an order exceeding Gbps, the oscillation frequency of the VCO also exceeds the GHz order. Therefore, in a CDR circuit incorporating such a VCO, the chip size increases and the power consumption increases. Negative factors such as cost and cost increase will increase.

  In addition, since the wiring delay cannot be ignored due to the increase in the data transfer speed, it is necessary to pay sufficient attention to the element arrangement and the wiring layout, and the design becomes more difficult. In addition, since the wiring delay greatly depends on the device characteristics to be used, it becomes necessary to redesign the layout for each process (or until the circuit is redesigned), which reduces the circuit reusability and development. The period is increased.

  As a solution to such a problem, an oversampling CDR circuit has been proposed (see, for example, Non-Patent Document 1).

  FIG. 27 is a configuration diagram of a conventional CDR circuit. As shown in FIG. 27, in the CDR circuit, the multiphase clock generation unit 900 is configured by a PLL, a DLL (Delayed Locked Loop), or the like, and has a phase difference of equal intervals shifted from the reference clock (RefCLK) by a predetermined phase. Generate a multiphase clock.

  A flip-flop (hereinafter referred to as “F / F”) circuit 901 inputs input data (Data) in common to the data terminals, and receives each clock (CLK1 to CLKN) of the multiphase clock supplied from the multiphase clock generation unit 900. ) Are input to the clock terminals, and input data is captured at the rising edge (or falling edge) of each clock. That is, the data output from the F / F circuit 901 is obtained by sampling the input data with a clock whose phase is gradually shifted.

  A digital PLL (hereinafter referred to as “DPLL”) 902 detects an inversion timing at which logic is inverted from a bit string supplied from the F / F circuit 901, and a clock having a phase synchronized with the timing is included in the multiphase clock. And restored as a recovered clock (RecCLK).

  Further, the DPLL 902 selects and outputs data taken in with a clock having a predetermined phase difference (for example, opposite phase) from the reproduction clock (RecCLK) as reproduction data (RecData). When selecting the reproduction clock (RecCLK), the DPLL 902 detects the data inversion timing by smoothing it with a filter.

  A subsequent signal processing unit (not shown) operates based on the reproduction clock (RecCLK). Since such a circuit configuration can be configured by a digital circuit other than the multiphase clock generation unit 900, it is relatively easy to implement. However, if the phase difference between the clocks of the multiphase clock generated by the multiphase clock generation unit 900 is not equal, the CDR circuit may malfunction.

  FIG. 28 is a diagram illustrating an example of a problem when the phase differences of the multiphase clocks are not equal. In FIG. 28, description will be made assuming that the multiphase clock output from the multiphase clock generation unit 900 has four phases.

  First, it is assumed that the phase of CLK2 is delayed by Δ from the ideal state, CLK2 is selected as the reproduction clock (RecCLK), and the signal processing unit processes each data in synchronization with CLK2.

  If CLK1 is selected as the reproduction clock (RecCLK) at time Tsw, the period of the reproduction clock is further shortened by Δ in addition to the original phase difference (T ′), and the time for setting up the F / F in the signal processing unit (T ′) Tsu ′) cannot be secured sufficiently, and the CDR circuit may malfunction.

  This is because, for example, even if the output phase of the multiphase clock generator 900 is designed so that the phase differences of the clocks of the multiphase clock are equally spaced, the clocks up to the output end of the recovered clock (RecCLK) The CDR circuit may malfunction due to the influence of skew (for example, due to wiring or a load). Furthermore, this skew becomes more prominent as the data transfer speed increases. Therefore, it becomes necessary to adjust the delay amount of the multiphase clock in each part, and it is not easy to realize, so that the above-mentioned problems have not been solved.

  In addition, there is a multiphase clock generator 900 that performs phase adjustment using a phase interpolator (see, for example, Patent Document 1).

  However, if a circuit such as a phase interpolator is provided, it will be possible to output multiphase clocks with equally spaced phase differences, but this will increase the number of devices and ignore wiring delays associated with higher speeds. Can not.

  As a method of avoiding this wiring delay, a method of matching the phases of the multiphase clocks at the respective inputs can be considered. However, this method realizes an oversampling CDR circuit that operates at an oversampling frequency higher than the frequency of the clock included in the transfer data (in the example of FIG. 28, four times the frequency of the clock included in the transfer data). Have the same difficulty.

  Therefore, in a device using a conventional CDR circuit using an analog PLL or an oversampling CDR circuit that recovers a clock from input data and performs signal processing based on the recovered clock, the transfer speed is increased. As a result, the difficulty of designing the CDR portion increases, so the development period increases and its realization becomes increasingly difficult.

  As a CDR circuit for solving these problems, data serially transferred in synchronization with a clock having a frequency f1 is oversampled by a multiphase clock generated by shifting the clock having a frequency f2 by a predetermined phase and sampled data. Even if the data transfer rate is high, the sampling unit for acquiring the data and the data recovery unit for detecting the f1 / f2 bits on the average from the acquired sampling data and recovering the received data are provided. In addition, since data recovery processing can be performed at a clock frequency that is a fraction of the data transfer rate, it can easily cope with system speedup, as well as jitter of transferred data and polyphase used during oversampling. Some were less susceptible to non-uniform clock phase spacing (examples) If, see Patent Document 2).

In addition, by arranging a waveform equalizer that performs digital sampling after oversampling the binarized received signal in the data recovery circuit described above, intersymbol interference caused by transmission path characteristics, etc. with a simple configuration In some cases, the deterministic jitter is reduced (see, for example, Patent Document 3).
B. Kim et. al. "A 30-MHz Hybrid Analog / Digtal Clock Recovery Circuit in 2-um CMOS", IEEE JSSC, December 1990, pp1385-1394 JP 2002-190724 A JP 2005-192192 A JP 2006-166229 A

  In general, the CDR circuit detects the phase information of the clock from the input data by the PLL, determines the sampling point of the input data based on the phase information, and reproduces the data by sampling the data at the sampling point. ing.

  The PLL functions as a low-pass filter and outputs a phase in which the high frequency component of the phase of the input data is attenuated. For this reason, when the frequency component of the jitter of the input data is sufficiently lower than the loop band of the PLL, the PLL can follow the jitter.

  In this case, since the same phase as the phase including the jitter of the input data is output from the PLL, it is possible to cancel the influence of the jitter of the input data by performing data recovery according to the phase information, and the accurate sampling Data recovery can be performed at points.

  Therefore, as the PLL faithfully follows the jitter of the input data, the probability of a data recovery error can be reduced.

  In order to improve the follow-up characteristic of the PLL, it is necessary to set a wide loop band of the PLL. However, since the PLL performs feedback control, the influence of the processing delay time and phase delay of the circuits constituting the PLL, and the influence of the delay due to the 0th-order hold caused by performing the phase detection for each bit of the input data. If the loop bandwidth is simply widened, the control system becomes unstable and normal operation cannot be performed.

  For this reason, the PLL loop band cannot be increased indefinitely, and the loop band of a general PLL used in a CDR circuit is about several tens of MHz at most. Jitter of input data is roughly classified into random jitter (Rj) and deterministic jitter (Dj). Dj is caused by intersymbol interference of transfer data, crosstalk, duty distortion, and the like, and has a large component up to a very high frequency near the bit rate of transfer data.

  For this reason, when serial data transfer is performed at a bit rate of several Gbps, frequency components up to several GHz are included, and jitter is generated in a frequency region higher than the general PLL band described above. It will be.

  Since the influence of intersymbol interference depends on the transferred data pattern and the characteristics of the transmission path, it is possible to reduce the influence by processing using an equalizer. However, generally, when a CDR circuit is configured with a high-speed and high-performance equalizer, the circuit scale increases, the chip area of the LSI increases, and the power consumption increases.

  In addition, jitter due to the influence of switching noise, jitter caused by non-uniformity of the phase interval of the multiphase clock during oversampling using the multiphase clock, and the like have higher frequency components than the loop band of the DPLL. These jitters do not depend on the data pattern at all, and these jitters cannot be reduced with a linear equalizer that is usually used.

  An object of the present invention is to provide a data recovery method and a data recovery circuit capable of reducing the influence of jitter of input data with a simple configuration and accurately restoring data.

The information processing apparatus according to the present invention is a data recovery method for detecting phase information of input data and sampling the input data based on the phase information, wherein the phase of the input data and the detected phase information represent The phase information is corrected so that the absolute value of the phase difference is clipped to the specified value for phase correction when the absolute value of the phase difference exceeds the specified value for phase correction. And a step of correcting the edge position of the input data so that the absolute value of the phase difference becomes small when the absolute value of the phase difference exceeds a specified value for edge correction .

  The present invention can provide a data recovery method and a data recovery circuit that can reduce the influence of jitter of input data with a simple configuration and can accurately restore data.

  Embodiments of a data recovery method of the present invention and a data recovery circuit of the present invention using the data recovery method will be described below.

(First embodiment)
FIG. 1 is a schematic configuration diagram showing a physical layer unit of a serial transfer unit to which the first embodiment of the data recovery circuit of the present invention is applied. The physical layer unit 100 illustrated in FIG. 1 includes a transmission unit 101 that transmits data and a reception unit 102 that receives data.

  When data is transmitted / received using this serial transfer unit, the physical layer unit 120 having the same function as the physical layer unit 100 and having one set of transmission unit 122 and reception unit 121 is connected to the transmission paths 106 and 107. And arranged to face each other.

  The physical layer unit 100 includes a PLL 113 that generates a clock having a frequency fa from the reference clock RefCLK1, and the physical layer unit 120 includes a PLL 123 that generates a clock having a frequency fb from the reference clock RefCLK2. The physical layer units 100 and 120 operate based on clocks generated by the PLLs 113 and 123, respectively, having frequencies fa and fb, respectively. In the following description, each set of the transmission unit and the reception unit of the physical layer units 100 and 120 is referred to as a “port”.

  Serial transfer of data is performed point-to-point between ports. The transmission paths 106 and 107 in the present embodiment constitute a full-duplex line that can be performed simultaneously by separate transmission paths for transmission and reception, but are not necessarily a full-duplex line. The data recovery circuit of the present invention can be applied even in the case of a double line. The transmission paths 106 and 107 are each configured by two lines, but may be configured by radio.

  The transmission unit 101 includes an encoder unit 103 that performs encoding according to a predetermined conversion rule for transmission data Dtx supplied from an upper layer, a serializer 104 that serially converts data encoded by the encoder unit 103, And a transmission output unit 105 that transmits the serially converted data to the transmission path 106.

  Data on the transmission path 106 is transmitted as a differential signal. The encoder unit 103 performs 8B / 10B conversion on the transmission data Dtx. The 8B / 10B conversion is a conversion from 8-bit data to 10-bit data (hereinafter referred to as “symbol data”), and is a 1-bit special code for control (called a K code (or K character)). DtxK) is added to the 8-bit data.

  The PLL 113 divides the transfer clock BCLK defined in each standard and the transfer clock BCLK by 10 based on the supplied reference clock RefCLK1 (when the encoder unit 103 performs 8B / 10B conversion). A clock PCLK for internal operation is generated. For example, when data transfer is performed at 2.5 Gbps, the PLL 113 generates a transfer clock BCLK of 2.5 GHz and a clock PCLK of 250 MHz.

  The PLL 113 operates each unit by supplying a clock PCLK to the encoder unit 103 and supplying the clock PCLK and the transfer clock BCLK to the serializer 104. In addition, data transfer between the physical layer unit 100 and the upper layer is performed in synchronization with the clock PCLK.

  The reception unit 102 includes a reception input unit 108 that binarizes the differential signal transmitted through the transmission path 107, a DEQ 115 that performs digital processing on the data binarized by the reception input unit 108, and a reception input. A data recovery unit 109 that restores the data binarized by the unit 108, a deserializer 110 that converts the restored data into 10-bit symbol data in parallel, and an error that absorbs the frequency difference between the clocks on the transmission side and the reception side. A stick buffer 111 and a decoder 112 that performs 10B / 8B conversion of 10-bit symbol data into 8-bit data are provided.

  Also in the physical layer unit 120 facing the physical layer unit 100, the transmission unit 122 transmits data in synchronization with the transfer clock having the frequency f1 generated by the PLL 123 based on the supplied reference clock RefCLK2.

  The elastic buffer 111 absorbs the frequency difference by adding or deleting a special code, for example. The allowable value of the frequency difference is determined for each interface standard. In this embodiment, the elastic buffer 111 is provided in the preceding stage of the decoder 112, but may be provided in the subsequent stage.

  In the present embodiment, the data recovery unit 109 and the deserializer 110 of the receiving unit 102 are described as constituting the data recovery circuit of the present invention, but the configuration of the data recovery circuit of the present invention is not limited. In addition, other configurations and functions of the physical layer unit 100 can be arbitrarily changed in combination with the first embodiment of the data recovery circuit.

  In addition, the physical layer unit 100 according to the present embodiment generates the multiphase clock supplied to the data recovery unit 109 or the clock PCLK supplied to the elastic buffer 111 or the like by the PLL 113, but the clock PCLK or transfer clock generated by the PLL 113 is also used. BCLK is also supplied to the transmission unit 101 such as the serializer 104 and the encoder unit 103, and the PLL 113 is shared. This is because the opposing physical layer units 100 and 120 are operated by clocks generated from independent reference clocks RefCLK1 and RefCLK2, respectively.

  FIG. 2 is a block diagram showing a first embodiment of the data recovery circuit of the present invention. As shown in FIG. 2, the data recovery circuit of the first embodiment includes an oversampling unit 1, a multiphase clock generation unit 2, and a symbol data restoration unit 3.

  Here, a part of the oversampling unit 1 and the symbol data restoration unit 3 constitutes the data recovery unit 109 shown in FIG. 1, and another part of the symbol data restoration unit 3 constitutes the deserializer 110 shown in FIG. doing.

  Further, the multiphase clock generator 2 constitutes a part of the PLL 113 shown in FIG. The deserializer 110 is not necessarily provided in the data recovery circuit, and may be provided separately.

  The multi-phase clock generation unit 2 shifts a clock having a predetermined frequency generated from the reference clock RefCLK by a predetermined phase, and generates a multi-phase clock having substantially equal phase differences. In the present embodiment, the multiphase clock generator 2 has multiphase clocks CK <b> 0 to CK <b> 15 having a frequency f <b> 2 that is about ½ of the transfer clock BCLK for which the cycle UI is defined and a phase difference of, for example, 1/8 UI. Generate.

  For example, when the data transfer rate is 2.5 Gbps (UI is 400 ps), the multi-phase clock generator 2 generates 16 clocks with a cycle of 800 ps (frequency is 1.25 GHz) and a phase difference of 50 ps each. Generate.

  Note that the frequency f2 of the multiphase clock does not need to be ½ of the frequency of the transfer clock BCLK, may be ¼ of the frequency of the transfer clock BCLK, or may be the same as the frequency of the transfer clock BCLK. For example, the multiphase clock generation unit 2 may generate 32 clocks having a frequency f2 of 1/4 of the frequency of the transfer clock BCLK as a multiphase clock.

  Furthermore, the phase difference of the multiphase clocks generated by the multiphase clock generation unit 2 need not be limited to 1/8 UI of the cycle UI of the transfer clock BCLK. In addition, the data recovery circuit of the present embodiment is configured to include the multiphase clock generation unit 2, but the multiphase clock generation unit 2 may be configured separately from the data recovery circuit.

  The oversampling unit 1 takes in the received data Data using the multiphase clocks CK0 to CK15 supplied from the multiphase clock generation unit 2 and outputs the oversampled data OVSD to the symbol data restoration unit 3.

  The symbol data restoring unit 3 restores 10-bit symbol data SYM from the oversampled data OVSD and generates a symbol clock SYMCLK, and has a data recovery function and a deserializer function. Note that the symbol data restoration unit 3 operates with one of the multiphase clocks (CK0 is illustrated in the figure).

  As described above, if a multiphase clock set to a frequency f2 lower than the frequency f1 of the transfer clock BCLK is used for the data recovery circuit, the oscillation frequency of the multiphase clock generation unit 2 can be lowered, thereby increasing the speed. Easy to handle.

  Next, the detail of each part is demonstrated.

  The oversampling unit 1 and an F / F circuit 4 composed of 16 F / Fs (F / F0 to F / F15) and parallel that outputs input data in synchronization with one clock (for example, CK0). And a conversion unit 5.

  In F / F0 to F / F15, the reception data Data is commonly input to the data terminals. F / F0 to F / F15 fetch the reception data Data at the timing when the multiphase clocks CK0 to CK15 rise, Q0 to Q15 are output respectively.

  The parallelization unit 5 has, for example, a two-stage F / F, and after Q0 to Q15 are once latched into outputs Q0 to Q7 and outputs Q8 to Q15, they are combined and output Q0 to Q15. Is output, for example, oversampled data OVSD synchronized with one clock of the multiphase clock (here, CK0).

  FIG. 3 is a diagram illustrating an example of a signal waveform of each main signal of the oversampling unit 1. 3, (a) is a waveform example of received data Data, (b) is a data transfer clock (which actually does not exist in the oversampling unit 1, but is described for convenience of explanation), (c−). 0) to (c-15) are multiphase clocks CK0 to CK15, and (d-0) to (d-15) are taken into F / F0 to F / F15 by the multiphase clock, and F / F0 to F Data Q0 to Q15, (e-0), and (e-1) respectively output from / F15 are data Q0 to Q5, data Q8 to Q15, and (f) that are once taken in by the parallelizing unit 5. The oversampled data OVSD output from the conversion unit 5 is shown.

  The cycles of the multiphase clocks CK0 to CK15 shown in (c-0) to (c-15) are set to twice (2UI) the cycle (UI) of the data transfer clock shown in (b). The phases of the clocks CK0 to CK15 are shifted so that the phase differences between adjacent clocks are equally spaced.

  The black circles attached to the received data Data shown in (a) are the sampling points of the multiphase clocks CK0 to CK15. The outputs Q0 to Q15 of the F / F0 to F / F15 captured by the multiphase clock are as follows. , (D-0) to (d-15). In FIG. 3, the left side of the bit string is LSB, which represents a sample point that is fast in time.

  The parallelizing unit 5 once fetches Q0 to Q7 at the clock CK0, outputs QQ [0: 7] as shown in (e-0), fetches Q8 to Q15 at the clock CK8, and (e-1) QQ [8:15] is output as shown in FIG.

  Then, the parallelization unit 5 takes in QQ [0: 7] and QQ [8:15] at the next clock CK0 and synchronizes them in parallel, and, as shown in (f), oversampled data OVSD [0:15]. Is output.

  As described above, the parallelization unit 5 captures Q0 to Q7 at the clock CK0, captures Q8 to Q15 at the clock CK8, and then captures Q0 to Q15 at the next clock CK0. This is because the setup time of the parallelizing unit 5 for Q15 and Q14 is insufficient and the data cannot be normally captured.

  Here, in the present embodiment, the data acquisition in the parallelization unit 5 is set to two stages as described above, but the number of stages may be further increased so that the data can be acquired more stably.

  In general, the reception data Data rises or falls at a timing that is so-called jitter that fluctuates randomly or due to a variety of factors as indicated by the hatched portion (a) in FIG.

  For this reason, sampling data near the timing at which data transitions may fluctuate and cannot be accurately restored. However, according to the present embodiment, such a problem can also be solved as shown by being surrounded by a broken line in FIG.

  Next, the configuration and operation of the symbol data restoring unit 3 that restores received data from oversampled data OVSD will be described.

  The symbol data restoration unit 3 includes a data selection unit 6, a selection signal generation unit 7, a deserializer 8, and a comma detection unit 9. The symbol data restoration unit 3 restores 10-bit symbol data SYM from the oversampled data OVSD and has a phase of An adjusted symbol clock SYMCLK is generated.

  In the present embodiment, the oversampled data OVSD is 16-bit data in which 2 bits of transfer data are sampled with an 8-phase clock. Therefore, the symbol data restoration unit 3 may select and output data (bits) taken in with a clock having a predetermined phase from the 16-bit oversampling data OVSD.

  However, the transfer clock included in the data transmitted from the transmitting unit 122 of the opposing physical layer unit 120 and the multiphase clocks (clocks CK0 to CK15) used for sampling in the receiving unit 102 of the physical layer unit 100 have exactly the same frequency. If the frequency of the multiphase clock is a natural fraction of the frequency of the transfer clock, the phase at which the symbol data restoration unit 3 captures the oversampling data OVSD may remain fixed.

  However, since the multi-phase clock and the transfer clock usually have a frequency difference within a certain range, the symbol data restoration unit 3 gradually shifts the capture phase. Therefore, it is sometimes necessary to selectively output one or three pieces of data.

  For example, if the frequency difference between the multiphase clock and the transfer clock is 0.1% (1000 ppm), a shift of 1 bit occurs with respect to 1000 bits of transfer data, and the clock CK0 used for oversampling has 500 cycles. Once, one or three pieces of data are output.

  The selection signal generation unit 7 constitutes a phase information detection circuit according to the present invention, and generates oversample data MOVSD in which the edge position is corrected from oversample data OVSD, and a selection signal Sel indicating the bit capture phase of MOVSD.

  The data selection unit 6 performs 1 to 3 restoration data (d0, d1) from the oversampled data MOVSD in which the edge position output from the selection signal generation unit 7 is corrected according to the selection signal Sel output from the selection signal generation unit 7. , D2) are selectively output. Further, the data selection unit 6 also outputs status signals S0 and S1 indicating the valid portion of the restored data.

  The comma detection unit 9 detects a comma code called a comma as a special code inserted into the transfer data at a predetermined interval, and outputs a comma detection signal Det.

  Based on the comma detection signal Det, the deserializer 8 performs parallel conversion of 1 to 3 restoration data (d0, d1, d2) supplied from the data selection unit 6 into 10-bit symbol data SYM. The deserializer 8 also generates a symbol clock SYMCLK.

  FIG. 4 is a diagram illustrating a configuration example of the selection signal generation unit 7. 4, the selection signal generation unit 7 includes both edge detection unit 20, edge correction unit 560, DPLL 566, edge correction data generation unit 564, and offset addition unit 567, and is supplied from the multiphase clock generation unit 2. It is configured to operate with reference to the clock CK0.

  Both edge detectors 20 detect both rising and falling edges from the bit string of oversampled data OVSD, and output edge data RxEdge indicating the edge positions.

  Specifically, the both-edge detection unit 20 performs exclusive logic between the oversampled data OVSD [0:15] and the data dOVSD [0:15] obtained by delaying the oversampled data OVSD from the phase difference of the multiphase clock. Calculate the sum.

  Note that dOVSD [0:15] is obtained by dOVSD [0:15] = {pOVSD [15], OVSD [0:14]} if OVSD [15] one clock before is expressed as pOVSD [15]. Can do.

  The edge correction unit 560 corrects the edge position of the edge data RxEdge output from both edge detection units 20 based on the phase represented by the phase data (phase information) output from the digital VCO 563 described later, and the edge position is corrected. The edge data MEDge is output. The edge correction unit 560 will be described in detail later.

  The edge correction data generation unit 564 receives the oversampling data OVSD before the edge position correction and the edge data MEDge with the corrected edge position, and the edge correction data generation unit 564 receives the overcorrected edge position. Sampling data MOVSD is output.

  The DPLL 566 includes a comparison unit 21, a loop filter 562, and a digital VCO 563, and outputs 6-bit phase data St representing a phase synchronized with the phase of the input edge data RxEdge.

  The comparison unit 21 compares the phase of the edge of the edge data RxEdge with the phase data St output from the digital VCO 563, and compares the phase difference data PDDat and the 6-bit four sets of phase difference data PDDatA, PDDatB, PDDatC, and PDDatD of each edge. Output.

  The configuration of the comparison unit 21 is shown in FIG. 5, the comparison unit 21 includes first phase difference detection units 530a and 530c, second phase difference detection units 530b and 530d, clip circuits 531a to 531d, and an addition circuit 532.

  The first phase difference detection unit 530a is the 0th to 3rd bits of the oversampling data, the second phase difference detection unit 530b is the 4th to 7th bits of the oversampling data, and the first phase difference detection unit 530c is The 8th to 11th bits of the oversampling data and the second phase difference detection unit 530d are provided for the 12th to 15th bits of the oversampling data, respectively.

  Since the pulse width of the signal received by the comparison unit 21 may be narrowed due to various jitters, there may be a plurality of data edges within a time corresponding to 1 UI. Even in such a case, the comparison unit 21 is configured as described above so that each of the phase difference detection units 530a to 530d does not detect two or more data edges.

  In the present embodiment, it is assumed that the shortest pulse width of the received signal at the time of oversampling is 1/2 UI or more, and edge detection is performed for each 1/2 UI. When there is a possibility that the pulse width of the received signal of the system actually used may be further narrowed, it can be dealt with by further dividing the phase detection unit.

  Each of the phase difference detection units 530a to 530d is set to 0 when no edge exists in the 4-bit portion of the input edge data RxEdge, and when there is an edge, the first phase difference detection units 530a and 530c perform FIG. The second phase difference detectors 530b and 530d output signals representing the phase difference from the phase data St output from the digital VCO 563 as shown in FIG.

  Each of the clipping circuits 531a to 531d clips the input data with the prescribed value for phase correction. For example, when clipping at ± 8, each of the clipping circuits 531a to 531d outputs the input data as it is when the value of the input data is -8 or more and 8 or less, outputs 8 when it exceeds 8, and when it is less than -8 Output -8. The same applies to each of the clipping circuits 531a to 531d when clipping input data with other values.

  The adder circuit 532 adds the outputs of the clip circuits 531a to 531d and outputs the result as phase difference data PDDat.

  With the above configuration, the phase difference data PDDat obtained by adding the phase difference data (PDDatA, PDDatB, PDDatC, PDDatD) of each 4-bit part of the edge data RxEdge and the phase difference data of each 4-bit part of the edge data RxEdge after clipping. Is output from the comparison unit 21.

  In FIG. 4, the phase difference data PDDat output from the comparison unit 21 is input to the loop filter 562. The loop filter 562 is a filter that determines the loop characteristics of the DPLL 566, and outputs the data VCOIn obtained by smoothing the phase difference data PDDat output from the comparison unit 21 to the digital VCO 563. By changing the characteristics of the loop filter 562, the characteristics of the DPLL 566 can be changed.

  FIG. 8 shows an example of the loop filter 562. In FIG. 8, the loop filter 562 includes multipliers 570 and 571, adders 572 and 575, a limit circuit 573, and an F / F 574.

  Multipliers 570 and 571 are multipliers having fixed magnifications a and b, respectively, and multiply the input phase difference data PDDat by a fixed number. By adopting a configuration in which the magnifications a and b of the multipliers 570 and 571 can be set by a register (not shown), the characteristics of the DPLL 566 can be changed.

  Further, the adder 572, the limit circuit 573, and the F / F 574 constitute an integrator. The limit circuit 573 is a circuit that limits the output to the maximum value or the minimum value when an overflow or underflow occurs in the adder 572.

  The digital VCO 563 corresponds to an analog PLL VCO and outputs phase data St. In this embodiment, it is assumed that the digital VCO 563 outputs data with 6 bits (64 values). In this case, 1 LSB of the phase data St output from the digital VCO 563 corresponds to a phase of 1/64 cycle (1/64 UI).

  FIG. 9 shows a configuration example of the digital VCO 563. In FIG. 9, the digital VCO 563 includes an adder 580 and an F / F 581. The adder 580 constitutes an integrator by adding the input data VCOIn and the feedback data from the F / F 581. The digital VCO 563 outputs the upper 6 bits among the bits held by the F / F 581 as the phase data St of the digital VCO 563.

  With this configuration, the digital VCO 563 integrates the data obtained by smoothing the phase difference data PDDat output from the comparison unit 21 by the loop filter 562. Therefore, the phase data St output from the digital VCO 563 represents a phase. .

  Here, as the number of bits of the phase data St is increased, the phase represented by one bit of the phase data St is reduced, and the accuracy of the phase that can be expressed by the digital VCO 563 with the phase data St is increased.

  The phase data St output from the digital VCO 563 is returned to the comparison unit 21, and feedback control is performed by the comparison unit 21, the loop filter 562, and the digital VCO 563. For this reason, the phase data St output from the DPLL 566 follows the phase of the edge data RxEdge.

  In FIG. 4, the edge correction unit 560 includes the edge data RxEdge output from both edge detection units 20 and the four phase difference data PDDatA, PDDatB, PDDatC, and PDDatD output from the comparison unit 21 in the DPLL 566, from the DPLL 566. Edge data MEDage obtained by correcting the edge position of the edge data RxEdge with reference to the output phase data St is output.

  Here, the processing performed by the edge correction unit 560 will be described with reference to FIG. In FIG. 10, the horizontal axis indicates the phase, and the edge position obtained from the phase data St output from the DPLL 566 is at the position indicated by A in FIG.

  The edge correction unit 560, when the absolute value of the phase difference between the edge position obtained from the phase data St output from the DPLL 566 and the edge position of the edge data RxEdge is less than or equal to the edge correction specified value, the edge data RxEdge. However, if this absolute value exceeds the edge correction specified value, the phase of the edge data RxEdge is corrected and output so that this absolute value becomes the edge correction specified value.

  In FIG. 10, when the edge position of the edge data RxEdge is P1 or P2, the edge data RxEdge is set to the retard side correction value on the retard side where the absolute value of the phase difference between the edge positions becomes the prescribed value for edge correction. The edge position of is corrected. When the edge position of the edge data RxEdge is P3 or P4, the edge position of the edge data RxEdge is not corrected and the edge data RxEdge is output as it is. In addition, when the edge position of the edge data RxEdge is P5 or P6, the edge of the edge data RxEdge is set to the advance side correction value on the advance side where the absolute value of the phase difference between the edge positions becomes the specified value for edge correction. The position is corrected.

  As described above, by correcting the edge position of the edge data RxEdge, the edge correction unit 560 can remove a part of the influence of the jitter component having a large component at a high frequency, and the corrected edge data MEDge can reduce the influence of jitter with respect to edge data RxEdge before edge correction.

  FIG. 11 shows a configuration example of the edge correction unit 560. In FIG. 11, the edge correction unit 560 includes shift amount generation units 600 a to 600 d, shift calculation units 601 a to 601 d, and an F / F 602.

  The shift amount generation units 600a to 600d obtain edge correction amounts based on the phase difference data PDDatA, PDDatB, PDDatC, and PDDatD output from the comparison unit 21, and output them as shift data.

  The shift calculation units 601a to 601d shift each 4-bit portion of the edge data RxEdge according to the shift data output from the corresponding shift amount generation units 600a to 600d, respectively, and shift each 4-bit portion of the edge data RxEdge. Output as data ShDatA, ShDatB, ShDatC, ShDatD.

  Of the data ShDatA, ShDatB, ShDatC, ShDatD output from the shift calculation units 601a to 601d, the upper 4 bits of the data ShDatD output from the shift calculation unit 601d are input to the F / F 602, and from the F / F 602, ShDatD The 4-bit data dShDatD delayed by one clock is output.

  The OR circuit 603 generates and outputs edge data MEDge subjected to edge correction from the ShDatA, ShDatB, ShDatC, ShDatD, and dShDatD.

The OR circuit 603 performs the following calculation.
Medge [15: 0] = {
(ShDatD [3] | ShDatC [7]), (ShDatD [2] | ShDatC [6]), (ShDatD [1] | ShDatC [5]),
(ShDatD [0] | ShDatC [4]), (ShDatC [3] | ShDatB [7]), (ShDatC [2] | ShDatB [6]),
(ShDatC [1] | ShDatB [5]), (ShDatC [0] | ShDatB [4]), (ShDatB [3] | ShDatA [7]),
(ShDatB [2] | ShDatA [6]), (ShDatB [1] | ShDatA [5]), (ShDatB [0] | ShDatA [4]),
(ShDatA [3] | dShDatD [3]), (ShDatA [2] | dShDatD [2]), (ShDatA [1] | dShDatD [1]),
(ShDatA [0] | dShDatD [0])}

  FIG. 12 shows an example of the operation of the edge correction unit 560. In FIG. 12, (a) is edge data RxEdge input to the edge correction unit 560, and (b) is data that does not actually exist but converts the phase data St output from the digital VCO 563 into equivalent to oversampling data. This is shown for illustrative purposes.

  Further, (c-1) to (c-4) are output data ShDatA, ShDatB, ShDatC, and ShDatD of the shift calculation units 601a to 601d, and (c-5) is output data dShDatD of the F / F 602. (D) is edge data MEDge output from the edge correction unit 560.

  As can be seen from FIG. 12, the edge correction unit 560 outputs the edge data MEDge that is entirely shifted by 2 bits with respect to the edge position of the edge data RxEdge even when the edge correction is not performed.

  For this reason, the data selection unit 6 in the subsequent stage is configured to sample a position obtained by adding an amount equivalent to 2 bits to the output value of the DPLL 566 that follows the phase of the edge data RxEdge.

  The edge correction data generation unit 564 receives edge data MEDedge after edge correction and oversampling data OVSD, and the edge correction data generation unit 564 generates oversampling data MOVSD subjected to edge correction.

  Here, the edge correction data generation unit 564 generates the oversampling data MOVSD by inverting the polarity of the oversampling data MOVSD at the edge position of the edge data MEDge subjected to the edge correction. However, since the polarity of the initial value cannot be determined by itself, the edge correction data generation unit 564 determines the polarity of the initial value based on the oversampling data OVSD.

  Specifically, the edge correction data generation unit 564, when the polarity of the oversampling data OVSD before edge correction is the same over a period longer than the worst jitter value assumed in the system, Using the fact that the sampling data MOVSD also has the same polarity as the OVSD, the polarity of the oversampling data MOVSD is determined, and thereafter the polarity is inverted at the edge position of the edge data MEDge.

  As described above, the edge correction data generation unit 564 can obtain the oversampling data MOVSD in which the edge position is corrected.

  In FIG. 4, an offset addition unit 567 represents a value obtained by adding 2 to the upper 3 bits of the phase data St output from the digital VCO 563 in order to correct the shift of 2 bits generated by the edge correction unit 560. A selection signal Sel is output so that an appropriate bit is selected by the subsequent data selection unit 6.

  In FIG. 2, the data selection unit 6 restores the restored data d0, d1, and d2 by using the oversampling data MOVSD output from the selection signal generating unit 7 and the selection signal Sel, and a status signal indicating an effective portion of the restored data S0 and S1 are output.

  FIG. 13 shows the configuration of the data selection unit 6. As illustrated in FIG. 13, the data selection unit 6 includes an F / F 700, a data generation unit 701, and a data state signal generation unit 702. The F / F 700 generates a signal dSel obtained by delaying the input selection signal Sel by one clock.

  The data generation unit 701 generates restored data d0, d1, and d2 from the input oversampling data MOVSD and the selection signals Sel and dSEL. FIG. 14 shows the relationship between the input signal and output signal of the data generation unit 701.

  The data status signal generation unit 702 generates status signals S0 and S1 indicating valid portions of data output from the data generation unit 701. FIG. 15 shows the relationship between the input signal and output signal of the data state signal generation unit 702.

  FIG. 16 is a diagram illustrating a configuration example of the deserializer 8. As shown in FIG. 16, the deserializer 8 includes a shift register 36 to which restored data d0, d1, and d2 are input, a symbol conversion unit 37, and a symbol synchronization control unit 38. The shift register 36 sequentially holds the restored data d0, d1, and d2 according to the status signals S0 and S1, and outputs the held restored data as parallel data PData.

  FIG. 17 is a diagram illustrating a detailed configuration example of the shift register 36 included in the deserializer 8. The shift register 36 shown in FIG. 17 includes F / Fs 40 (0) to (11) and multiplexers 41 (1) to (11). In addition, in FIG. 17, the illustration of those subsequent to F / F 40 (5) is omitted.

  F / Fs 40 (0) to (11) are connected in cascade to form a shift register. The multiplexers 41 (1) to (11) select restored data d0, d1, and d2 to be input to the F / Fs 40 (0) to (11), respectively, according to the status signals S0 and S1.

  Each of the multiplexers 41 (1) to (11) corresponds to a 3-bit shift, 2-bit shift, and 1-bit shift from the top among the three inputs of the restored data d1, d0, and d2, and {S1, S0} = {0,1}, the bottom input to perform 1-bit shift, and {S1, S0} = {1,1}, the top input to perform 3-bit shift, etc. In this case, since the 2-bit shift is performed, the middle input is selected and output.

  Further, the F / Fs 40 (0) to (11) output the outputs Q0 to Q11 as parallel data PData [0:11]. As a result, the data restored by 1 to 3 is converted in parallel.

  In FIG. 2, the comma detection unit 9 detects whether or not a predetermined comma code pattern is included in the parallel data PData output from the deserializer 8, and a detection signal Det representing the detection result is detected. The detected position signal DetPos (for example, the number of LSB bits of the detected comma code pattern) is output to the deserializer 8.

  Note that the comma code in the 8B / 10B conversion is “00111111010” or “1100000101” when the left side is FRB (First Received Bit). Here, “0011111001” or “1100010001” may be detected as another code having an attribute indicating a symbol delimiter.

  For example, when PData [11: 0] is “100111110101”, since PData [10: 1] matches the comma code, “H” is detected as the detection signal Det, and 1 is detected from the comma detection unit 9 as the detection position signal DetPos. Is output.

  18 is a signal waveform diagram for explaining the symbol synchronization control unit 38 and the symbol conversion unit 37 shown in FIG. In FIG. 18, PData [11] is a bit (FRB) received first, and PData [0] is a bit (LRB) received last.

  Further, (a) is a clock CK0, (b) is PData [11: 0], (c) is a detection signal Det, (d) is a detection position signal DetPos, (e-0), (e- 1) shows status signals S0 ′ and S1 ′ (where S0 ′ and S1 ′ are signals obtained by delaying S0 and S1 by one clock, respectively), and (g) shows one clock of parallel data PData. The delayed dPData, (h) is the symbol clock SYMCLK (the same signal as the latch enable signal LE), (i) is the symbol position signal LEPos indicating the symbol effective position of the parallel data PData, (j) is 10 bits Symbol data SYM signal is represented.

  When the comma code pattern COM is detected in the parallel data PData shown in (b) (the underlined portion of the enlarged view), the detection signal Det shown in (c) from the comma detection unit 9 and the detection shown in (d) A position signal DetPos is output.

  The symbol synchronization control unit 38 has a built-in counter, and uses the detection signal Det as a start signal and the detection position signal DetPos as a count initial value, and starts counting. This counter is counted by the number of 1 to 3 restored data input to the deserializer 8.

  That is, the symbol synchronization control unit 38 performs counting based on the status signals S0 ′ and S1 ′, and outputs a latch enable signal LE shown in (h) (LE) every time the count value accumulates 10 bits (one symbol). To “H”) and set the count value to −10.

  At the same time, the symbol synchronization control unit 38 outputs a count value as the symbol position signal LEPos shown in (i) indicating the effective position of the parallel data PData. The status signal is counted by using S0 ′ and S1 ′ shown in (e-1) and (e-2), respectively, which are delayed by the processing time in each block (one clock in this example).

  The symbol synchronization control unit 38 advances the count by 1 when {S1 ′, S0 ′} is {0, 1}, and advances the count by 3 when {S1 ′, S0 ′} is {1, 1}. In other cases, the count is advanced by two.

  The symbol conversion unit 37 delays the parallel data PData by one clock from the dPData shown in (g), and the 10-bit symbol shown in (j) according to the symbol position signal LEPos when the latch enable signal LE is “H”. Data SYM [0: 9] is taken out.

  Therefore, if the symbol position signal LEPos is 0, 1, or 2, dPData [9: 0] [10: 1] [11: 2] is extracted. If the symbol position signal LEPos is 3 or more, the data is extracted at the previous clock, so there is no data to be extracted here.

  The symbol synchronization control unit 38 outputs the same signal as the latch enable signal LE as the symbol clock SYMCLK. In this way, 10-bit symbol data SYM can be restored in synchronization with the symbol clock SYMCLK.

  The cycle of the symbol clock SYMCLK is normally 5 clocks (CK0) (10 clocks of the transfer clock), but is 4 clocks or 6 clocks depending on the frequency difference between the transmitting side and the receiving side. May be. This difference is absorbed by the elastic buffer 111 described with reference to FIG.

  FIG. 19 is a diagram illustrating a configuration example of the PLL 113. The PLL 113 shown in FIG. 19 includes frequency dividers 50 and 58, a phase frequency comparator 51, a low-pass filter 52, a voltage controlled oscillator 53, and a frequency divider circuit 55, and a transfer clock from the reference clock RefCLK. BCLK, internal operation clock PCLK, and multiphase clocks CK0 to CK11 are generated.

  The voltage controlled oscillator 53 includes a ring oscillator to which three stages of differential buffers 54a to 54c are connected, generates 6-phase clocks c0 to c5, and outputs one of them as a transfer clock BCLK.

  The frequency divider 50 divides the transfer clock BCLK by 10 and feeds it back to the phase frequency comparator 51. The phase frequency comparator 51 performs phase comparison between the reference clock RefCLK and the output of the frequency divider 50, and drives an inherent charge pump based on this phase difference information.

  The low pass filter 52 smoothes the charge pump output and supplies the control voltage Vc to the voltage controlled oscillator 53. The differential buffers 54a to 54c in the voltage controlled oscillator 53 perform phase synchronization control by changing the delay amount according to the control voltage Vc. For example, when a clock of 250 MHz is supplied as the reference clock RefCLK, the voltage controlled oscillator 53 generates a transfer clock BCLK of 2.5 GHz.

  The frequency divider 58 divides the transfer clock BCLK by 10 to generate the clock PCLK. The frequency dividing circuit 55 includes six frequency dividers 56a to 56f (configured by toggle F / F or the like) to which clocks c0 to c5 are input, and the normal rotation and inverted signals are output from the frequency dividing circuit 55. .

  Further, these two frequency dividers 56a to 56f are reset by the output RSTB of the reset circuit 57, and adjust the phase of each clock so as to be (c-0) CK0 to (c-11) CK11 shown in FIG. .

  That is, by dividing the 6-phase clocks c0 to c5 by 2, the 12-phase clocks CK0 to CK11 are generated by the 2-frequency dividers 56a to 56f at a frequency half that of the transfer clock BCLK.

  FIG. 20 is a diagram illustrating a relationship between a plurality of physical layer units and a PLL. The PLL 150 in FIG. 20 also serves as the multi-phase clock generation unit 2 and includes a plurality of physical layer units (here, the first and second lane physical layer units 151 and 152 are shown, and the others are not shown). The transfer clock BCLK, the clock PCLK, and the multiphase clocks CK0 to CK11 are commonly supplied.

  The first lane physical layer unit 151 includes a transmission unit 101-1 and a reception unit 102-1 (having the data recovery circuit of the present embodiment), and the second lane physical layer unit 152 also includes the first lane physical layer. Similarly to the unit 151, the transmission unit 101-2 and the receiving unit 102-2 (having the data recovery circuit of this embodiment) are provided.

  A reference clock RefCLK is supplied to the PLL 150, and the PLL 150 supplies a transfer clock BCLK and a clock PCLK to each of the transmission units 101-1 and 101-2, and a multiphase clock CK0 to each of the reception units 102-1 and 102-2. ˜CK11 is supplied. Thus, the PLL 150 can be shared by a plurality of physical layer units.

  As described above, when the phase difference between the phase of the input data and the phase represented by the detected phase data exceeds the specified value for phase correction, the data recovery circuit of this embodiment has an absolute value of the phase difference. Since the phase data is corrected so as to be reduced and then used as phase data for comparison with the input data, the influence of the jitter of the input data on the phase data can be reduced.

  From the characteristic evaluation results by simulation, it can be seen that the data recovery circuit according to the present embodiment has improved jitter tolerance by 0.15 UI or more compared to the data recovery circuits disclosed in Patent Document 2, Patent Document 3, and the like. It was.

  In addition, the data recovery circuit of the present embodiment can suppress the data recovery error because the eye opening of the input data whose edge position is corrected can be made larger than that before correction.

  For example, in the case of performing oversampling in which a transfer time per bit (hereinafter, 1 UI) is sampled, 1 UI is output as 8-phase data as shown in FIG. FIG. 21 shows 4 UI oversampled data.

  In FIG. 21, as oversampled data, b0, b1,. . . , B7. Here, for the sake of explanation, it is assumed that the reference frequency and phase of the sampling clock and the serially transferred data are completely the same.

  Further, it is assumed that the edge of the oversampling data OVSD is distributed in b1 to b5 (OVSD [0] to OVSD [5]) due to jitter, and the average value is b3. As a result, since there is no data edge in OVSD [6], OVSD [7], and OVSD [0], correct data can be demodulated by sampling data somewhere.

  When the clock is detected using the oversampling data OVSD, the DPLL 566 can detect a clock having an edge in any one of OVS [1] to OVS [5].

  Here, by sufficiently narrowing the bandwidth of the DPLL 566, it is possible to detect a clock whose edge is OVSD [3], which is an average edge position, and a position OVSD [ 7] can be sampled, in which case the correct data can be demodulated.

  On the other hand, if the bandwidth of the DPLL 566 is increased, it also follows Dj having a large jitter component in the intersymbol interference, crosstalk, and other high frequency regions that the DPLL 566 does not want to follow.

  As a result, a clock having OVSD [1] or OVSD [5] as an edge is reproduced with a certain probability, and OVSD [5] or OVSD [1] at a position 180 ° away from the clock edge is data. When sampled as a bit, a data recovery error occurs with a certain probability.

  Assuming that the Rj of serial data serially transferred at 5 Gbps is about σ = 2 ps, in order to keep the error rate below 1e-12, the peak-to-peak is 14σ (28 ps) jitter. It is necessary to see.

  On the other hand, in the data transfer of 5 Gbps, 1 UI has a time width of 200 ps, and when this is oversampled with 8 samples, the oversampling interval is 25 ps.

  Therefore, the jitter of 28 ps to be estimated as the influence of Rj is almost included in one oversample period. When an edge appears in OVSD [1] or OVSD [5] with OVSD [3] as the center, it is due to code interference, crosstalk, oversampling non-uniformity, etc. It may be considered that the kind of jitter that does not want to follow the DPLL 566 having a large component in the high frequency region is dominant.

  For this reason, the data recovery circuit according to the present embodiment detects the edge of the data edge when the edge of the input data is detected at a position that exceeds the edge correction specified value from the edge position obtained from the phase data St output from the DPLL 566. By correcting the position to be close to the edge position obtained from the phase data St output from the DPLL 566, the eye opening of the data can be made wider than that before correction.

  Further, when the data recovery circuit of the present embodiment detects the edge of the input data at a position exceeding the specified value for phase correction from the edge position obtained from the phase data St output from the DPLL 566, the phase difference in the DPLL 566 is detected. By clipping the detection result, it is possible to prevent the tracking of Dj that is not desired to be tracked without reducing the bandwidth of the DPLL 566.

  In addition, the data recovery circuit according to the present embodiment generates a multiphase clock using an independent reference clock without restoring the clock (embedded clock) included in the received data, and oversampled data oversampled with the multiphase clock. Data is restored from OVSD.

  That is, in the data recovery circuit of this embodiment, the selection signal generation unit 7 virtually restores the clock included in the reception data from the oversampled data OVSD as the clock pattern CKP, and the data selection unit 6 generates the clock pattern CKP. The data is restored by outputting the selection signal Sel indicating the position for taking in the data while comparing with the oversampled data OVSD while gradually changing.

  Further, most of the data recovery circuits except the oversampling unit 1 operate with a single frequency clock CK0, and there is almost no need to worry about the skew between multiphase clocks or between data. The data recovery circuit can easily cope with high speed.

  In addition, the data recovery circuit according to the present embodiment can be easily applied to circuit / layout design verification tools that have been remarkably developed in recent years, simplifying the design, improving circuit reusability, and shortening the development period. Can be realized.

  Furthermore, the data recovery circuit of this embodiment can be parallel-processed to further reduce the operating frequency, and the transfer rate can be easily increased.

  In addition, the data recovery circuit of the present embodiment can be easily changed from oversampling with 12 phases at a half frequency of the transfer clock BCLK to oversampling with 24 phases at a quarter frequency of the transfer clock BCLK, for example. By further lowering the operating frequency, the transfer data rate can be further increased.

  In addition, since the data recovery circuit of this embodiment can restore data using a clock that is not synchronized with the received data, the generation of the multiphase clock can be shared with the generation of the transfer clock BCLK, and the chip size Can be suppressed.

(Second Embodiment)
FIG. 22 is a block diagram showing a selection signal generation unit constituting the second embodiment of the data recovery circuit of the present invention. In the following, the same components as those already described are assigned the same reference numerals and description thereof is omitted.

  In FIG. 22, the selection signal generation unit 7 is different in that the selection signal generation unit 7 includes a comparison unit 321 instead of the comparison unit 21 illustrated in FIG. 4. The comparison unit 321 is different from the comparison unit 21 in that a prescribed value for phase correction can be set.

  As illustrated in FIG. 23, the comparison unit 321 is different from the comparison unit 21 in that it includes clip circuits 331 a to 331 d instead of the clip circuits 531 a to 531 d.

  The clipping circuit 331a to 331d receives the phase correction specified value setting data LevelA. The clip circuits 331a to 331d are different from the clip circuits 531a to 531d shown in FIG. 5 in that the phase correction specified value is changed to a level represented by the phase correction specified value setting data LevelA.

  Since the jitter characteristics of input data differ depending on the transmission path for data transmission and the surrounding environment, the optimum value for phase correction for the system differs for each system. For this reason, in the present embodiment, the phase correction specified values set in the clip circuits 331a to 331d of the comparison unit 321 can be changed from outside the selection signal generation unit 7, thereby eliminating the influence of the PLL characteristics and jitter. The configuration is such that the performance can be changed.

  Therefore, the data recovery circuit of this embodiment can suppress data recovery errors even when the transmission path and the surrounding environment change.

(Third embodiment)
FIG. 24 is a block diagram showing a selection signal generation unit constituting a third embodiment of the data recovery circuit of the present invention. In the following, the same components as those already described are assigned the same reference numerals and description thereof is omitted.

  In FIG. 24, the selection signal generation unit 7 is different in that the selection signal generation unit 7 includes an edge correction unit 360 instead of the edge correction unit 560 illustrated in FIG. 4. The edge correction unit 360 is different from the edge correction unit 560 in that a specified value for edge correction can be set.

  As shown in FIG. 25, the edge correction unit 360 is different from the edge correction unit 560 in that shift amount generation units 300 a to 300 d are provided instead of the shift amount generation units 600 a to 600 d.

  The shift amount generation units 300a to 300d receive edge correction specified value setting data LevelA. The shift amount generation units 300a to 300d are different from the shift amount generation units 600a to 600d shown in FIG. 11 in that the amount of edge correction of the edge data RxEdge is calculated according to the edge correction specified value setting data LevelB. To do.

  Since the jitter characteristics of input data vary depending on the transmission path for data transmission and the surrounding environment, the optimum value for edge correction varies depending on the system. For this reason, in this embodiment, it is possible to change the PLL characteristic and the performance of removing the influence of jitter by changing the edge correction specified values set in the shift amount generation units 300a to 300d of the edge correction unit 360. The configuration.

Therefore, the data recovery circuit of this embodiment can suppress data recovery errors even when the transmission path and the surrounding environment change.
(Fourth embodiment)
FIG. 26 is a block diagram showing a selection signal generation unit constituting the fourth embodiment of the data recovery circuit of the present invention. In the following, the same components as those already described are assigned the same reference numerals and description thereof is omitted.

  24, the selection signal generation unit 7 includes a comparison unit 321 instead of the comparison unit 21 illustrated in FIG. 4, includes an edge correction unit 360 instead of the edge correction unit 560, and further includes a selection circuit 310. Is different.

  The selection circuit 310 outputs Level A when the Lock signal is “L”, and outputs Level A2 when it is “H”. Here, the PLL 113 outputs an “L” Lock signal when the PLL 113 is not locked in the initial state, and outputs an “H” Lock signal when the phase of the generated clock follows the phase of the input data. It is designed to output.

  If the phase of the clock generated by the PLL 113 does not follow the phase of the input data, and if the phase data correction or the data edge correction is performed, the PLL 113 cannot be pulled in or cannot be pulled in. However, it may take a long time to pull in.

  For this reason, in this embodiment, when the PLL 113 is not locked, the prescribed value for phase correction in the comparison unit 321 is set to a level where clipping is not substantially performed or a level where the clip width is widened.

  Specifically, Level A1 is set to a level used when the PLL 113 is not locked, and Level A2 is set to a level used when the PLL 113 is locked, so that different phases are obtained when the PLL 113 is pulled in and when the PLL 113 is locked. The specified correction value can be set in the comparison unit 321.

  As described above, the data recovery circuit of this embodiment can stably perform the pull-in of the PLL 113.

It is a block diagram which shows the physical layer part of the serial transfer part to which 1st Embodiment of the data recovery circuit of this invention is applied. 1 is a block diagram showing a first embodiment of a data recovery circuit of the present invention. It is a timing chart which shows an example of each main signal of the oversampling part which comprises 1st Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the selection signal production | generation part which comprises 1st Embodiment of the data recovery circuit of this invention. FIG. 5 is a block diagram illustrating a comparison unit configuring the selection signal generation unit illustrated in FIG. 4. It is a graph which shows the characteristic of the 1st phase difference detection part which comprises the comparison part shown in FIG. It is a graph which shows the characteristic of the 2nd phase difference detection part which comprises the comparison part shown in FIG. It is a block diagram which shows the loop filter which comprises the selection signal production | generation part shown in FIG. FIG. 5 is a block diagram showing a digital VCO constituting the selection signal generation unit shown in FIG. 4. It is a conceptual diagram for demonstrating the process which the edge correction | amendment part which comprises the selection signal production | generation part shown in FIG. It is a block diagram which shows the edge correction | amendment part which comprises the selection signal production | generation part shown in FIG. 12 is a timing chart for explaining the operation of the edge correction unit shown in FIG. 11. It is a block diagram which shows the data selection part which comprises 1st Embodiment of the data recovery circuit of this invention. It is a figure which shows the relationship between the input signal and output signal of a data generation part which comprises the data selection part shown in FIG. It is a figure which shows the relationship between the input signal and output signal of the data state signal generation part which comprises the data selection part shown in FIG. It is a block diagram which shows the deserializer which comprises 1st Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the shift register which comprises the deserializer shown in FIG. It is a timing chart for demonstrating operation | movement of the symbol synchronization control part and symbol conversion part which comprise the deserializer shown in FIG. It is a block diagram which shows PLL which comprises the physical layer part shown in FIG. It is a block diagram at the time of providing one PLL with respect to a some physical layer part. It is a conceptual diagram for demonstrating the effect | action of 1st Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the selection signal production | generation part which comprises 2nd Embodiment of the data recovery circuit of this invention. It is a block diagram which shows the selection signal generation part which comprises the selection signal generation part shown in FIG. It is a block diagram which shows the selection signal production | generation part which comprises 3rd Embodiment of the data recovery circuit of this invention. FIG. 25 is a block diagram illustrating an edge correction unit that configures the selection signal generation unit illustrated in FIG. 24. It is a block diagram which shows the selection signal production | generation part which comprises 4th Embodiment of the data recovery circuit of this invention. It is a block diagram of a CDR circuit used conventionally. FIG. 28 is a timing chart showing an example of a problem when the phase difference of each clock of the multiphase clock is not equal in the CDR circuit shown in FIG. 27.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Oversampling part 2,900 Multiphase clock generation part 3 Symbol data decompression | restoration part 4,901 F / F circuit 5 Parallelization part 6 Data selection part 7 Selection signal generation part 8 Deserializer 9 Comma detection part 20 Both edge detection part 21, 321 Comparison unit 36 Shift register 37 Symbol conversion unit 38 Symbol synchronization control unit 40, 574, 581, 602, 700 F / F
41 Multiplexer 50, 58 Frequency divider 51 Phase frequency comparator 52 Low pass filter 53 Voltage controlled oscillator 54a-54c Differential buffer 55 Frequency divider 56a-56f Frequency divider 57 Reset circuit 100, 120 Physical layer part 101, 122 Transmission Unit 102, 121 receiving unit 103 encoder unit 104 serializer 105 transmission output unit 106, 107 transmission path 108 reception input unit 109 data recovery unit 110 deserializer 111 elastic buffer 112 decoder 113, 123, 150 PLL
151 First lane physical layer unit 152 Second lane physical layer unit 300a to 300d, 600a to 600d Shift amount generation unit 310 Selection circuit 331a to 331d, 531a to 531d Clip circuit 360, 560 Edge correction unit 530a, 530c First phase difference Detectors 530b, 530d Second phase difference detector 532 Adder circuit 562 Loop filter 563 Digital VCO
564 Edge correction data generation unit 566, 902 DPLL
567 Offset addition unit 570, 571 Multiplier 572, 575, 580 Adder 573 Limit circuit 601a to 601d Shift operation unit 603 OR circuit 701 Data generation unit 702 Data state signal generation unit

Claims (7)

A data recovery method for detecting phase information of input data and sampling the input data based on the phase information,
Detecting a phase difference between the phase of the input data and the phase represented by the detected phase information;
Correcting the phase information so that the absolute value of the phase difference is clipped to the prescribed value for phase correction when the absolute value of the phase difference exceeds the prescribed value for phase correction ;
And a step of correcting an edge position of the input data so that the absolute value of the phase difference is reduced when the absolute value of the phase difference exceeds a specified value for edge correction. . A data recovery method for detecting phase information of input data and sampling the input data based on the phase information,
Detecting a phase difference between the phase of the input data and the phase represented by the detected phase information;
And a step of correcting an edge position of the input data so that the absolute value of the phase difference is reduced when the absolute value of the phase difference exceeds a specified value for edge correction. . A data recovery circuit comprising a phase information detection circuit for detecting phase information from input data, and sampling the input data based on phase information detected by the phase information detection circuit,
The phase information detection circuit includes:
A phase difference detector that detects a phase difference between the phase of the input data and the phase represented by the detected phase information;
A clip circuit that corrects the phase information so that the absolute value of the phase difference clips to the prescribed value for phase correction when the absolute value of the phase difference exceeds the prescribed value for phase correction;
A data recovery circuit comprising: an edge correction unit that corrects an edge position of the input data so that an absolute value of the phase difference is reduced when the phase difference exceeds a specified value for edge correction; . 4. The data recovery circuit according to claim 3 , wherein the clip circuit is capable of changing the prescribed value for phase correction. Two phase correction values are input to the phase information detection circuit,
The phase information detection circuit performs one phase correction from the two prescribed values for phase correction according to whether or not the phase represented by the phase information detected by the phase information detection circuit and the phase of the input data are synchronized. With a selection circuit that selects the specified value for
5. The data recovery circuit according to claim 4 , wherein the clipping circuit corrects the phase information so that an absolute value of the phase difference is clipped to a prescribed value for phase correction selected by the selection circuit. A data recovery circuit comprising a phase information detection circuit for detecting phase information from input data, and sampling the input data based on phase information detected by the phase information detection circuit,
The phase information detection circuit includes:
A phase difference detector that calculates a phase difference between the phase of the input data and the phase represented by the detected phase information;
And an edge correction unit that corrects an edge position of the input data so that the absolute value of the phase difference is reduced when the absolute value of the phase difference exceeds a specified value for edge correction. Data recovery circuit. The edge correction unit, the data recovery circuit according to any one of claims 3 to 6, characterized in that it is possible to change the edge correction specified value.

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