KR100377505B1 - Jitter control circuit - Google Patents

Abstract

The present invention relates to a jitter control circuit of the bit leaking method. According to the present invention, an elastic buffer, buffer occupancy analyzer, clock regulator, DPLL, and frequency analyzer are used to implement the jitter control circuit of the bit-leak scheme for the SDH transmission network that satisfies the jitter standard recommended by the ITU-T. The jitter control circuit satisfies the performance criteria of ITU-T G.823, thus improving the market competitiveness of AIZ.

Description

Bit-leaking jitter control circuit {JITTER CONTROL CIRCUIT}

The present invention relates to a jitter control circuit, and more particularly, to a jitter control circuit of a bit leaking method.

In general, in a synchronous multiple device based on the ITU-T standard synchronous digital system (SDH), a pointer synchronization technique is applied as a method of synchronizing signal frames. This means that the pointer adjustment is compensated for the frequency difference of the clocks which are not synchronized with each other. Pointer adjustment in the SDH transmission network is more difficult to control than positive stuffing jitter in the PDH.

In addition, since the jitter in the PDH has a relatively high frequency of 1 bit, a second PLL having a 3 decibel bandwidth of several hundred hertz is used to reduce this jitter in the demultiplexer. On the other hand, pointer adjustment jitter in SDH networks is so narrow that the bandwidth of the required PLL is so narrow that it cannot be implemented using analog circuitry. In addition, the digital implementation of such a PLL requires several times higher frequency than the STM-1 clock.

Due to this conventional problem, in ITU-T G.783, an implementation of a bit leaking control circuit capable of spreading the n-bit phase difference caused by pointer adjustment to n 1-bit phases is urgently required.

Accordingly, an object of the present invention is to provide a jitter control circuit of a bit leaking method that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a jitter control circuit of a bit leaking scheme for an SDH transmission network that satisfies the jitter standard recommended by ITU-T.

In order to achieve the above object, in the present invention, the WDT and WCLK to each of the E1 signal data and the synchronized write clock is input; A buffer occupancy analyzer configured to input a WCLK, generate a Delet signal when the number of bits stored in the elastic buffer exceeds an upper limit threshold, and generate an Insert signal when the WCLK exceeds an upper limit threshold; a clock adjuster receiving a W'CLK signal, generating a CCLK signal, and receiving a Delet signal and an Insert signal from the buffer occupancy analyzer when justification and stuffing do not occur; A DPLL to which the CCLK signal generated from the clock regulator is input; And a frequency analyzer for inputting PPJ, PNJ, C1, and C2 signals representing positive justification, negative justification, and stuffing information, respectively, and transferring clock increases and decreases to the clock regulator in the form of clock insertion and removal signals. A jitter control circuit of a bit leaking method is provided.

1 is a block diagram of a bit leaking control circuit according to an embodiment of the present invention.

2 is a state transition diagram of a frequency change detector.

3 is a state transition diagram of a clock controller.

4 is a block diagram of a DPLL.

5 is a clock increase / decrease waveform.

6 is a state transition diagram of the K counter.

7 is a state transition diagram of a clock increment / decrementer.

8 is a state transition diagram of a buffer occupancy analyzer.

9 is a state transition diagram of a clock regulator.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a jitter control circuit of a bit leaking method according to the present invention.

Referring to the drawings, the WDT and WCLK input to the elastic buffer unit 1 represent the E1 signal data and the write clock synchronized thereto, respectively. The PPJ, PNJ, C1, and C2 signals input to the frequency analyzer 5 represent positive justification, negative justification, and stuffing information, respectively. The W'CLK signal input to the clock adjuster 3 represents a clock corresponding to the case where justification and stuffing have not occurred.

The frequency analyzer 5 applies the received justification information and the stuffing information to the bit leaking control algorithm to derive the bit leaking information, and then executes the clock increment and decrement operation, and adds and removes the clock. ) Is transmitted to the clock controller 3 in the form of a signal. The clock adjuster 3 inserts or removes one clock at W " CLK based on the insert and remove signals received from the frequency analyzer 5 to generate a CCLK signal and transfers it to the DPLL 4. Since the CCLK signal is a gap clock with one clock inserted or removed at W " CLK, the DPLL 4 smoothes it and restores RCLK, which is a read clock of the elastic buffer 1.

Due to the phase difference between the read clock RCLK and the write clock WCLK of the elastic buffer 1, the number of bits stored in the elastic buffer 1 exceeds an upper limit threshold to prevent overflow or underflow that may occur in the elastic buffer 1. Delet signal is generated to lower the frequency of the read clock. On the contrary, if the lower limit threshold is exceeded, an insert signal for increasing the frequency of the read clock is transmitted to the clock controller 3. By this operation, the number of bits in the elastic buffer 1 is maintained between the upper limit threshold and the lower limit threshold, thereby implementing a bit leaking control circuit capable of wander and jitter absorption with only one stage of the elastic buffer 1.

Here, the frequency analyzer 5 detects the occurrence of stuffing and justification based on the values of PPJ, PNJ, C1, and C2, and calculates an amount of clock adjustment as needed and a frequency change detector (not shown). And a clock control unit (not shown) that performs insertion and removal of the clock in accordance with the clock adjustment amount received from the detector. This frequency analyzer 5 counts the amount of justification and stuffing that occurred during time T (500 Hz in the present invention) and distributes it evenly during T.

2 shows a state transition diagram of the frequency change detector. The output signal in each state is as follows.

S3: C1, C2 Latch, Counter Enable

S4: PPJ, PNJ Latch

S5: PPJ, PNJ. C1, C2 latch

S6: PPJ, PNJ value latch

S7: C1, C2 value latch

S8: Calculate Clock Adjustment (SUM)

S10: SP <-"H", SUM output

2 shows a state transition diagram of the clock controller.

A, B and C in the drawing

A: Cntr = 100or200or300or400or500or600or700or800or900,

B: Cntr = 100or200or300or400or500or600or700or800,

C: Cntr = 100or200or300or400or500or600or700. The output signal in each state is as follows.

S2, S3, S4, S5, S6, S7, S8, S9: Counter active

S6, S7, S8, S9: if "SUM> 0" Add "H"

Or Erase "H"

4 shows a detailed block diagram of the DPLL 4.

Referring to the figure, the DPLL 4 is composed of a phase detector 10, a K counter 12, a clock increase / decrease 14, an N divider 16 and a two divider circuit 18.

The phase detector 10 compares the phase difference between φin which is the phase of the input signal and Φout which is the phase of the output signal of the DPLL 4 and outputs an error signal KdΦe. Kd represents a gain of the phase detector 10 and Φ e represents a phase difference Φ in -Φ out. The K counter 12 operates in conjunction with the clock increment / decrementer to generate a signal fed back through the N divider 16. In addition, the K counter 12 is composed of an up counter having a carry signal and a down counter having a right signal. Add and Erase of the K counter 12 are connected to the clock increase / decrease 14. At this time, as shown in FIG. 5, Erase causes the elimination of half cycles of the clock increase / decrease 14 output, while Add adds half cycles. The clock increment / decrementer 14 generates a half-division clock of CLK × 2N clock when no Add or Erase signal is generated.

Meanwhile, in FIG. 4, when the center frequency of the DPLL 4 is fc, the clock of the K counter 12 has the frequency of Mfc and the output frequency of the clock increase / decrease 14 is Nfc. Is expressed.

fc = RCLKxL / N

In addition, Kout which is the output of the K counter 12 and I / Dout which is the output of the clock increase / decrease 14 are as follows. Where K is the module of the K-counter.

Kout = KdΦeMfc / K

I / Dout = Nfc + KdΦeMfc / 2K

Therefore, the output of the DPLL 4 is as follows.

fout = fc + KdΦeMfc / 2KN

On the other hand, fmax, which is a tracking frequency range, can be derived from the above equation. At the end of the lock area, KdΦ is ± 1, so fmax is

Fmax = (fout) max-fc = Mfc / 2KN

It can be seen that by changing K in the above equation, the lock area of the DPLL 4 can be adjusted. In the locked state where fout and find of DPLL 4 are the same, there is a constant phase difference between the two signals. The equation below shows this expression of phase difference.

Φe = 2KN (fe-fc) / kdMfc

6 shows a state transition diagram of the K counter 12, and the output signal in each state is as follows.

S8: Erase "H"

S16: Add "H"

7 shows a state transition diagram of the clock increase / decrease 14, and the output signal in each state is as follows.

S1: RCLK × N ← CLK × 2N

S2: RCLK × N ← CLK × 2N

S3: RCLK × N ← CLK × N

S4, S5: RCLK × N ← “L”

8 shows a state transition diagram of the buffer occupancy analyzer 2.

Referring to the drawings, BL is a variable representing the number of bits in the buffer, and MBL represents the length of the elastic buffer. In addition, WCLK ↑ and RCLK ↑ represent the rising transition of WCLK and RCLK, respectively. The output value in each state is as follows.

S0: BL ← 0

S1: Bl ← BL + 1

S2: BL ← BL

S3: Bl ← BL

S4: BL ← BL + 1

If BL> upper threshold, Insert ← "H"

Or if BL <lower threshold, Delete ← "L"

S5: Bl ← BL -1

If BL> upper threshold, Insert ← "H"

If BL <lower threshold, Delete ← “L”

9 shows a state transition diagram of the clock regulator 3, and output signal values in each state are as follows.

S0, S1, S4: CCLK ← W'CLK

S2: CCLK ← "H"

S3, S5, S6, S7: CCLK ← "L"

What has been described above is only one embodiment, and the present invention is not limited to the above-described embodiment, and those skilled in the art without departing from the gist of the present invention as claimed in the following claims Anyone can make changes.

As described above, in the present invention, an elastic buffer, a buffer occupancy analyzer, a clock adjuster, a phase detector, a K counter, an N divider, a clock increase / decrease, a DPLL composed of a dividing circuit, a frequency change detector, and a clock controller By using the frequency analyzer which is composed of two bits, we implement the jitter control circuit of bit-leak method for SDH transmission network that satisfies the jitter standard recommended by ITU-T. Since the jitter control circuit satisfies the performance criteria of ITU-T G.823, there is an advantage that can improve the market competitiveness of the related products.

Claims (3)

In the bit-leaking jitter control circuit: An elastic buffer unit to which WDT and WCLK, respectively, representing E1 signal data and synchronized write clocks are input; A buffer occupancy analyzer configured to input a WCLK, generate a Delet signal when the number of bits stored in the elastic buffer exceeds an upper limit threshold, and generate an Insert signal when the WCLK exceeds an upper limit threshold; a clock adjuster receiving a W'CLK signal, generating a CCLK signal, and receiving a Delet signal and an Insert signal from the buffer occupancy analyzer when justification and stuffing do not occur; A DPLL to which the CCLK signal generated from the clock regulator is input; And PPJ, PNJ, C1, and C2 signals representing positive justification, negative justification, and stuffing information, respectively, are input, and a frequency analyzer is provided to transmit the clock increase and decrease to the clock regulator in the form of clock insertion and removal signals. The jitter control circuit of the bit leaking method. The jitter control circuit of claim 1, wherein the frequency analyzer comprises a frequency change detector and a clock control unit. The jitter control circuit of claim 1, wherein the DPLL comprises a phase detector, a K counter, an N divider, a clock increase / decrease, and a divider circuit.