KR19980049361A - AU Pointer Adjustment Jitter Reduction Device in Synchronous Multiple Devices - Google Patents

Abstract

In synchronous multiplexing, pointer adjustment jitter occurs when the AU3 signal is mapped to the VC3 signal. The pointer adjustment jitter is a conventional AU pointer adjustment jitter reduction device that is reduced by stuffing by 1/2 bit unit according to the bit leaking operation. However, in the related art, when the interval of occurrence of pointer adjustment is changed drastically, the interval of occurrence of bit leaking also changes rapidly, so that the amount of jitter at this moment may increase. Therefore, the present invention provides an improved AU pointer adjustment that can effectively reduce the jitter increase caused by changing the interval more gently by generating the bit-leaking interval by averaging the value calculated immediately before and the current calculated value. Jitter reducer. The reduction of the jitter component may improve the performance of the device to improve the reliability, and further contribute to stabilization of the transmission network.

Description

AU Pointer Adjustment Jitter Reduction Device in Synchronous Multiple Devices

The present invention is applied to a synchronous transmission technique used for inter-station transmission, which is a transmission between an exchange and an exchange. In a synchronous multiple device using a synchronous transmission technique, AU pointer adjustment may cause serious jitter on DS3 dependent signals.

Therefore, there is a conventional technique to solve this problem by placing an AU pointer adjustment jitter reduction device between the functions of interpreting the AU pointer and forming the VC3 signal in order to reduce the jitter component.

If the STM-1 clock and the system clock of the device are not synchronized with each other or there is a wonder component in the synchronous transmitter, the clock difference between the two clocks is generated. This clock difference is compensated for by adjusting the pointer value, i.e. byte stuffing, counted in bytes.

However, such pointer adjustment may cause jitter on the dependent signal, which may degrade the device performance and may not satisfy the output jitter specification of 1.5 UI. To solve this problem, based on the Bit Leaking algorithm, the byte component is divided into 1/2 bit units, 16 times of leaking and stuffing is performed to reduce the bit leaking unit to 0.5 UI components. There is a conventional AU pointer adjustment jitter reduction device (AU pointer adjustment jitter reduction device of a synchronous multiplexing device, Application No. 94-34029) to satisfy the following requirements.

Pointer adjustments that occur in a point-to-point (PTP) network generally occur somewhat constant, with some differences between occurrences.

However, in a network with a large number of nodes and a complex structure, there may be a case in which the occurrence interval between the front and rear pointer adjustments is drastically different from the above generation form. In this case, if the conventional method of generating bit leaking by simply dividing the pointer adjustment interval just generated by 16 (the number of bit leaks corresponding to one pointer adjustment), the jitter caused by the sudden difference is large. Can increase. Therefore, there is a need for a method for reducing such jitter.

The present invention is to reduce the jitter component by more gently processing the interval between the occurrence of bit leaking when the occurrence interval between the front and rear pointer adjustment is significantly different.

In order to achieve this, the present invention is to convert the byte (8-bit) component into a 0.5UI component and to process 16 bit-leakings, counting the interval of occurrence of pointer adjustment by the frame clock, and dividing the count value by two. By averaging the value and the previously calculated value, the averaged bit-leaking interval is sent to the bit-leaking interval counter to be processed to reduce the amount of jitter by smoothing the sudden change of interval.

By reducing the jitter component in this way, it is intended to improve the performance of the device, improve the reliability, and further contribute to the stabilization of the transmission network.

1 is a block diagram of an improved AU pointer adjustment jitter reduction device according to the present invention,

2 is a structural diagram of an AU pointer frame applied to the present invention,

3 is a detailed configuration diagram of a bit leaking processor of FIG. 1;

4 is a detailed configuration diagram of the bit leaking interval generator of FIG.

5 is a detailed configuration diagram of the stuffing and burst detector of FIG. 3;

6 is a detailed configuration diagram of the bit leaking request signal counter of FIG. 3;

FIG. 7 is a detailed configuration diagram of a gap clock generator of FIG. 3;

8 is a bit leaking process diagram;

9 is a timing diagram of a bit leaked gap clock.

Explanation of symbols on the main parts of the drawings

1, 4: address generator 2: elastic buffer

3: bit leaking processing unit 5: divider

11: bit leaking interval generator 12: bit leaking interval selector

13: bit leaking interval counter 14: bit leaking request signal counter

15 stuffing and burst detection circuit 16 gapped clock generator

17: delay 31: counter and divider

32: full adder and 2 divider 33: comparator

34: calculation circuit 135: calculation circuit 2

36: 3: 1 selector 37: latch

41: stuffing detection circuit 42: homogeneous and heterogeneous burst detection circuit

43: Burst and leaking code change decision circuit

51: operator control circuit 52: operator

53: Counter 61: 2: 1 Selector

62: gap clock generation control circuit 63: counter

64: AND logic circuit

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of an improved AU pointer adjustment jitter reducer according to the present invention. As shown in the drawing, in order to achieve the above object, the present invention is generated in the process of pointer processing when an AU3 signal is recorded as a VC3 signal. In the reduction circuit for reducing the AU pointer adjustment jitter, an elastic buffer (2) for supplying AU3 received data from the AU pointer analyzer (6) and VC3 received data to the VC3 processor (7), and the elastic buffer (2). A first address generator 1 connected to the first address generator 1 to generate a write address by the AU3 gap division clock of the AU pointer analyzer 6, and a read address generated by the V3 gap division clock to be connected to the elastic buffer 2; The frame clock, positive / negative stuffing information, and bit leaking control (BLC) clock are inputted from the second address generator 4 and the AU pointer analyzer 6, and the pointer interval is counted as a frame clock. The bit-leaking processing unit 3 and the bit-leaking, which divides the value by 2, averages the divided value and the previously calculated value, and supplies the V3 gap clock to the VC3 processor 7 by the averaged bit-leaking interval. It is connected to the processing unit 3 and the second address generator 4 and divides the VC3 gap clock output from the bit leaking processing unit 3 and supplies it to the second address generator 4 and the VC3 processor 7. It is composed of a divider (5).

The adjustment jitter reduction circuit is located between the AU pointer interpreter 6 and the VC3 processor 7 to receive the received data, the write clock, the positive / boost information and the frame clock from the AU pointer interpreter 6. The VC3 processor 7 supplies the VC3 gap clock, the VC3 divide clock and the VC3 received data.

When the first address generator 1 is connected to the elastic buffer 2 to generate a write address using a write clock that is an AU3 gap-divided clock (6.480 MHz), the elastic buffer 2 generates the AU3 pointer interpreter ( Accept and store AU3 received data in 6). Then, the VC3 received data is output to the VC3 processor 7 based on the read address of the second address generator 4.

At this time, the bit leaking processing unit 3 receives a BLC clock (51.840 MHz), positive / negative stuffing information and a frame clock from the AU pointer analyzer 6 to calculate a stuffing generation interval, and extracts a bit leaking interval. The clock is adjusted to generate a VC3 gap clock and supply it to the VC3 processor 7 and the divider 4. The divider 5 receiving the VC3 gap clock divides the VC3 gap clock by eight and supplies it to the second address generator 4 and the VC3 processor 7 as the VC3 gap divide clock.

Therefore, the AU3 received data is written to the elastic buffer 2 using the 6.480 MHz gap clock, and the data coming from the elastic buffer 2 is read out by dividing the clock coming from the bit leaking processing section 3 into eight.

At this time, if a stuffing process request is input from the AU pointer interpreter 6, AU3 received data and AU3 gap division clock are deleted by one byte (positive pointer adjustment or positive stuffing), or one byte is added (sub pointer adjustment or negative). Stuffed) and the pointer adjusted data is written to the buffer 2. In order to obtain the same effect as the pointer adjustment (byte stuffing) processing, the bit leaking processing section 3 calculates the pointer adjustment occurrence interval, and pushes 16 clocks in 1/2 bit units for each calculated bit leaking interval ( Positive bit leaking) or pull (sub bit leaking).

The VC3 gap clock adjusted by the bit leaking processing section 3 is divided into eight by the divider 5 and supplied to the second address generator 4. Therefore, the data written to the elastic buffer 2 reads the data by the bit-leaking read clock, and there is no data loss in the elastic buffer 2. That is, the feature of the present invention is that the bit leaking processing unit 3 generates the VC3 gap clock that is bit leaked by calculating the pointer adjustment interval.

2 shows a structural diagram of an AU3 frame applied to the present invention. Stuffing related information is stored in H1 and H2 bytes. If positive stuffing occurs, dummy data is contained in H3 byte, and actual data is contained in H3 byte when sub-stuffing occurs.

FIG. 3 is a detailed configuration diagram of the bit leaking processing unit 3 of FIG. 1. As shown therein, the next pointer adjustment from the previous pointer adjustment using the frame clock supplied from the AU pointer analyzer 6 is performed. It counts until it occurs, averages it, and generates the interval to be bit-leaked, outputs the count value obtained, and calculates the value calculated so far whenever pointer adjustment occurs by the calculation end and start signals. Selects the bit-leaking interval generator 11, which stores the value, resets the calculated value and recalculates, and one of the average value calculated by the bit-leaking interval generator 11 or the value calculated by the software. A bit leaking interval selector 12 comprising a logic circuit for selecting and outputting an input according to an external selection signal and a bit leaking from the bit leaking interval selector 12. It receives the interval value and counts the delayed frame clock to generate a bit leaking request signal, and the bit leaking interval counter 13, which is composed of a counter and a logic circuit, and the frame clock delaying the bit leaking interval The delayer 17 which provides the counter 13 as a clock for the down coefficient, and receives the constant stuffing signal and the boosting signal from the AU3 pointer analyzer 6 and based on the signal, the leaking completion signal, and the carry signal. To generate the calculation end and start signals supplied to the bit leaking interval generator 11 and the count start and end signals supplied to the bit leaking interval counter 13, as well as the +/- code signal and the like and Stuffing and burst detector 15 for outputting burst information for detecting heteroburst, burst information output from the stuffing and burst detector 15 and bits of the bit leaking interval counter 13 A bit-leak request signal counter 14 which detects the completion of bit-leaking as a input of a leaking request signal and outputs a leaking completion signal and a carry signal to the stuffing and burst detector 15, and a gap using a BLC clock. When the stuffing information is generated at this time, the gap clock generator 16 outputs the VC3 gap clock by performing a positive / negative bit leaking process at a gap position using a bit leaking request signal and a +/- code signal. It is composed.

The operation of the bit leaking processing unit of the adjustment jitter reducer according to the present invention configured as described above is as follows.

The bit-leakning interval generator 11, as a key aspect of the present invention, counts the interval from the previous pointer adjustment to the next pointer adjustment using the frame clock and averages it, and then calculates the interval to be bit-leaked. It performs the function of generating and supplies the count value obtained to the bit leaking interval selector 12.

At this time, the bit leaking interval generator 11 stores the values calculated so far and resets the calculated values every time the pointer adjustment occurs by the calculation end and start signals provided from the stuffing and burst detection circuit 15. It will be recalculated later. One of the average value calculated by the bit leaking interval generator 11 or the value calculated by the software of the CPU I / F is selected as the bit leaking interval, and the input is selected and output according to the external selection signal.

A function of generating a bit leaking request signal by receiving the bit leaking interval value output from the bit leaking interval selector 12 and counting the bit leaking interval counter 13 as a delayed frame clock by the delay unit 17. Is performed by counting start and end signals of the stuffing and burst detection circuit 15.

If a stuffing request does not occur, the bit leaking interval counter 13 does not operate, but when a stuffing request is received, the bit leaking interval coefficient value is received from the bit leaking interval selector 12 and temporarily stored in a buffer. The down counting is started by the frame clock which has passed 17. When the count value becomes 0, the bit leaking request signal is generated, and the stored bit leaking interval count value is read and counted again. The bit leaking interval counter 13 stops counting by an end signal from the stuffing and burst detection circuit 15.

At this time, the stuffing and burst detection circuit 15 receives a normal stuffing signal and a boosting signal, receives a leaking completion signal and a carry signal from the bit leaking request signal counter 14, and ends the calculation and start signals. Generates count start and end signals, plus / minus signals, and detects homogeneous and heterogeneous bursts.

The bit leaking request signal counter 14 inputs the burst information and the bit leaking request signal output from the stuffing and burst detection circuit 15 and the bit leaking interval counter 13 to complete the bit leaking. Detects and outputs a leaking completion signal and a carry signal to the stuffing and burst detection circuit 15, and the gap clock generator 16 gaps the 30 th clock using a BLC clock to generate 50.112 MHz, At this time, when stuffing information is generated, the bit biting request (half-clock meme) or the negative bit leaking (half-clock pulling) is performed at a position where the bit gaple request signal and the +/- code signal are gapped (see FIG. 9). ). The clocked clock as described above becomes a VC3 gap clock, is provided to the elastic buffer through a divider, and supplied to the VC3 signal processor.

FIG. 4 is a detailed configuration diagram of the bit leaking interval generator 11 of FIG. 3. As shown in FIG. 4, the frame clock is counted as a clock signal based on the calculation end and start signals and divided into two divisions (one bit shift write). After inserting the most significant bit into 0, the counter and the divider 31 for generating the calculated value 1 according to the bit-leaking interval measurement for the pointer adjustment interval and the counter and the divider 31 are provided. A full adder and a divider 32 which add the calculated value 1 and the average value 1, which is the previous average value, and then divide by 2 (1 bit shift write) to generate the calculated value 2 which is the average value, and the calculated value Comparing the size of the average value 1 with 1 and outputs the information, and the value calculated by subtracting the set value 1 set as the weight to the calculated value 2 output from the folder and the divider 32 Calculation circuit 1 (34), and calculated value 2 output from the folder and divider (32) A calculation circuit 2 (35) for generating a value obtained by adding a set value 1 set as a weight, and among calculation values coming from the full ether and the divider (32), the calculation circuit 1 (34) and the calculation circuit 2 (35). The 3: 1 selector 36, which is selected based on the comparison information of the comparator 33, and the outputs of the 3: 1 selector 36 are latched to the full ether and the divider 32 at an average value 1. It is composed of a latch 37 for feeding back and outputting to the bit leaking interval selector 12.

Referring to the operation of the bit leaking interval generator 11 is configured as follows.

The counter and the divider 31 are circuits for measuring the interval between stuffings which are pointer adjustments. It counts only when the calculation end and start signals are 1, using the frame clock as the clock signal, and resets the counter when 0. The count value counted as described above is changed to the calculated value 1, which is a bit leaking interval with respect to the pointer adjustment interval by shifting 1 bit right and inserting the most significant bit as 0 to perform 2 division. In the prior art, the calculated value 1 is supplied to the bit leaking interval counter 13 directly through the bit leaking interval selector 12 without averaging the calculated value 1, which is the bit leaking interval with respect to the pointer adjustment interval. The average is supplied to the bit leaking interval counter 13.

Accordingly, the output of the counter and the divider 31 is supplied to a full adder and the divider 32, and the calculated value 1 is added to the previous average value 1, and then divided into two divisions (1 Bit shift write) to generate a calculated value 2 that is an average value. The pole ether and the divider 32 are composed of a pole ether and a logic circuit. Here, the calculated value 2 represents the averaged bit leaking interval, but if it is used immediately, the size of the elastic buffer 2 must be increased, so the calculated value 1 compares the average value 1 and controls accordingly.

As described above, the comparator 33 compares the magnitudes of the calculated value 1 and the average value 1 and then provides them to the 3: 1 selector 36 to select the corresponding value. The information provided to the 3: 1 selector 36 uses two bits, 'C1' and 'C0'. If the value of 'C1C0' is 00, the calculated value 1 and the average value 1 are equal, and if it is 01, the average value 1 is larger than the calculated value 1, and if the value is 10, the average value 1 is smaller than the calculated value 1.

The comparator 33 is composed of a logic circuit.

The calculation circuit 1 34 performs a function of generating a value obtained by subtracting a set value 1 set as a weight from the calculation value 2 output from the full adder and the divider 32, which is a full adder and a logic circuit. It consists of. The setting value 1 is set for the system and provided through the CPU connection. The calculation circuit 2 35 performs a function of generating a value obtained by adding the set value 1 set as the weight to the calculation value 2 output from the full ether and the divider 32, and the configuration thereof includes It consists of logic circuits.

The 3: 1 selector 36 selects C0 and C1 values of the comparator 33 among the calculated values from the full adder and the divider 32, the calculation circuit 1 34 and the calculation circuit 2 35, respectively. Therefore, one value is selected and provided to the latch 37. That is, if the current calculated value 1 is greater than the average value 1, the value of the calculation circuit 2 (35) is selected. If the current calculated value 1 is less than the average value 1, the value of the calculation circuit 1 (34) is selected, and the average value. If 1 and the calculated value 1 are the same, select the calculated value 2 and output it.

Therefore, if the current calculated value 1 is larger than the average value 1, that is, if the current pointer adjustment interval is wider than the previous pointer adjustment interval, the newly calculated average value is added to the newly calculated average value by the weighted setting value 1 to make the bit leaking interval more wide. do. On the contrary, if the current calculated value 1 is smaller than the average value 1, that is, if the current pointer adjustment interval is narrower than the previous pointer adjustment interval, the bit buffering interval is made narrower by subtracting the set value 1 from the newly calculated average value. The burden on the size of (2) can be reduced.

The latch 37 latches the calculated value coming from the 3: 1 selector 36 in the zero state by the calculation end and start signals of the counter and the divider 31. The latched data becomes the final average value 1, which is supplied to the bit leaking interval counter 13 via the bit leaking interval selector 12 and also to the full ether and the divider 32 and the comparator 33. to provide.

FIG. 5 is a detailed configuration diagram of the stuffing and burst detection circuit 15 of FIG. 3. As shown therein, the calculation ends and starts with the bit leaking interval generator 11 based on the constant stuffing information and the boosting information. A stuffing detection circuit 41 for sending a signal, outputting a counting start and end signal to the bit leaking interval counter 13, and generating a +/− sign signal 1, based on the constant stuffing information and the boosting information If a burst of the same polarity is generated, a homogeneous burst signal 1 is output; if a burst of different polarity is output, a heterogeneous burst signal 1 is output, and a homogeneous and heterogeneous burst detection indicating a generation of homogeneous and heterogeneous bursts reset by the leaking completion signal is detected. In response to the circuit 42, the +/- code signal 1, the homogeneous burst signal 1, and the heterogeneous burst signal 1, the state of the +/- code signal 1 is changed upon request to change the sign and polarity according to the carry signal. Output, and consists of a burst and riking sign change determining circuit (43) for each turn outputs the same type / two kinds of burst signals.

Referring to the operation of the stuffing and burst detector 15 configured as described above are as follows.

The stuffing detection circuit 41 receives the constant stuffing information and the boosting information and sends a calculation end and start signal to the bit leaking interval generator 11 accordingly, and counts the bit leaking interval counter 13. A start and end signal are output, and a +/- code signal 1 is output to the burst and leaking code change determination circuit 43. The stuffing detection circuit 41 is composed of a JK flip flop, a D flip flop, and a logic circuit.

The calculation end and start signals end the generation of the calculated bit leaking interval calculated by averaging in the 0 state and store the calculated bit leaking interval, and start the calculation again in the 1 state. The initial state of this signal stays in one state at the beginning and then changes to zero when positive or boosting occurs.

The counting start and end signals operate in the same manner as the counting end and start signals, but since the counting starts after receiving the bit leaking interval from the bit leaking interval counter 13, the counting delay and the start signal are delayed. Occurs. The positive / signal signal 1 outputs a zero state when positive stuffing occurs and causes the gap clock generator 16 to perform positive bit leaking, and when boosting occurs, one state is output to perform negative bit leaking. do.

On the other hand, the homogeneous and heterogeneous burst detection circuit 42, which receives the constant stuffing information and the boosting information, outputs one state to the homogeneous burst signal 1 when a burst of the same polarity occurs, and the heterogeneous burst when the burst of the other polarity is generated. The signal 1 is output in 1 state to indicate the occurrence of homogeneous and heterogeneous bursts. This signal is also reset by the leaking completion signal of the bit leaking request signal counter 14.

The homogeneous and heterogeneous burst detection circuit 42 is composed of a D flip-flop and a logic circuit.

The burst and leaking code change determining circuit 43 receives a +/- code signal 1, a homogeneous burst signal 1, and a heterogeneous burst signal 1 and outputs the same as the current state unless a change of a sign and a polarity is required according to the carry signal. When the code and polarity change request are made, the +/- code signal 1 is changed to 1 state if the state is 0, and if it is 1 state, it is changed to 0 state and then output as +/- code signal. The homogeneous burst signal 1 is a heterogeneous burst signal, and the heterogeneous burst signal 1 is converted into a homogeneous burst signal for output.

The sign and polarity change request occurs when the heterogeneous burst signal becomes 1 and the carry signal from the bit leaking request signal counter becomes 1 state. The output value used for the circuit is reset to the initial state by the leaking completion signal. The burst and leaking code change determination circuit 43 is composed of a D flip-flop and a logic circuit.

FIG. 6 is a detailed configuration diagram of the bit leaking request signal counter 14 of FIG. 3. As shown therein, an operator control circuit 51 outputting an operator control signal based on the burst information, and the control thereof. By calculating the bit-leak request signal coefficient value using the fixed value 16, and calculating the count value by the bit-leak request signal coming from the bit-leak interval counter. When it is in the 0 state, the counter 53 is configured to generate a leaking completion signal.

In the bit leaking request signal counter 14 configured as described above, the operator control circuit 51 controls the operation of the operator 52 by inputting burst information from the stuffing and burst detection circuit 15. A signal is output, and the controlled calculator 52 calculates using the output value of the counter 53 and 16 which is a fixed value. The calculated count value is loaded into the counter 53 and counted down by the bit leaking request signal from the bit leaking interval counter. When the value is 0, the leak completion signal is generated.

FIG. 7 is a detailed block diagram of the gap clock generator 16 of FIG. 3, wherein the 2: 1 selector 61 selecting the BLC clock and its inverted clock by a clock selection signal as shown in FIG. The clock selection signal is generated by using the bit-leak request signal from the trimming interval counter 13 and the +/- code signal from the stuffing and burst detection circuit 15. The gap clock generation control circuit 62 which provides the coefficient control signal and, when there is no byte stuffing, the 30th clock is gapped using the selected clock from the 2: 1 selector 61, and when byte stuffing occurs, the gapping is performed. A counter 63 for generating a gap signal for positive / sub bit leaking at a gapping position using the count control signal, and a selection clock from the 2: 1 selector 61 and a counter 63; Coming gap signal After the AND logic is applied, the AND circuit 64 generates the VC3 gap clock. The gap clock generator 16 is composed of a counter, a D flip flop, and a logic circuit.

Referring to the operation of the gap clock generator configured as described above is as follows.

The 2: 1 selector 61 generates an inverted clock by using a 51.84 MHz BLC clock and inverts the BLC clock 0 and the inverted clock 1 by a clock selection signal from the gap clock generation control circuit 62. Select). The selected clock is supplied to the counter 63 and the AND circuit 64.

The gap clock generation control circuit 62 performs positive bit leaking by using a bit leaking request signal from the bit leaking interval counter 13 and a +/- sign signal from the stuffing and burst detection circuit 15. A clock select signal for selecting a source clock for over bit leaking is generated, and a counter control signal is provided to the counter 63 for positive and negative bit leaking to push and pull the clock.

The counter 63 generates and provides a gap signal to the AND circuit 64 by gapping the 30 th clock using a selection clock from the 2: 1 selector when no byte stuffing occurs. In addition, if byte stuffing occurs, a half clock is pushed at the gapping position (forward bit leaking) or a half clock is pulled by using the count control signal from the gap clock generation control circuit 62 after the 30 th clock is gapped. Boosting) generates a gap signal and supplies it to the AND circuit 64. (See FIG. 9)

The AND circuit applies AND logic using the selection clock from the 2: 1 selector 61 and the gap signal from the counter to generate the VC3 gap clock.

FIG. 8 is a detection state diagram of pointer adjustment jitter according to an embodiment of the present invention. (A) shows pointer adjustment jitter generated due to a difference between a read and a write clock when no bit leaking is processed. The pointer adjustment jitter that has been bit-leaked using the technique is shown, and (c) shows the pointer adjustment jitter that appears when using the improved AU pointer adjustment jitter reducer of the present invention. In (a), when the pointer adjustment interval changes drastically, the interval of (b) bit leaking also changes drastically, but in (c), the bit-leaking interval is processed on average.

9 is a timing diagram of a bit leaking gap clock, (a) shows a VC3 gap clock in which the 30th clock is gapped in a steady state without stuffing, and (b) positive stuffing occurs. The half-clock push at the gap position indicates the occurrence of positive bit leaking, and (C) shows the occurrence of the negative bit pulling at the position where the gap stuffing is caused by the sub-clock pulling.

According to the present invention configured and operated as described above, when byte stuffing, which is an AU pointer adjustment, occurs 16 times bit-leaking in 1 / 2-bit units, the bit-leaking interval is treated as an average value. By slightly changing the trimming interval, you can reduce the expected increase in jitter.

The conventional technique of reducing jitter by stuffing in 1 / 2-bit units according to bit-leaking operation when byte stuffing, an AU pointer adjustment, occurs (application number: 94-34029). The king spacing also changes rapidly, which can increase jitter at this moment. Therefore, as presented in the present invention, by averaging the bit-leaking intervals, the jitter component can be reduced by changing the intervals more gently. In addition, the reduction of the jitter component can improve the device performance to improve the reliability of the device, and further contribute to stabilization of the transmission network.

The present invention relates to an AU pointer adjustment jitter reduction device for reducing pointer adjustment jitter which occurs when an AU3 (Administrative unit-3) signal is historically represented as a VC3 (Virtual container-3) signal in a synchronous multiple device. It is an object of the present invention to provide an improved AU pointer adjustment jitter reduction device for effectively reducing the jitter increase component that may occur when the interval changes abruptly by supplementing the bit leaking generation interval.

Claims (6)

An apparatus for reducing AU pointer adjustment jitter generated during pointer processing by using bit-leaking processing means when inverting an AU3 signal in a synchronous multiple device into a VC3 signal, Elastic buffer means for supplying the AU3 received data of the AU pointer analyzer to the VC3 received data of the VC3 processor; First address generating means for generating a write address of said elastic buffer means by an AU3 gap division clock; Second address generating means for generating an address of said elastic buffer means by a divided VC3 gap clock; Frame Clock, Positive / Boosting inputs information and Bit Leaking Control (BLC) clock to count the interval between pointer adjustments as the frame clock, averages the counts, and averages the current average and the previously calculated average again. A bit leaking processing means for counting the bit leaking intervals, generating a VC3 gap clock according to the counted bit leaking intervals, and outputting the VC3 gap clock to the VC3 processor; And a dispensing means for distributing the VC3 gap clock outputted from the bit leaking processing means and supplying the second address generating means and the VC processor to the VC processor. The method of claim 1, wherein the bit leaking processing means, A bit leaking interval generator 11 which counts previous pointer adjustment intervals using a frame clock, averages them, and generates intervals to be bit leaked, A bit leaking interval selector 12 for selecting one of the average value calculated by the bit leaking interval generator 11 or the value calculated by the software as the bit leaking interval, A bit leaking interval counter 13 which receives a bit leaking interval value from the bit leaking interval selector 12 and counts down by a delayed frame clock to generate a bit leaking request signal; A delay unit 17 delaying the frame clock and providing the bit clocking interval counter 13 as a clock for a down coefficient; On the basis of the positive stuffing signal, the busping signal, the leaking completion signal, and the carry signal from the AU3 pointer analyzer, a +/- code signal is generated, and the bit leaking interval generator 11 receives a calculation end and start signal from the AU3 pointer analyzer. A stuffing and burst detector 15 for supplying counting start and end signals to the bit leaking interval counter 13 and outputting burst information by homogeneous and heterogeneous burst detection; A bit leaking request signal counter 14 for detecting completion of bit leaking by inputting the burst information and the bit leaking request signal and outputting the leaking completion signal and a carry signal; A gap clock is generated using a BLC clock, and when stuffing information is generated, a gap clock that outputs a VC3 gap clock by performing a positive / negative bit leaking process at a gap position using a bit leaking request signal and a +/- code signal. AU pointer adjustment jitter reduction device in a synchronous multiple device, characterized by comprising a generator (16). The method of claim 2, wherein the bit leaking interval generator 11, Based on the calculation end and start signals, the frame clock is counted as a clock signal, divided by two (1 bit shift write), and the most significant bit is inserted into 0. A counter and a divider 31 for generating a, A full adder and a divider 32 which adds the calculated value 1 and the average value 1, which is the previous average value, and then divides the result by two (1 bit shift write) to generate the calculated value 2 which is the average value; A comparator 33 for comparing the magnitude of the calculated value 1 with the average value 1 and outputting the information thereof; A calculation circuit 1 (34) for generating a value obtained by subtracting a set value 1 set as a weight to the calculated value 2; A calculation circuit 2 (35) for generating a value obtained by adding the set value 1 set as a weight to the calculated value 2; Based on the comparison information, if the current calculated value 1 is greater than the average value 1, the value of the calculated circuit 2 35 is selected. If the current calculated value 1 is less than the average value 1, the value of the calculated circuit 1 34 is determined. A 3: 1 selector 36 for selecting the calculated value 2 of the folder and the divider 32 in the same case; A latch 37 which latches the output of the 3: 1 selector 36 to feed back to the full ether and the divider 32 with an average value of 1, and outputs to the bit leaking interval selector 12. AU pointer adjustment jitter reduction in synchronous multiplexing. The stuffing and burst detection circuit (15) of claim 2, The calculation end and start signals are sent to the bit leaking interval generator 11 based on the constant stuffing information and the boosting information, the count start and end signals are output to the bit leaking interval counter 13, and +/- A stuffing detection circuit 41 for generating code signal 1; On the basis of the constant stuffing information and the boosting information, if a burst of the same polarity is generated, a homogeneous burst signal 1 is output; And homogeneous and heterogeneous burst detection circuits 42 for informing heterogeneous bursts; Receives the +/- code signal 1, the homogeneous burst signal 1, the heterogeneous burst signal 1, and outputs by changing the state of the +/- code signal 1 upon request to change the sign and polarity according to the carry signal. An apparatus for adjusting AU pointer jitter in a synchronous multiplex device, characterized in that it comprises a burst and a leaking code change determination circuit (43) which outputs a burst signal by interchange. The method of claim 2, wherein the bit leaking request signal counter 14, An operator control circuit 51 for outputting an operator control signal based on the burst information; An arithmetic unit 52 for calculating the bit-leak request signal count value using the fixed value 16 by the control; The counted coefficient value is counted down by the bit-leaking request signal from the bit-leaking interval counter, and when the value is 0, the synchronous multi-device comprises a counter 53 for generating a leaking completion signal. Pointer Adjustment Jitter Reduction Device The method of claim 2, wherein the gap clock generator 16, The 2: 1 selector 61 for selecting the BLC clock and its inverted clock by a clock select signal, The clock selection signal is generated by using the bit leaking request signal from the bit leaking interval counter 13 and the +/- sign signal from the stuffing and burst detection circuit 15, and the positive and negative bit leaking is performed. A gap clock generation control circuit 62 for providing a coefficient control signal for When there is no byte stuffing, the 30th clock is gapped using the selected clock coming from the 2: 1 selector 61, and when byte stuffing occurs, the gapped clock is positive / negative at the gapping position using the coefficient control signal. A counter 63 for generating a gap signal for bit leaking; Synchronous multiplexing, characterized in that it consists of an AND circuit (64) which generates VC3 gap clock after applying AND logic using the selection clock from the 2: 1 selector (61) and the gap signal from the counter (63). AU Pointer Adjustment Jitter Reduction Device.