KR930011251B1 - Tu pointer controlling gitter attenuator circuit of synchronous multiple equipment - Google Patents

Abstract

The circuit decreases the tuning jitter generated in the process of the byte stuffing. The circuit comprises the elastic buffer unit which TUin and VCin receiving data can be written down or read; the first address generator unit (1) which generates a writting address by writting clock; the second address generator which provides a reading address by read clock; the buffering process unit which extracts out the bit leacking interval and calculates the stuffing generation span; and a frequency divider which provides various the divided frequency signals.

Description

TU Pointer Adjustment Jitter Reduction Circuit in Synchronous Multiple Devices

1 is a configuration diagram of a TU pointer adjustment jitter reduction circuit according to the present invention.

2 is a structural diagram of a TUin frame applied to the present invention.

3 is a detailed configuration diagram of the bit leaking processing unit in FIG.

4 is a detailed block diagram of the stuffing and burst detection circuit of FIG.

5 is a detailed configuration diagram of the bit leaking request signal counter of FIG.

* Explanation of symbols for the main parts of the drawings

1,4 Address generator 2: Birth buffer

3: bit leaking processing unit 5: divider

11: bit leaking interval generator 12: bit leaking interval selector

13: bit leaking interval counter 14: bit leaking request signal counter

15 stuffing and burst detection circuit 31 stuffing detection circuit

32: homogeneous and heterogeneous burst detection circuit

33: Burst and leaking code change determination circuit

41: operator control circuit 42: operator

43: counter

According to the present invention, in the synchronous multiplexing device, the TUin (Tributary Unit in: n = 1, 2) signal is converted into a VCin (Virtual Continer in: n = 1, 2) signal. TU pointer adjustment jitter reduction circuit for reducing

When the STM-1 clock and the new STM-1 clock at the time of initial VCn formation are operated as independent clocks that are not synchronized with each other at the network node, the difference between the two clocks is compensated by adjusting the pointer value counted in bytes. However, the jitter component caused by the pointer adjustment does not satisfy the allowed 1.5 UI output jitter.

Therefore, in the present invention, the pointer adjustment jitter generated by processing the read clock of the elastic buffer in byte units when stuffing occurs, based on the bit leaking algorithm, 64 times in 1/8 bit units to handle the stuffing It is an object of the present invention to provide a TU pointer adjustment jitter reduction circuit which reduces the adjustment jitter to 0.125 UI or less to satisfy the specification of the output jitter.

In order to achieve the above object, the present invention provides a pointer adjustment jitter reduction circuit for reducing pointer adjustment jitter generated during the byte stuffing process in which a TUin signal is converted into a VCin signal, so that TUin received data and VCin received data can be read and written. An elastic buffer means, first address generating means connected to the elastic buffer means for generating a write address by a write clock, second address generating means connected to the elastic buffer means for generating a read address by a read clock, and a frame A bit leaking processing means for calculating a stuffing generation interval and extracting a bit leaking interval by inputting a clock, positive / negative stuffing information, and a BLC clock, and being connected to the bit leaking processing means and an address generating means. The number of occurrences of the address is divided by dividing an upper clock output from the trimming processing means To be supplied to is characterized in that the means consists of a frequency divider.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a TU pointer adjustment jitter reduction circuit according to the present invention, where 1 and 4 represent an address generator, 2 an elastic buffer, 3 a bit leaking processor, and 5 a divider.

The TU pointer adjustment jitter reduction circuit according to the present invention comprises two address generators (1, 4), an elastic buffer (2), a bit leaking processor (3), and a divider (5) as shown in FIG. A TU pointer interpreter (not shown) and a VCin processor (not shown) to receive data and write clocks, positive / boost stuffing information, and a frame clock from the TU pointer interpreter. It supplies VCin higher clock, VCin dispensing clock and VCin receiving data.

The address generator 1 is connected to the elastic buffer to generate a write address using a 288 KHz (216 KHz) gap clock, and the address generator 4 is 280 KHz (208 KHz) output from the divider 5. ) The read address is generated using the clock.

The elastic buffer 2 reads and writes the TUin received data and the VCin received data by using the read address and the write address generated by the address generators 1 and 4.

The bit leaking processor 3 inputs a BLC clock (17.920 MHz when using TU12, 13.312 MHz when using TU11), positive / boost stuffing information, and a frame clock from the TU pointer analyzer to input a stuffing interval. The clock is adjusted by calculating and extracting the bit leaking interval.

The divider 5 is connected to the bit leaking processor 3 and the address generator 4 to output the VCin upper clock (4.408 MHz when using TU12 and 3.328 MHz when using TU11) output from the bit leaking processor 3. 16 divisions are supplied to the address generator 4.

The TU12 (TU11) received data is written to the 16-byte elastic buffer 2 using a 288 KHz (216 KHz) gap clock, and the clock coming from the bit leaking processing section 3 (4.480 MHz using TU12, 3.312 using TU11). MHz) The data is read from the elastic buffer 2 using a 16-minute clock (280 KHz when using TU12 and 208 KHz when using TU11). At this time, if a stuffing process request is input from the TU pointer analyzer, the bit leaking processing unit 3 that receives the BLC clock (17.920 MHz for TU12 and 13.31 MHz for TU11) calculates a stuffing generation interval. Then, the bit-leaking interval obtained by dividing the calculated interval by 64 to obtain the same effect as the byte stuffing process is extracted, and the clock is pulled or lags 64 times in 1 / 8-bit units during the bit-leaking interval. The clock adjusted by the bit-leaking processing section 3 (4.480 MHz when using TU12 and 3.328 MHz when using TU11) is supplied to the address generator 4 as a clock divided by 16 from the divider 5 to the elastic buffer 2. To read the data. In this case, the data written to the elastic buffer 2 by byte stuffing is read out by the bit leaking read clock, so that there is no data loss in the elastic buffer 2.

2 is a structural diagram of a TUin frame applied to the present invention, (a) TU11. (B) shows the frame structure of TU12.

The TU11 and TU12 frames are formed as shown in FIG. 2, and stuffing related information is stored in the V1 and V2 bytes. If the normal stuffing occurs, dummy data is put in the byte following the V3 byte, and boosting is performed. When generated, dummy data is contained in V3 bytes.

3 is a detailed configuration diagram of the bit leaking processing unit 3 of FIG. 1, 11 is a bit leaking interval generator, 12 is a bit leaking interval selector, 13 is a bit leaking interval counter, and 14 is a bit leaking request signal counter. 15 denotes a stuffing and burst detection circuit, and 16 denotes a main counter.

The bit leaking processing section 3 includes a bit leaking interval generator 11, a bit leaking interval selector 12, a bit leaking interval counter 13, and a bit leaking request signal counter as shown in FIG. 14, a stuffing and burst detection circuit 15, and a main counter 16. As shown in FIG.

The bit leaking interval generator 11 composed of a counter and a logic circuit performs a function of generating an interval to be counted and bit-leaked until a stuffing request occurs using a frame clock. Supply to interval selector 12. The maximum measuring interval of the diffuser counter is 8.192 sec (2 ²⁰ × 500 μsec) and the counter's output is reset each time stuffing occurs.

The bit leaking interval selector 12 is configured as a logic circuit which selects one of the value calculated by the bit leaking interval generator or the value calculated by the software and selects and outputs an input according to an external selection signal. .

The bit leaking interval counter 13 receives a bit leaking interval value from the bit leaking interval selector 12 and counts the bit leaking interval signal with a 128 kHz clock to generate a bit leaking request signal. The operation of the bit leaking interval counter 13 is performed by counting start and end signals of the stuffing and burst detection circuit 15. If a stuffing request does not occur, the bit leaking interval counter 13 does not operate. However, when a stuffing request is made, the bit leaking interval count value is received from the bit leaking interval selector 12 and temporarily stored in a buffer. The down coefficient is started by the synchronized delay clock. When the count value becomes '0' state, the bit leaking request signal is generated, and the stored bit leaking interval count value is read and counted again. The bit leaking price counter 13 stops counting by an end signal from the stuffing and burst detection circuit 15.

The stuffing and burst detection circuit 15 has a function of generating a count start light end signal and a +/- sign signal and detecting homogeneous and heterogeneous bursts.

The bit leaking request signal counter 14 inputs the burst information and the bit leaking request signal output from the stuffing and burst detection circuit 15 and the bit leaking interval counter 13 to complete the bit leaking. It detects and outputs a leaking completion signal and a carry signal to the stuffing and burst detection circuit 15.

The main counter 16 functions to generate a clock divided by 3 to 5 by using a bit leaking request signal and a +/- code signal. The received BLC clock (17.920 MHz for TU12 and 13.312 for TU11) is received. MHz) outputs a clock divided by 4 when there is no bit leaking request signal. However, if there is a bit leaking request signal, the division ratio is determined according to the +/- sign signal supplied from the stuffing and burst detection circuit 15. When a + sign signal is generated, a clock divided by 5 is output to push 1/8 bit. Bit-leaking is performed, and when a code signal is input, bit-leaking is performed to pull 1/8 bit by performing three divisions according to the leaking request signal. The main counter 16 is composed of a D-type flip-flop and a logic circuit.

4 is a detailed configuration of the stuffing and burst detection circuit 15 of FIG. 3, 31 is a stuffing detection circuit, 32 is a homogeneous and heterogeneous burst detection circuit, and 33 is a burst and leaking code change determination circuit, respectively.

The stuffing and burst detection circuit 15 is composed of a stuffing detection circuit 31, a homogeneous and heterogeneous burst detection circuit 32, and a burst and leaking code change determination circuit 33 as shown in FIG. .

The stuffing detection circuit 31 outputs counting start and end signals to the bit leaking interval counter 13, and outputs +/− sign signals to the main counter 16 to JK flip-flops and logic circuits. It is composed. When the counting start and end signals are in the '0' state, the counting end and stop are shown. In the '1' state, the counting start and counting enable are indicated. Therefore, in the initial state, this signal is maintained in the state of '0', and is output from the state of '0' to '1' according to the occurrence of positive or boosting. The state of '1' is returned to the '0' state by the leaking completion signal. The +/- sign signal outputs the positive stuffing generator '0' state to perform 5 division of the main counter 16, and if boosting occurs, outputs the state of the main counter 16 by '1' state. Allow three minutes to dispense.

The homogeneous and heterogeneous burst detection circuit outputs a " 1 " state to a homogeneous burst signal when a burst of the same polarity occurs, and outputs a " 1 " state to a heterogeneous burst signal when a burst of another polarity indicates a homogeneous and heterogeneous burst occurrence. do. This signal is also reset by the leaking completion signal of the bit leaking request signal counter 14. The homogeneous and heterogeneous burst detection circuit 32 is composed of a D flip-flop and a logic circuit.

The burst and leaking code change determination circuit 33 receives the +/- code signal, the homogeneous burst signal, and the heterogeneous burst signal and performs the same as the current state unless the code and the polarity change are required according to the carry signal Cn + 1. When the code and polarity change request are made, the +/- code signal is changed to '1' state when the state of '0' state is '0' state and is changed to '0' state when it is '1' state and then output as +/- code signal. In addition, the homogeneous burst signal is a heterogeneous burst signal, and the heterogeneous burst signal is converted into a homogeneous burst signal and output. The sign and polarity change request are generated when the heterogeneous burst signal becomes " 1 " and the carry signal Cn + 1 coming from the bit leaking request signal counter becomes " 1 " state. The output value used for the circuit is reset to the initial state by the leaking completion signal. The burst and leaking code change determination circuit 33 is composed of a D-type flip-flop and a logic circuit.

5 is a detailed configuration of the bit leaking request signal counter 14 of FIG. 3, where 41 is an operator control circuit, 42 is an operator, and 43 is a counter.

The bit leaking request signal counter 14 is composed of an operator control circuit 41, an operator 42, and a counter 43, as shown in FIG.

The operator control circuit 41 outputs an operator control signal for controlling the operation of the operator 42 by inputting burst information from the stuffing and burst detection circuit 15, and the controlled operator 42 outputs the operator. It calculates using the output value of the counter 43 and the fixed value # 64k. The calculated count value is counted down by the bit leaking request signal coming from the bit leaking interval counter by loading the counter 43, and generating a leaking completion signal when the value becomes '0' state.

6 is a detection state of the pointer adjustment jitter according to the present invention, (A) shows the difference between the read and write clock, and (B) shows the pointer adjustment jitter which has been bit-leaked. Shows a decrease in adjustment jitter.

According to the present invention configured and operated as described above, when 8UI byte stuffing is generated, the stuffing is processed in units of 1/8 bits according to the enhanced bit-leaking operation to satisfy the output jitter specification and pointer adjustment of a conventional synchronous multi-device. Compared with the jitter reduction circuit (Application Nos. 90-11804), it is possible to eliminate the difficulties and cost savings due to the elimination of the PLL.

Claims (4)

TU pointer adjustment jitter reduction circuit to reduce pointer adjustment jitter generated during byte stuffing process that converts TUin (Tributary Unit in: n = 1,2) signal into VCin (Virtual Container in: n = 1,2) signal In the: elastic buffer means (2) for reading and writing TUin received data and VCin received data, the first address generating means (1) connected to the elastic buffer means (2) for generating a write address by a write clock, The second address generating means 4 connected to the elastic buffer means 2 to generate a read address by a read clock, frame clock, positive / negative stuffing information, and BLC (Bit Leaking Control Clock) are inputted. Bit-leaking processing means (3) for calculating a generation interval and extracting a bit-leaking interval, and said bit-leaking processing means (3) connected to said bit-leaking processing means (3) and an address generating means (4). Output from That divides the clock consists of a frequency division means (5) to be supplied to the address generating means (4) decreases TU pointer adjustment, characterized jitter circuit. The bit leaking interval generating means (11) and the bit leaking interval generating means (12) according to claim 1, characterized in that the bit leaking processing means (3) receives the clock to generate an interval to be bit leaked. A bit leaking interval selecting means 12 connected to the bit leaking interval selecting means 12 to determine a bit leaking interval, and a bit leaking interval received from the bit leaking interval selecting means 12. A bit leaking interval counting means 13 for receiving a value and counting a value and generating a bit leaking request signal; Stuffing and burst detection means 15 for supplying a counting start and end signal to the counting means 13 to control the bit leaking interval counting means 13 and to detect homogeneous and heterogeneous burst signals with +/- sign signals, Stuffing with the bit leaking interval counting means (13) And detecting the completion of the bit leaking operation by inputting the bit leaking request signal and the burst information to output the leaking completion signal and the carry signal to the stuffing and burst detection means 15. It is connected to the bit leaking request signal counting means 14 and the bit leaking interval counting means 13 and the stuffing and burst detecting means 15, and divided according to the bit leaking request signal and the +/- code signal. TU pointer adjustment jitter reduction circuit, characterized in that it comprises a main counting means (16) for generating a clock. 3. The method according to claim 2, wherein the stuffing and burst detecting means (15) inputs the leaking completion signal of the bit leaking request signal counting means (14) and the positive / minus stuffing information to the bit leaking interval counting means ( 13) a stuffing detecting means 31 for generating the counting start and end signals outputted to the +/- sign signal and the biting completion request signal counting means 14 and the positive / sub stuffing; Homogeneous and heterogeneous burst detection means 32 for detecting the homogeneous and heterogeneous burst signals by inputting information, and homogeneous and heterogeneous burst detection with the bit leaking request signal counting means 14 and the stuffing detection means 31. TU pointer, characterized in that it is connected to the means 32 and comprises burst and leaking code change determining means 33 for changing the sign and polarity of the homogeneous and heterogeneous burst signals with the carry signal and the +/- code signal. Adjustable jitter reduction circuit. 3. The apparatus according to claim 2, wherein said bit leaking request signal counting means (14) is connected to said operator control means (41) and said operator control means (41) for outputting an operator control signal with said homogeneous and heterogeneous burst information as inputs. And a calculation means 42 for calculating using a fixed value ＂64＂ according to the arithmetic control signal of the arithmetic controller control means 41, and the arithmetic means 42 to the output of the arithmetic means 42. And counting means 43 which outputs a leaking completion signal and outputs a counting value to the calculating means 42 when it is loaded by the bit-leaking request signal and down-counted by the bit-leaking request signal. TU pointer adjustment jitter reduction circuit.