JP2952935B2 - Asynchronous data transmission system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an asynchronous data transmission system for transmitting asynchronous data using a synchronous network.

[Conventional technology]

In the digital transmission system, usually, a plurality of low-order group digital signals are multiplexed in a time-division manner to create a high-order group digital signal, which is transmitted to a distant place.
Then, on the receiving side, the original low-order group digital signal is obtained by separating the signal. For this purpose, the following two conditions are required.

(I) On the transmitting side, the multiplexed low-order group signals have completely the same speed.

(R) To know the exact position of each channel from the multiplexed signal to correctly separate it on the receiving side.

In the current communication network, each transmitting device has a clock source, and transmits a low-order group signal in synchronization with an independent clock frequency. Therefore, in order to satisfy the condition (i), the transmitting side needs to synchronize the bits of each low-order group signal before multiplexing. Also,
In order to satisfy the condition (b), the receiving side synchronizes frames as a multi-channel code group.

Of these, the bit synchronization (i) is generally performed using a stuff synchronization method. In this method, all the low-order group signals can be placed on a common frequency by reading out the input signal with a clock slightly faster than any low-order group signal. In this case, the phase difference between the read clock and the low-order group signal clock gradually increases, so that there is sometimes no data to be read. Therefore, compensation is performed by inserting a so-called stuff pulse at this position.

FIG. 4 shows a data transmission system using such a stuff synchronization system.

In this figure, a transmission device 101 is a transmission line 1 constituting an asynchronous network.
02 is connected to the receiving device 103. This transmitting device 1
In 01, an elastic store 104 is provided as a buffer memory having a FIFO (first-in first-out) function of about several bytes, and an input clock 105 of a frequency f _i and input data 106 synchronized with the input clock 105 are input. .
This input clock 105 is also input to the phase comparator 108 via the write counter 107.

Also, this device is provided with a clock oscillator 109,
And it outputs a read clock 111 of frequency f _0. The read clock 111 is stored in the elastic store 10
4, and to the stuff information generating circuit 113, and also to the phase comparator 108 via the read counter 114. The frequency f _{0 of the} read clock 111
Has a value slightly larger than the frequency f _i of the input clock 105, and is set such that the average stuffing ratio becomes an appropriate value. Here, the average stuff rate is a numerical value indicating the average number of stuffs performed in one frame.

An output side of the phase comparator 108 is connected to one of two inputs of the adder 116 via a stuff information generating circuit 113. The other input of the adder 116 is connected to the elastic store 104, and the output side is connected to the transmission line 102 via the frame synchronization signal multiplexing circuit 117.

On the other hand, the receiving apparatus 103 includes a frame synchronization signal detecting circuit 121.
Is provided, and data is input from the transmission line 102. The output side of the frame synchronization signal detection circuit 121 is branched into two,
2. It is connected to the stuff information termination circuit 123. The output side of this stuff information termination circuit 123 is a destuff control circuit 1
After passing through 24, it is branched into two, one to the elastic store 122 and the other to the phase comparator via the write counter 127.
It is connected to one of the 128 inputs. The destuffing control circuit 124, a clock 125 of frequency f ₀ extracted from the received data are inputted.

The output side of the phase comparator 128 is connected to a phase locked loop (PLL) circuit 135 including a digital-to-analog converter (D / A) 132, a low-pass filter (LPF) 133, and a voltage controlled oscillator (VCO). I have. The output of the phase locked loop circuit 135 is output as an output clock 137 and is input to a phase comparator 128 via a read counter 139. The output clock 137 is also input to the elastic store 122, and data read out in synchronization with the output clock 137 is output as output data 138.

The operation of the conventional data transmission system using the stuff synchronization scheme configured as described above will be described.

The input data 106 is written to the elastic store 104 in synchronization with the input clock 105 having the frequency f _i . The data written in the elastic store 104 is the read clock 1 of the frequency f ₀ output from the clock oscillator 109.
The data is read out in synchronization with 11 and input to the adder 116.

On the other hand, the number of clock pulses of the input clock 105 and the read clock 111 are counted by the write counter 107 and the read counter 114, respectively.
Is input to The phase comparator compares these count values, and outputs a stuff request signal 112 when the phase difference exceeds 1 UI. In response to this, the stuff information generating circuit 113 generates a stuff pulse 115, and the adder 11
Enter 6 As a result, in the adder 116, a stuff pulse is inserted at the corresponding timing position of the data read from the elastic store 104. Then, the stuffed data 118 is multiplexed with a frame synchronization signal by the frame synchronization signal multiplexing circuit 117 and then transmitted to the transmission line 102.

The frame synchronization signal is first detected by the frame synchronization signal detection circuit 121 from the data input to the reception device 103, and the frame synchronization is achieved. Then, when the position of the stuff pulse is detected by the stuff information termination circuit 123, a destuff request signal 131 is output. As a result, the destuff control circuit 124 performs destuffing for removing the stuff pulse. As a result, a destuffed write clock 126 is generated, and data 129 is written to the elastic store 122 in synchronization with this.

The write clock 126 is also input to the write counter 127, and the number of clock pulses is counted. This count value is input to the phase comparator 128 together with the read pulse count value output from the read counter 137, and the phase difference is extracted. This phase difference information is stored in the digital-to-analog converter 132 of the PLL circuit 135.
Is converted to an analog quantity by a low-pass filter 133 to remove high-frequency components.
Is input to From the voltage controlled oscillator 134, a clock having a frequency proportional to the input voltage is output and input to the read counter 137.

In this way, the output clock 139 (frequency fi) that follows the frequency of the write clock 126 is output by the loop control of the PLL circuit 135, and reading from the elastic store 122 is performed in synchronization with this. Output data 138
Will be output as

In the stuff synchronous communication system in the conventional asynchronous network as described above, the frequency of the read clock is selected so that the average stuff ratio is appropriate, and the PLL is provided to the receiving device side.
By providing a circuit and reproducing the read clock, so-called stuff jitter can be reduced. This makes it possible to stabilize the cycle of inserting stuff pulses. For example, when one stuff pulse is inserted for every 20 bits of input data, there is a fluctuation of about ± 1 bit, but the average In this case, a stuff pulse is inserted every 20 bits.

Such a conventional stuff synchronous transmission system corresponds to a relatively low clock frequency. However, in recent years, with the advancement of information in society, higher-speed data transmission has been required, and naturally, the clock frequency used has been higher. For this reason, it is becoming difficult to cope with the conventional stuff synchronous data transmission system.

Therefore, recently, a new synchronous network data transmission system has been proposed, and research and development have been advanced. In this system, communication is attempted by synchronizing the entire system, Japan, and the whole world with one clock. In this new synchronous network data transmission system,
All devices in the system operate in synchronization with a common clock frequency generated by a common clock source (DCS).

[Problems to be solved by the invention]

With the transition to such a new system, it is necessary to use existing devices transiently. In this case, since these devices are asynchronous with respect to the common clock, the clock of the input data matches the frequency of the common clock by providing a clock source for generating a clock having the same frequency as the common clock frequency in each device. Need to be done. However, in practice, these cannot be completely matched, so that there is a slight frequency shift between the read clock and the write clock to the elastic store. Since the frequency shift is slight, if the common clock is simply used as the read clock, the cycle of inserting the stuff pulse becomes long, and some frames are not inserted at all. In addition, the phase comparator does not output a stuff request unless the count difference between the write pulse and the read pulse becomes equal to or more than one clock. And the average staff ratio may become zero. Therefore, the so-called latency jitter becomes the worst value of 1 UIp-p (unit interval peak-to-peak), and data is transmitted with a phase shift of almost 1 bit. You will not be able to receive correctly.

As described above, when the asynchronous data of the existing device is transmitted using the new synchronous network, there is a disadvantage that the conventional stuff synchronous method is not practical.

Therefore, an object of the present invention is to provide an asynchronous data transmission system capable of transmitting asynchronous data of an existing device using a synchronous network.

[Means for solving the problem]

According to the first aspect of the present invention, (i) the number of clocks per frame at a predetermined cycle is determined based on the common clock in a synchronous communication network that performs communication by synchronizing the entire network with one common clock frequency. First pulse generating means for generating a clock which is coprime to the number of clocks per frame of the synchronized input clock; (ii)
When the phase difference between the clock output from the first pulse generating means and the input clock exceeds a predetermined threshold value, clock stuff information multiplexing for multiplexing clock stuff information for notifying the fact to output data. Means (ii)
i) a transmission path for transmitting the multiplexed data transmitted from the clock stuff information multiplexing means, and (iv) a second pulse generating means for generating a clock having the same frequency as the clock output from the first pulse generating means. (V) clock destuffing means for destuffing the clock output from the second pulse generating means when clock stuff information is detected in the data separated from the multiplexed data received from the transmission line. An asynchronous data transmission system is provided.

According to the first aspect of the present invention, the number of clocks per frame at a predetermined period is relatively prime to the number of clocks per frame of the input clock synchronized with the input data, based on the clock of the synchronous network. A clock with a frequency slightly higher than the frequency of the clock is generated, and the clock stuff control is performed. Further, data destuffing control is performed by using a stuff controlled clock.

According to the second aspect of the present invention, (a) (i) a data read circuit for reading input data written in a buffer in synchronization with an input clock with a read clock synchronized with a network synchronization signal which is a common clock of the entire synchronization network. (Ii) a data phase comparison circuit for comparing the number of data read by the data read circuit with the number of data written to the buffer for each frame of a predetermined period, and (iii) the data phase comparison circuit. When the phase difference of one clock or more is detected by the circuit, the read timing of the data read circuit is set to 1
A data stuff control circuit for performing data stuff control for shifting by a clock, and (iv) a notification that data stuff control has been performed by the data stuff control circuit when a phase difference of one clock or more is detected by the data phase comparison circuit. A data stuff information multiplexing circuit for multiplexing data stuff information to be read out by the data readout circuit, and a phase locked loop circuit for generating a clock having a frequency that is an integral multiple of the input clock frequency. (Vi) a clock synchronized with a basic clock that counts the number of bytes accommodated in one frame, wherein the number of clocks per frame is a fixed number larger than the number per frame at a clock frequency that is an integral multiple of the input clock frequency. A pulse generating circuit for generating a pulse, and (vii) an output from the pulse generating circuit. (Viii) when a phase difference equal to or greater than a predetermined threshold value is detected by the clock phase comparison circuit, (B) a transmission device comprising a clock stuff information multiplexing circuit for multiplexing clock stuff information for notification to data read by the data reading circuit;
(I) The original reception data of the channel data separated from the multiplexed data transmitted from the transmission device via the synchronous network is written by the write clock having the same frequency as the read clock in the data read circuit of the reception device. A data write circuit for writing data into a buffer; (ii) a data stuff information detection circuit for detecting data stuff information from channel data; and (iii) data writing when data stuff information is detected by the data stuff information detection circuit. A data destuff control circuit for performing data destuff control for shifting the write timing by one clock by the circuit;
(Iv) a clock stuff information detecting circuit for detecting clock stuff information from channel data, (v) a pulse generating circuit for generating a clock pulse having the same frequency as the clock pulse generated by the pulse generating circuit of the transmitting device,
i) a clock destuff control circuit that executes clock destuff control on a clock output from the pulse generation circuit when the clock stuff information detection circuit detects clock stuff information; and (vii) the clock destuff control circuit. And (viii) generating a read clock for reading the data written in the buffer, following the clock output from the frequency divider. An asynchronous data transmission system is provided with a receiving device including a phase locked loop circuit.

According to the second aspect of the present invention, when the phase difference between the clocks output from the phase locked loop and the pulse generating means in the transmitting device is equal to or larger than a predetermined threshold, the clock stuff information is multiplexed with the data and transmitted. . On the other hand, on the receiver side, when clock stuff information is detected in the separated data, the output clock from the pulse generating means is destuffed and then divided, and the read clock is generated by further smoothing. I decided to.

According to the third aspect of the present invention, (a) (i) a data read circuit for reading input data written in a buffer in synchronization with an input clock with a read clock synchronized with a network synchronization signal which is a common clock of the entire synchronization network. (Ii) a data phase comparison circuit for comparing the number of data read by the data read circuit with the number of data written to the buffer for each frame of a predetermined period, and (iii) the data phase comparison circuit. When the phase difference of one clock or more is detected by the circuit, the read timing of the data read circuit is set to 1
A data stuff control circuit for performing data stuff control for shifting by a clock, and (iv) a notification that data stuff control has been performed by the data stuff control circuit when a phase difference of one clock or more is detected by the data phase comparison circuit. (V) a data stuff information multiplexing circuit for multiplexing data stuffing information to data read by the data reading circuit, and (v) a basic clock for counting the number of bytes contained in one frame. A pulse generation circuit for generating a clock pulse whose number of clocks is larger by a fixed number than the number per clock of a clock having a frequency that is an integral multiple of the input clock;
A frequency dividing circuit for dividing the clock output from the clock pulse generating circuit by a factor of 1; and (vii) a clock phase comparing circuit for comparing the phase of the clock output from the frequency dividing circuit with the input signal clock. And (viii) a clock for multiplexing, when the clock phase comparison circuit detects a phase difference of one clock or more, clock stuff information for notifying the detection of the phase difference to the data read by the data read circuit. A transmission device comprising a stuff information multiplexing circuit, and (b) (i) the original reception data of the channel data separated from the multiplexed data transmitted from the transmission device via the synchronous network, by the transmission device data. A data write circuit for writing data to the buffer with a write clock having the same frequency as the read clock in the read circuit; Data stuff information detection circuit for detecting data stuff information, and (iii) data destuff control for shifting the write timing of the data writing circuit by one clock when the data stuff information is detected by the data stuff information detection circuit. A data stuff control circuit, and (iv) a clock stuff information detecting circuit for detecting clock stuff information from channel data.
(V) a pulse generation circuit that generates a clock pulse having the same frequency as the clock pulse generated by the pulse generation circuit of the transmission device; and (vi) a clock output from the pulse generation circuit that is divided by an integer. When the clock stuff information is detected by the frequency dividing circuit and the (vii) clock tap information detecting circuit, the output clock from the frequency dividing circuit is set to 1
(Viii) a clock destuffing control circuit for performing clock destuffing control by shifting the clock, and (viii) generating a read clock for following the clock destuffed by the clock destuffing control circuit and reading out the data written in the buffer. An asynchronous data transmission system is provided with a receiving device including a phase locked loop circuit.

According to the third aspect of the present invention, when the phase difference between the input signal clock and the clock output from the frequency divider becomes equal to or more than one clock on the transmitting device side, the clock stuff information is multiplexed with the data. Send out. On the other hand, on the receiving apparatus side, when clock stuff information is detected in the data separated from the reception, the output clock from the frequency dividing means is destuffed and then smoothed to generate a read clock.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 shows an asynchronous data transmission system according to a first embodiment of the present invention. In this figure, a transmitting device 11 is connected to a receiving device 13 by a synchronous network 12. Each of these devices provided with a clock generator 15, and outputs a common clock 17 of frequency f _s which is supplied from the data clock source (DCS) 14 is a common clock source of the entire synchronous network I have.

The transmission device 11 is provided with an elastic store 18 so that an input clock 19 having a frequency f _i and input data 21 synchronized with the input clock 19 are input. This input clock 19 is supplied to a first phase comparator via a write counter 22.
The signal is input to one of the inputs of a second phase comparator 25 via a phase locked loop (hereinafter, referred to as a PLL) circuit 24.

Common clock 17 of frequency f _s that is output from the clock generator 15 is input to the first, second pulse generator 27. The first pulse generator 27 is connected to the elastic store 18 via the data stuff control circuit 29, and the first pulse comparator 27 is connected to the first phase comparator via the read counter 31.
Connected to the other input of 23.

The output side of the first phase comparator 23 is connected to one of two inputs of an adder 34 via a data stuff information generation circuit 33, and is also connected to a data stuff control circuit 29. The other input of the adder 34 is connected to the elastic store 18, and the output side is connected to the synchronization network 12 via the clock stuff multiplexing circuit 35 and the frame synchronization signal multiplexing circuit 36.

The second pulse generator 28 is connected to the other input of the second phase comparator 25. The output side of the phase comparator 25 is connected to a clock stuff multiplexing circuit 35 via a clock stuff information generating circuit 38.

On the other hand, the receiving device 13 is provided with a frame synchronization signal separation circuit 41 so that data received from the synchronization network 12 is input. The output side of the frame synchronization signal separation circuit 41 is branched into three, each of which is an elastic store.
42, a data stuff information termination circuit 43, and a clock stuff information termination circuit 44.

Common clock 17 of frequency f _s that is output from the clock generator 16, the third, is input to the fourth pulse generator 46 and 47. The third pulse generator 46 is connected to the elastic store 42 via the data destuff control circuit 49. The output side of the data stuff information termination circuit 43 is connected to the data destuff control circuit 49.

The fourth pulse generator 47 is connected to the PLL circuit 53 via the clock destuff control circuit 51 and the frequency dividing circuit 52. The output side of the clock stuff information termination circuit 44 is connected to the clock destuff control circuit 51. Then, the PLL circuit 53, is output the output clock 55 of frequency f _i, in synchronization with this, so that the output data 56 read from the elastic store 42.

Next, the operation of the asynchronous data transmission system configured as described above will be described.

The input data 21 is written to the elastic store 18 in synchronization with the input clock 19 having the frequency f _i . The data written to the elastic store 18 is read out in synchronism with the read clock 57 generated by the first pulse generator 27 on the basis of a common clock 17 of frequency f _s, the adder 34
Is input to The number of bits per frame of the read clock 57 is obtained by adding one bit for stuff control to the number of bits per frame of the input data 21.

On the other hand, the number of clock pulses of the input clock 19 and the read clock 57 are counted by the write counter 22 and the read counter 31, respectively, and the respective count values are input to the phase comparator 23. This phase comparator 23 compares these count values,
Stuff request signal 58 when phase difference exceeds 1 UI
Is output. Data stuff control circuit 29 receiving this
Performs control to shift reading by one clock, and
The data stuff information generation circuit 33 generates data stuff information indicating that data stuff has been performed,
Enter 34.

Then, the adder 34 adds the data read from the elastic store 18 and the data stuff information. This data stuff information is added to a previously reserved bit position in one frame, and this bit is set to “0”.
The presence or absence of data staff is displayed depending on whether it is "1" or "1".

The operation up to this point is almost the same as that of the conventional example. If the same control is performed on the receiving apparatus side, the waiting time jitter becomes 1 UIp-p because the average stuff ratio is also almost 0. Problems will arise.

However, in this embodiment, this problem is solved by providing an additional circuit for performing clock stuff as described below.

FIG. 2 shows in detail an additional circuit for performing clock stuff control of the asynchronous data transmission system of FIG. In this figure, the PLL circuit 24 is shown in particular detail, and the reference numerals assigned to the other parts correspond to FIG.

The PLL circuit 24 includes a phase comparator 61, and the input clock 19 is input to one of its inputs. Its output side is connected to a frequency dividing circuit 65 via a digital / analog converter 62, a low-pass filter 63, and a voltage controlled oscillator 64, and also to the phase comparator 25. The output side of the frequency dividing circuit 65 is connected to the other input of the phase comparator 61. The voltage controlled oscillator 64 is the frequency of the input clock
A clock 66 having a frequency N times f _i is output, and a clock having a frequency of Nf _i is output accurately by further loop-controlling this clock. Here, N indicates an arbitrary integer. Therefore, one of this clock
The number of clocks per frame is given by the following equation (1).
Here, the frame period is _Tf .

Nf _i T _f (1) Here, the expression (1) satisfies the following expression (2).

Nf _i T _f <f _s T _f ... (2) Further, the pulse generator 28 _outputs the common clock 17 of the frequency f _s.
The number of clocks per frame is based on
, A clock 67 which is n clocks greater than the number of clocks output per frame per frame is output. 1 of this clock 67
The number P _s per frame is as following equation (3). Here, n is a positive integer.

P _s = Nf _{i Tf} + n (3) As a result, the phase difference between the output clock 66 of the PLL circuit 24 and the clock 67 output from the pulse generator 28 gradually increases, and the average stuff ratio is not zero.

The second phase comparator 25 compares the phases of the clocks 66 and 67, and outputs a clock stuff request signal 68 when the phase difference exceeds a predetermined threshold value of M bits. In response to this, the clock stuff information generating circuit 38 outputs one bit of clock stuff information indicating that the clock stuff is to be performed, and the clock stuff multiplexing circuit 35 (hereinafter, FIG. 1)
Is input to The clock stuff information is multiplexed by the clock stuff multiplexing circuit 35 with the data from the adder 34, and further multiplexed with the frame synchronization signal by the frame synchronization signal multiplexing circuit 36 before being sent out onto the synchronization network 12. . Therefore, the average staff rate of clock staff S _r
Is given by the following equation (4).

S _r = n / M (4) On the other hand, the data input to the receiving device 13 from the synchronization network 12 is first subjected to the detection of the frame synchronization signal by the frame synchronization signal separation circuit 41, and then to the target channel data 71 And separated.

In the data stuff information termination circuit 43, the channel data
When the data stuff information is detected from 71, a data destuff request signal 72 is output. In response to this, the data destuff control circuit 49 performs destuff control to shift the write clock 73 output from the pulse generator 46 by one clock. Here, the number of clocks per frame of the write clock 73 is the same as that of the read clock 57 output from the first pulse generator 27 of the transmission device 11. In this manner, the original received data portion of the channel data 71 is written to the elastic store 42 in synchronization with the destuff-controlled write clock 73.

The channel data 71 is also input to the clock stuff information termination circuit 44, and when the clock stuff information is detected, a clock destuff request signal 75 is output. In response to this, the clock destuff control circuit 51 destuffs the clock 76 output from the fourth pulse generator 47. The number of clocks per frame of the clock 76 is the same as that of the second pulse generator 28 of the transmitting device 11.
This is the number shown in equation (3). Therefore, the number of clocks per frame of the clock output from the clock destuffing control circuit 51 by the clock destuffing control is as shown in the equation (1). This is achieved by dividing the frequency by N
A clock whose frequency is divided by a factor of 1 and the number of clocks per frame becomes the following equation (5), that is, an average frequency
The clock of f _i is input to the PLL circuit 53.

f _i T _f (5) As shown in FIG. 2, the PLL circuit 53 includes a phase comparator 78, a digital-to-analog converter 79, a low-pass filter 81, and a voltage-controlled oscillator 82. In accordance with the clock 77, the control is performed to reduce the latency jitter included in the clock 77. This allows the input clock 19
An output clock 55 having the same frequency f _i and having little latency jitter is output. This output clock 55 is output to the outside of the device as it is, and
42 (hereinafter FIG. 1). In synchronization with this, data is read from the elastic store 42 and output as output data 56.

In the above explanation, for example, 2.048Mbps (Megabit / sec)
Considering the case where asynchronous data is transmitted over a new synchronous network, various parameters are as shown in the following equations (6) to (9).

f _i = 2.048 Mbps (6) f _s = 19.44 MHz (7) T _f = 125 μs (8) n = 1 (9) and one frame of the common clock 17 having the frequency f _s the number of clocks P _c is a value such as the following equation (10).

P _c = f _s T _f = 2430 (10) Therefore, the integer N satisfying the expression (2) is 9, so that
Equation (3) takes the value of the following equation (11).

P _s = 2305 (11) That is, the number of clocks output from the second pulse generator 28 per frame may be set to 2305. At this time, assuming that the clock stuff threshold M is 13, the average stuff ratio becomes the value of the following equation (12) from the equation (4).

S _r = 1/13 = 0.0769 (12) Next, a second embodiment of the present invention will be described in detail.

FIG. 3 shows an asynchronous data transmission system according to a second embodiment of the present invention.

In this figure, the same parts as those in the first embodiment (FIG. 1) are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In this system, the input clock (frequency f _i ) to the transmission device 11 is directly input to one of the inputs of the phase comparator 25. The other input of the phase comparator 25 is connected to a frequency divider 81
The via is connected to the second pulse generator 28 is input a common clock 17 of frequency f _s. Other configurations are the same as those of the first embodiment (FIG. 1).

Also, the receiving apparatus 13, a fourth pulse generator 17 which is input a common clock 17 of frequency f _s is connected to the PLL circuit 53 via a frequency divider 52 and the clock destuffing control circuit 51 . Other configurations are the same as those of the first embodiment (FIG. 1).

Next, the operation of the asynchronous data transmission system configured as described above will be described. However, the stuff control of the input data 21, that is, the portion related to the data stuff control is the same as that of the first embodiment, and the explanation is omitted here.

The second pulse generator 28 of the transmitter 11, based on the common clock 17 of frequency f _s, the number of clocks per one frame, than the number of 1 frame per N times the frequency clock of the input clock 19 A clock 67 which is n clocks higher is output. That is, the number P _s per frame of the clock 67 is then shown again (3) it becomes as expression. Where n
Is a positive integer.

P _s = Nf _i T _i + n (3) This clock 67 is frequency-divided by the frequency dividing circuit 81 to 1 / N and input to the phase comparator 25. The number of clocks per frame of the divided clock 82 is expressed by the following (13)
It takes the value shown in the equation.

f _i + T _f + n / N (13) As a result, the phase difference between the input clock 19 and the clock 82 output from the frequency divider 81 gradually increases by (n / N) for each frame. That is, this is the average staff rate.

The second phase comparator 25 compares the phases of the locks 19, 82,
The clock stuff request signal 68 is output when the phase difference becomes 1 UI or more. The clock stuff information generating circuit 38 receives this and outputs one bit of clock stuff information indicating that clock stuff is to be performed, and inputs it to the clock stuff multiplexing circuit 35.

Thereafter, the multiplexed data is sent out onto the synchronous network 12 by the same operation as in the first embodiment.

Also in the receiving device 13, the channel data 71 separated by the same operation as in the embodiment is input to the data stuff information terminating circuit 43, the elastic store 42, and the clock stuff information terminating circuit 44. Here, the description of the operation regarding the data stuff control is omitted.

The clock stuff information termination circuit 44 detects the clock stuff information from the input channel data 71,
A clock destuff request signal 75 is output and supplied to the clock destuff control circuit 51.

The fourth pulse generator 47 outputs a clock 76 in which the number of clocks per frame is the same as that of the second pulse generator 28 of the transmitting device 11, as shown in equation (3). This clock 76 is frequency-divided by the frequency dividing circuit 52 to 1 / N.
The number of clocks per frame is input to the clock destuff control circuit 51 as the clocks 84 of the number shown in the equation (13). As a result, the clock destuff control circuit 51
Performs destuffing of the clock 84 at the timing when the clock destuff request signal 75 is received. Accordingly, the number of clocks per frame of the clock 85 output from the clock destuff control circuit 51 is as shown in the following expression (5).

f _i T _f (5) That is, a clock having the average frequency f _i is input to the PLL circuit 53.

In the PLL circuit 53, the same control as in the first embodiment (FIGS. 1 and 2) is performed, and the output clock having the same frequency f _i as the input clock 19 and having a small latency jitter is used.
55 is output. The output clock 55 is output to the outside of the apparatus as it is, and is also input to the elastic store 42. Then, data is read from the elastic store 42 in synchronization with the output clock 55, and is output as output data 56.

In this way, the asynchronous network transmission of the asynchronous data with little stuff jitter is performed.

〔The invention's effect〕

As described above, according to the first aspect of the present invention,
Since clock stuff control is performed separately from data stuff control, there is an effect that asynchronous data transmission by a synchronous network, which has been difficult in the past, can be realized with low latency jitter.

According to the second and third aspects of the present invention,
Since the average stuff ratio of the clock stuff of the asynchronous data can be selected to some extent, there is an effect that the circuit design for reducing the latency jitter becomes easy.

[Brief description of the drawings]

1 to 3 are diagrams for explaining an embodiment of the present invention. FIG. 1 is a block diagram showing an asynchronous data transmission system in the first embodiment, and FIG. 2 is a block diagram of FIG. FIG. 3 is a block diagram showing a main part, FIG. 3 is a block diagram showing an asynchronous data transmission system in a second embodiment, and FIG. 4 is a block diagram showing a conventional stuff synchronous data transmission system. 11 ... transmitting device, 12 ... synchronous network, 13 ... receiving device, 14 ... data clock source, 15, 16 ... clock generator, 17 ... common clock, 19 ... input clock, 21 ... input Data, 24 PLL circuit, 25 Phase comparator, 28, 47 Pulse generator, 38 Clock stuff information generation circuit, 51 Clock destuff control circuit, 52, 81 Frequency divider circuit , 53… PLL circuit, 55… output clock, 56… output data.

Claims (3)

(57) [Claims] 1. A synchronous communication network for performing communication by synchronizing the entire network to one common clock frequency, and based on the common clock, the number of clocks per frame of a predetermined period is set to one of the input clocks synchronized with the input data. First pulse generating means for generating a clock which is relatively prime to the number of clocks per frame; and a phase difference between the clock output from the first pulse generating means and the input clock exceeds a predetermined threshold. When
Clock stuff information multiplexing means for multiplexing clock stuff information for notifying the fact to output data; a transmission path for transmitting multiplexed data sent from the clock stuff information multiplexing means; and the first pulse Second pulse generating means for generating a clock having the same frequency as the clock output from the generating means, and when the clock stuff information is detected in data separated from the multiplexed data received from the transmission line, the second pulse generating means Clock destuffing means for destuffing a clock output from the pulse generating means. 2. A data read circuit for reading input data written in a buffer in synchronization with an input clock with a read clock synchronized with a network synchronization signal which is a common clock of the entire synchronization network; A data phase comparison circuit for comparing the number of data written to the buffer and the number of data written to the buffer for each frame of a predetermined period; and when a phase difference of one clock or more is detected by the data phase comparison circuit. A data stuff control circuit for performing a data stuff control for shifting the read timing of the data read circuit by one clock, and a data stuff control circuit for detecting a phase difference of one clock or more by the data phase comparison circuit. Data stuff information for notifying that data stuff control has been performed, A data stuff information multiplexing circuit that multiplexes the data read by the output circuit, a phase locked loop circuit that generates a clock having a frequency that is an integer multiple of the input clock frequency, A pulse generation circuit for generating a clock pulse in synchronization with the clock, wherein the number of clocks per frame is a fixed number greater than the number per frame at a clock frequency that is an integral multiple of the input clock frequency; A clock phase comparator for comparing the phase of the output clock with the clock output from the phase-locked loop circuit; and when the clock phase comparator detects a phase difference equal to or greater than a predetermined threshold, notifies the effect. Clock stuff information to be read out by the data readout circuit. A transmission unit comprising a clock stuff information multiplexing circuit for multiplexing the received data, and the transmission device, which transmits the original reception data of the channel data separated from the multiplexed data transmitted from the transmission unit via the synchronization network, to the transmission unit. A data write circuit for writing to a buffer with a write clock having the same frequency as the read clock in the data read circuit; a data stuff information detection circuit for detecting the data stuff information from the channel data; A data destuff control circuit for performing data destuff control for shifting the write timing by one clock by the data writing circuit when the stuff information is detected; and a clock stuff information detection for detecting the clock stuff information from the channel data. A circuit; and the transmitting device. A pulse generation circuit that generates a clock pulse having the same frequency as the clock pulse generated by the pulse generation circuit; and a clock destuff control for a clock output from the pulse generation circuit. A clock destuffing control circuit to be executed when detected, a frequency dividing circuit for dividing a clock output from the clock destuffing control circuit into an integer, and following a clock output from the frequency dividing circuit A receiving device comprising a phase locked loop circuit for generating a read clock for reading data written in the buffer. 3. A data read circuit for reading input data written in a buffer in synchronization with an input clock with a read clock synchronized with a network synchronization signal which is a common clock of the entire synchronization network; A data phase comparison circuit for comparing the number of data written to the buffer and the number of data written to the buffer for each frame of a predetermined period; and when a phase difference of one clock or more is detected by the data phase comparison circuit. A data stuff control circuit for performing a data stuff control for shifting the read timing of the data read circuit by one clock, and a data stuff control circuit for detecting a phase difference of one clock or more by the data phase comparison circuit. Data stuff information for notifying that data stuff control has been performed, A data stuff information multiplexing circuit that multiplexes the data read by the output circuit, and a basic clock that counts the number of bytes contained in one frame, and the number of clocks per frame is an integral multiple of the input clock. A pulse generation circuit for generating a clock pulse having a fixed number more than the number per frame of the frequency clock, a frequency dividing circuit for dividing the clock output from the clock pulse generating circuit to the integral number, A clock phase comparator for comparing the phase of a clock output from the frequency divider with an input signal clock; and, when a phase difference of one clock or more is detected by the clock phase comparator, notification of the fact. Clock multiplexing the clock stuff information to the data read by the data read circuit. A transmission device comprising a transmission information multiplexing circuit, and reading out, in a data readout circuit of the transmission device, original reception data of the channel data separated from the multiplexed data transmitted from the transmission device via the synchronization network. A data write circuit for writing to the buffer with a write clock having the same frequency as the clock; a data stuff information detection circuit for detecting the data stuff information from the channel data; and a data stuff information detected by the data stuff information detection circuit. A data destuff control circuit for performing data destuff control for shifting a write timing by one clock by the data writing circuit; a clock stuff information detection circuit for detecting the clock stuff information from the channel data; Clock generated by the pulse generator A pulse generating circuit that generates a clock pulse having the same frequency as the clock pulse; a frequency dividing circuit that divides a clock output from the pulse generating circuit to one-half of the integer; and a clock stuff information detecting circuit that generates clock stuff information. A clock destuffing control circuit for performing clock destuffing control for shifting the output clock from the frequency dividing circuit by one clock when detected, following a clock destuffed by the clock destuffing control circuit, An asynchronous data transmission system comprising: a reception device including a phase locked loop circuit that generates a read clock for reading written data.