JPH03244237A - Asynchronous data transmission system - Google Patents

Abstract

PURPOSE:To realize conventionally difficult asynchronous data transmission by a synchronous network with small waiting time jitter by executing clock stuff control separately from data stuff control. CONSTITUTION:The common clock 17 of an entire synchronous network is inputted to pulse generators 27 and 28. The pulse generator 27 is connected through a data stuff control circuit 29 to an elastic store 18. The pulse generator 28 is connected to one input of a second phase comparator 25 and the output side of the phase comparator 25 is connected through a clock stuff information generating circuit 38 to a clock stuff multiplexing circuit 35. Based on the clock of the synchronous network, the clock stuff control is executed while generating clocks so that the number of clocks per frame of a specified period can be mutually prime to the number of clocks per one frame of the input clock synchronized to the input data and that the frequency can be slightly highly deviated rather than the frequency of the input clock. Further, by using stuff-controlled clock, the data stuff control is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an asynchronous data transmission system that transmits asynchronous data using a synchronous network.

[Conventional technology]

In a digital transmission system, a plurality of low-order digital signals are usually time-division multiplexed to create a high-order digital signal, which is then transmitted to a long distance. Then, on the receiving side, by separating this, the original low-order group digital signal can be obtained. For this purpose, the following two conditions are required.

(I) On the transmitting side, the speeds of the multiplexed low-order group signals must completely match each other.

(b) On the receiving side, the exact location of each channel must be known in order to correctly separate each channel from the multiplexed signal.

In current communication networks, each transmitter has a clock source and transmits low-order group signals in synchronization with independent clock frequencies.

Therefore, in order to satisfy condition (i), on the transmitting side, it is necessary to synchronize the bits of each low-order group signal before multiplexing. Furthermore, in order to satisfy the condition (b), on the receiving side, synchronization of frames as a multi-channel code group is performed.

Of these, the stuff synchronization method is generally used to achieve bit synchronization. In this method, all the low-order group signals can be placed on a common frequency by reading out the input signal with a clock that is slightly faster than any of the low-order group signals.

In this case, since the phase difference between the read clock and the low-order group signal clock increases little by little, data to be read may sometimes run out. Therefore, compensation is performed by inserting and adding a so-called stuff pulse at this position.

FIG. 4 shows a data transmission system using such a stuff synchronization method.

In this figure, a transmitting device 101 is connected to a receiving device 103 via a transmission path 102 forming an asynchronous network. This transmitting device 101 is equipped with an elastic store 104 as a buffer memory having a FIF○ (first in, first out) function of about several bytes,
05 and input data 106 synchronized therewith are input. This input clock 105 is also input to the phase comparator 108 via the write counter 107.

Further, this device is equipped with a clock oscillator 109,
Frequency f. The read clock 111 is output. This read clock 111 is input to the elastic store 104 and the stuff information generation circuit 113, and is also input to the phase comparator 108 via the read counter 114. The frequency f of this read clock 111 has a value slightly larger than the frequency f of the input clock 105, and is set so that the average stuff rate is an appropriate value.

Here, the average stuffing rate is a numerical value indicating the average number of times stuffing is performed in one frame.

The output side of the phase comparator 108 is the stuff information generation circuit 11
3 to one of the two inputs of adder 116. The other input of this adder 116 is connected to the elastic store 104, and the output side is connected to the transmission line 104 via a frame synchronization signal multiplexing circuit 117.
connected to 2.

On the other hand, the receiving device 103 includes a frame synchronization signal detection circuit 1.
21 is provided, and data is input from a transmission line 102. This frame synchronization signal detection circuit 12
The output side of 1 is branched into two, and each is connected to an elastic store 122 and a staff information termination circuit 123. The output side of this stuff information termination circuit 123 passes through a destuff control circuit 124 and is branched into two.
One is connected to elastic store 122 and the other is connected via write counter 127 to one of two inputs of phase comparator 128 . Destuff control circuit 12
4 shows the frequency f extracted from the received data. The clock 125 is inputted.

The output side of the phase comparator 128 includes a digital-to-analog converter (D/A) 132 and a low-pass filter (LPF) 13.
3, and a phase locked loop (PLL) circuit 135 consisting of a voltage controlled oscillator (VC○). The output of this phase-locked loop circuit 135 is output as an output clock 137 and is also input to the phase comparator 128 via a read counter 139. This output clock 137 is the elastic store 1
22, and data read out in synchronization with this is output as output data 138.

The operation of the data transmission system using the conventional horizontal aperture stuff synchronization method as described above will be explained.

The input data 106 is an input clock 10 with a frequency ft
It is written to the elastic store 104 in synchronization with 5. The data written to this elastic store 104 is based on the frequency f output from the clock oscillator 109.
It is read out in synchronization with the read clock 111 of 0 and input to the adder 116.

On the other hand, the number of clock pulses of the input clock 105 and the read clock 111 are counted by the write counter 107 and the read counter 114, respectively, and each count value is input to the phase comparator 108.

This phase comparator 108 compares these count values,
When the phase difference exceeds IUI, a stuff request signal 112 is output. The stuff information generating circuit 113 that receives this generates the stuff pulse 115, and adds the stuff pulse 115 to the adder 11.
Enter 6. As a result, the adder 116 inserts a stuff pulse at the corresponding timing position of the data read from the elastic store 104. Then, this stuffed data 118 is multiplexed with a frame synchronization signal by a frame synchronization signal multiplexing circuit 117, and then sent to the transmission path 102.

The frame synchronization signal detection circuit 121 first detects a frame synchronization signal on the data input to the receiving device 103, and achieves frame synchronization.

When the stuffing pulse position is detected by the stuffing information termination circuit 123, the destuffing request signal 131
is output. As a result, the destuffing control circuit 124 performs destuffing to remove the stuffing pulse. As a result, a destuffed write clock 126 is generated, and data 129 is written to the elastic store 122 in synchronization with this.

The write clock 126 is also input to a write counter 127, and the number of clock pulses is counted. This count value is input to the phase comparator 128 together with the count value of the read pulses output from the read counter 137, and the phase difference is extracted. This phase difference information is converted into an analog quantity by the digital-to-analog converter 132 of the PLL circuit 135, and after high frequency components are removed by the low-pass filter 133,
It is input to the voltage controlled oscillator 134. This voltage controlled oscillator 134 outputs a clock having a frequency proportional to the input voltage, and inputs it to the read counter 137.

In this way, the output clock 1 that follows the frequency of the write clock 126 is controlled by the loop of the PLL circuit 135.
39 (frequency fi) is output, and in synchronization with this, reading from the elastic store 122 is performed and is output as output data 138.

In the conventional stuffing synchronous communication system in an asynchronous network as explained above, the frequency of the read clock is selected so that the average stuffing rate is appropriate, and a PLL is installed on the receiving device side.
By providing a circuit to regenerate the read clock, so-called stuff jitter can be reduced. This makes it possible to stabilize the period at which stuff pulses are inserted. For example, if one stuff pulse is inserted every 20 bits of input data, there will be fluctuations of about ±1 bit, but the average If this is done, a stuff pulse will be inserted every 20 bits.

Such conventional stuff synchronous transmission systems were compatible with relatively low clock frequencies. However, in recent years, as society has become more information-oriented, higher-speed data transmission has been required, and as a result, the clock frequencies used have also become higher. For this reason, it is becoming difficult for conventional staff synchronous data transmission systems to cope with this problem.

Therefore, recently, a new synchronous network data transmission system has been proposed and research and development is underway. In this system,
The entire system, within Japan, or even the entire world.
It attempts to perform communication in synchronization with one clock. In this new synchronous network data transmission system, all devices in the system operate in synchronization with a common clock frequency generated by a common clock source (DC3).

[Problem to be solved by the invention]

With the transition to such a new system, it is necessary to temporarily use existing equipment. In this case, since these devices are asynchronous to the common clock, by providing a clock source that generates a clock with the same frequency as the common clock frequency in each device, the input data clock can be matched to the frequency of the common clock. It is necessary to do so. However, in reality, they cannot be made to match completely, so some frequency deviation exists between the read clock and write clock to the elastic store. Since this frequency shift is slight, if the common clock is simply used as a read clock, the period for inserting stuff pulses will be long, and there will be frames in which no stuff pulses are inserted at all. In addition, the phase comparator does not output a stuff request unless the count difference between the write pulse and the read pulse is one clock or more, so if these frequencies are very close, there will be a difference of 7 l clocks. It may become stable at the previous state and the average staffing rate may become 0. Therefore, the so-called latency jitter has the worst value, IUIpp (unit interval peak-to-peak), and data is transmitted with a phase shift of almost 1 bit. You will no longer be able to receive it.

As described above, when a new synchronous network is used to transmit asynchronous data from existing devices, the conventional staff synchronous method has the drawback of not being practical.

SUMMARY OF THE INVENTION An object of the present invention is to provide an asynchronous data transmission system that can transmit asynchronous data from existing devices using a synchronous network.

[Means to solve the problem]

In the invention according to claim 1, (i) the number of clocks per frame of a predetermined period is determined based on the common clock in a synchronous communication network in which communication is performed by synchronizing the entire network to one common clock frequency, a first pulse generating means for generating a clock that is coprime to the number of clocks per frame of the synchronized input clock;
) Clock stuff information multiplexing for multiplexing clock stuff information to output data to notify when the phase difference between the clock output from the first pulse generating means and the input clock exceeds a predetermined threshold. and (
iii) a transmission line for transmitting multiplexed data sent out from the clock stuff information multiplexing means; and (iv) a first
(v) when clock stuff information is detected in the data separated from the multiplexed data received from the transmission line; The asynchronous data transmission system is provided with clock destuffing means for destuffing the clock output from the second pulse generation means.

In the invention according to claim 1, based on the clock of the synchronization network, the number of clocks per frame of the predetermined period is coprime to the number of clocks per frame of the input clock synchronized with the input data, and the input clock A clock with a frequency slightly higher than that of is generated and clock stuff control is performed. Furthermore, data destuffing control is performed by using a stuffed clock.

In the invention as claimed in claim 2, (a) (1) a data read circuit that reads input data written in the buffer in synchronization with an input clock using a read clock synchronized with a network synchronization signal that is a common clock of the entire synchronization network; (ii) a data phase comparison circuit that compares the number of data read by this data reading circuit and the number of data written to the buffer for each frame of a predetermined period; and (iii) this data phase comparison circuit. When a phase difference of one clock or more is detected by the circuit, a data stuff control circuit that performs data stuff control to shift the read timing of the data read circuit by one clock, and (iv) a data phase comparison circuit that shifts the read timing of the data read circuit by one clock or more. a data stuff information multiplexing circuit that multiplexes data stuff information, which is used to notify that data stuff control has been performed by the data stuff control circuit, on the data read by the data read circuit when a phase difference between the two is detected; (v) a phase-locked loop circuit that generates a clock having a frequency that is an integral multiple of the input clock frequency; and (vi) a phase-locked loop circuit that is synchronized with a basic clock that counts the number of bytes accommodated in one frame, and that is synchronized with the number of clocks per frame. (vi
i) a clock phase comparison circuit that compares the phases of the clock output from this pulse generation circuit and the clock output from the phase-locked loop circuit; A transmitting device consisting of a clock stuff information multiplexing circuit that multiplexes clock stuff information for notifying the fact on data read out by a data reading circuit when detected; Data writing in which the original received data of the channel data separated from the multiplexed data sent via the synchronous network is written to the buffer using a write clock with the same frequency as the read clock in the data read circuit of the transmitting device. (11) a data stuff information detection circuit that detects data stuff information from channel data; and (iii) when data stuff information is detected by the data stuff information detection circuit, the timing of writing by the data write circuit is determined. a data destuffing control circuit that performs data destuffing control to shift the data by one clock; (iv) a clock stuffing information detection circuit that detects clock stuffing information from channel data; and (v) a clock pulse generated by the pulse generating circuit of the transmitting device. and (vi) a clock that performs clock destuffing control on the clock output from the pulse generating circuit when the clock stuff information detection circuit detects clock stuff information. a destuffing control circuit;
<vii) A frequency divider circuit that divides the clock output from the clock destuff control circuit into an integer fraction;
ii) Follow the clock output from this frequency dividing circuit,
An asynchronous data transmission system is provided with a receiving device including a phase-locked loop circuit that generates a read clock for reading data written in a buffer.

In the invention as claimed in claim 2, when the phase difference between the clocks output from the phase locked loop and the pulse generating means respectively in the transmitting device exceeds a predetermined threshold, the clock stuff information is multiplexed with data and transmitted. . On the other hand, on the receiving device side, when clock stuff information is detected in the received and separated data, the output clock from the pulse generating means is destuffed, divided, and further smoothed to generate a read clock. I decided to.

In the invention as claimed in claim 3, (a) (1) a data read circuit that reads input data written in the buffer in synchronization with an input clock using a read clock synchronized with a network synchronization signal that is a common clock of the entire synchronization network; (ii) a data phase comparison circuit that compares the number of data read by this data reading circuit and the number of data written to the buffer for each frame of a predetermined period; and (iii) this data phase comparison circuit. When the circuit detects a phase difference of 1 clock or more, the data stuff control circuit performs data stuff control to shift the read timing of the data read circuit by 1 clock, and (iv) the data phase comparison circuit A data stuffer that multiplexes data stuff information, which is used to notify that data stuffing control has been performed by the data stuffing control circuit, on the data read out by the data reading circuit when a phase difference of more than a clock period is detected. It is synchronized with the information multiplexing circuit and (■) a basic clock that counts the number of bytes accommodated in one frame, and the number of clocks per frame is more constant than the number of clocks per frame with a clock whose frequency is an integral multiple of the input clock. (vi) a frequency dividing circuit that divides the clock output from the clock pulse generating circuit into an integer divided by (vj
) A clock phase comparison circuit that compares the phase of the clock output from this frequency dividing circuit and the input signal clock; (i) A transmission device consisting of a clock stuff information multiplexing circuit that multiplexes clock stuff information for notification to that effect with data read out by a data reading circuit; a data write circuit that writes original received data of the channel data separated from the multiplexed data sent to the buffer using a write clock having the same frequency as a read clock in the data read circuit of the transmitting device;
(ii) a data stuff information detection circuit that detects data stuff information from channel data; and (iii) when data stuff information is detected by this data stuff information detection circuit, the writing timing by the data writing circuit is changed by one clock. (iv) a clock stuff information detection circuit that detects clock stuff information from channel data; and (v) a clock pulse having the same frequency as the clock pulse generated by the pulse generation circuit of the transmitting device. A pulse generation circuit that generates a clock pulse of a clock destuffing control circuit that performs clock destuffing control to shift the output clock from the frequency dividing circuit by one clock when detected;
(viii) The asynchronous data transmission system is equipped with a receiving device comprising a phase-locked loop circuit that follows the clock destuffed by the clock destuff control circuit and generates a read clock for reading data written in the buffer. let

In the third aspect of the invention, when the phase difference between the input signal clock and the clock output from the frequency dividing means becomes one clock or more, the transmitting device multiplexes the clock stuff information into the data. Send. On the other hand, on the receiving device side, when clock stuff information is detected in the received and separated data, a read clock is generated by destuffing and smoothing the output clock from the frequency dividing means.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows an asynchronous data transmission system according to a first embodiment of the present invention. In this figure, a transmitting device 11 is connected to a receiving device 13 via a synchronous network I2. Each of these devices has a clock generator 15.16.
is provided with a frequency f supplied from a data clock source (DC3) 14 which is a common clock source for the entire synchronous network.
1 common clock 17 is output.

The transmitting device 11 is equipped with an elastic store 18, and is configured to receive an input clock 19 having a frequency f1 and input data 21 synchronized therewith. This input clock 19 is input to the first clock via a write counter 22.
The second phase comparator 23 is input to one input of the second phase comparator 23 , and the second phase comparator 25 is input to the second phase comparator 25 via a phase locked loop (hereinafter referred to as PLL) circuit 24 .

Frequency f output from clock generator 15.

The common clock 17 of the first and second pulse generators 27
．． 28 is input. Among them, the first pulse generator 27 is connected to the elastic store 18 via the data stuff control circuit 29, and the first pulse generator 27 is connected to the elastic store 18 via the data stuff control circuit 29.
It is connected to the other input of the first phase comparator 23 via.

The output side of the first phase comparator 23 is connected to one of two inputs of an adder 34 via a data stuff information generation circuit 33 and is also connected to a data stap control circuit 29. The other input of this adder 34 is connected to the elastic store 1B, and the output side is connected to the synchronization network 12 via a clock stuff multiplexing circuit 35 and a frame synchronization signal multiplexing circuit 36.

Further, the second pulse generator 28 is connected to the second phase comparator 25.
is connected to the other input of the The output side of this phase comparator 25 is the clock stuff information generation circuit 3.
8 to the clock stuff multiplex circuit 35.

On the other hand, the receiving device 13 includes a frame synchronization signal separation circuit 41.
is provided, and data received from the synchronous network 12 is input thereto. This frame synchronization signal separation circuit 4
The output side of 1 is branched into three parts, each connected to an elastic store 42, a data stuff information termination circuit 43, and a clock stuff information termination circuit 44.

Frequency f output from clock generator 16.

The common clock 17 of the third and fourth pulse generators 46
．． 47 is input. Of these, the third pulse generator 46 is connected to the elastic store 42 via a data destuff control circuit 49. This data destuffing control circuit 49 includes a data stuffing information termination circuit 4.
3 output side is connected.

Further, the fourth pulse generator 47 is connected to a PLL circuit 53 via a clock destuff control circuit 51 and a frequency division interval v&52.
It is connected to the. Of these, the output side of the clock stuff information termination circuit 44 is connected to the clock destuff control circuit 51. An output clock 55 having a frequency f is output from the PLL circuit 53, and output data 56 is read from the elastic store 42 in synchronization with this.

Next, the operation of the asynchronous data transmission system configured as above will be explained.

Input data 21 is written to elastic store 18 in synchronization with input clock 19 of frequency f. The data written in the elastic store 18 is read out in synchronization with the read clock 57 generated by the first pulse generator 27 based on the common clock 17 with a frequency f, and is input to the adder 34. Ru. This read clock 5
The number of bits per frame of input data 21 is the number of bits per frame of input data 21 plus l bits for stuff control.

On the other hand, the number of clock pulses of the input clock 19 and the read clock 57 are counted by the write counter 22 and the read counter 31, respectively, and each count value is sent to the phase comparator 2.
3 is input. The phase comparator 23 compares these counts and outputs a stuff request signal 58 when the phase difference exceeds IUI. Upon receiving this, the data stuff control circuit 29 performs control to shift the reading by one clock, and the data stuff information generation circuit 33 generates data stuff information indicating that data stuffing has been performed, and sends it to the adder 34. input.

Then, the adder 34 adds the data read from the elastic store 18 and the data stuff information. This data stuff information is added to a pre-secured bit position in one frame, and whether this bit is "0" or "1" indicates the presence or absence of data stuff.

The operation up to this point is almost the same as the conventional example, and if the receiving device side were to perform the same control as the conventional example, the average stuffing rate would be almost 0, so the waiting time jitter would be IUIp-p. A problem will arise.

However, in this embodiment, this problem is solved by providing an additional circuit that performs clock stuffing as described below.

FIG. 2 shows in detail an additional circuit for performing clock stuff control of the asynchronous data transmission system of FIG. In this figure, the PLL circuit 24 is shown in particular detail, and the symbols assigned to other parts correspond to those in FIG.

The PLL circuit 24 is equipped with a phase comparator 61, and the input clock 19 is input to one of its inputs. Its output side is connected to a frequency divider circuit 65 via a digital-to-analog converter 62, a low-pass filter 631, and a voltage-controlled oscillator 64, and is also connected to a phase comparator 25. The output side of the frequency dividing circuit 65 is a phase comparator 61.
connected to the other input of the Voltage controlled oscillator 6
4 outputs a clock 66 with a frequency N times the frequency f of the input clock, and by further loop-controlling this clock, a clock with a frequency exactly Nf is output. However, N represents an arbitrary integer. Therefore, the number of clocks per frame is expressed by the following equation (1). However, the frame period is T.

shall be.

NfI Tr ・・・・・・(
1) However, it is assumed that equation (1) satisfies the following equation (2).

Nft Tt <f, Tt...
(2) Also, the pulse generator 28 has a frequency of f, based on the common clock 17, and the number of clocks per frame is PLL times! The number of clocks 67 that is n more than the number of clocks per frame output by 824 is output. The number P of clocks 67 per frame is expressed by the following equation (3).

However, n is a positive integer.

Ps=N ft Tt +n ・”・”
(3) As a result, the output clock 66 of the PLL circuit 24
The phase difference between the clock signal 67 and the clock signal 67 output from the pulse generator 28 gradually increases, and the average stuff rate is no longer zero.

The second phase comparator 25 compares the phases of the clocks 66 and 67, and outputs a clock stuff request signal 68 when the phase difference exceeds a predetermined threshold of M bits. Upon receiving this, the clock stuff information generation circuit 38 generates 1 clock stuff information indicating that clock stuff is to be performed.
This clock stuff information is output from the pit and input to the clock stuff multiplexing circuit 35 (hereinafter shown in FIG. 1).
The data from the adder 34 is multiplexed by the clock stuff multiplexing circuit 35, and the frame synchronization signal is multiplexed by the frame synchronization signal multiplexing circuit 36 before being sent onto the synchronization network 12.

Therefore, the average stuffing rate Sr of clock stuffing is expressed by the following formula <4>.

S, = n/M ・・・・・・〈4〉
On the other hand, data input from the synchronization network 12 to the receiving device 13 is first detected for a frame synchronization signal by the frame synchronization signal separation circuit 41 and separated into target channel data 71.

Data staff information, [times! At 843, when data stuffing information is detected from the channel data 71, a data destuffing request signal 72 is output.

Upon receiving this, the data destuffing control circuit 49 performs destuffing control to shift the write clock 73 output from the pulse generator 46 by one clock. Here, the write clock 73! The number of clocks per frame is the same as that of the read clock 57 output by the first pulse generator 27 of the transmitter 11. In synchronization with the destuff-controlled write clock 73 in this manner, the original received data portion of the channel data 71 is written into the elastic store 42 .

The channel data 71 is also input to the clock stuff information termination circuit 44, and when clock stuff information is detected, a clock destuff request signal 75 is output. In the clock destuff control circuit 51 that receives this,
Destuffing is performed on the clock 76 output from the fourth pulse generator 47. The number of clocks per frame of this clock 76 is the same as that of the second pulse generator 28 of the transmitter 11, and is the number shown in equation (3).

Therefore, by the clock destuffing control, the number of clocks per frame output from the clock destuffing control circuit 51 is as shown in equation (1). This frequency is divided by N by the frequency dividing circuit 52, and the clock whose number of clocks per frame is as follows (5>), that is, the clock whose average frequency is f, is sent to the PLL circuit 52.
3 will be input.

f+Tr ・・・・・・(5
> As shown in FIG. 2, the PLL circuit 53 is connected to the phase comparator 7
8, a digital-to-analog converter 79, a low-pass filter 81, and a voltage-controlled oscillator 82,
Control is performed to follow the input clock 77 and reduce the latency jitter included therein. This results in
An output clock 55 having the same frequency f as that of the input clock 19 and having less latency jitter is output. This output clock 55 is output as is to the outside of the device, and is also input to the elastic store 42 (hereinafter shown in FIG. 1). In synchronization with this, data is read from the elastic store 42 and is output as output data 56.

In the above explanation, when considering the case where asynchronous data of, for example, 2.048 Mbps (1 Gbit/sec) is transmitted over a new synchronous network, various parameters are as shown in the following equations (6> to (9)).

fs = 2.048Mbps (
6) f, = 19.44MHz --------
(7) Tr = 125 μs ・・・・・・
(ill)n-1...(9>) Then, the number of clocks PC per frame of the common clock 17 of frequency f5 becomes a value as shown in the following equation (10>).

PC=f,T.

=2430...(lO) Therefore, the integer N that satisfies formula (2) is 9, so <3>
The expression takes the value of the following expression (11).

P, = 2305 (11)
That is, the number of clocks output by the second pulse generator 28 per frame may be set to 2305.

At this time, if the clock stuff threshold M is set to 13, the average stuffing rate will be the value of the following equation (12) from equation (4).

S, = 1/13 = 0.0769 ・−・−・(12)
Next, a detailed explanation of the present invention will be given regarding a second embodiment.

FIG. 3 shows an asynchronous data transmission system according to a second embodiment of the present invention.

In this figure, the same parts as in the first embodiment (FIG. 1) are given the same reference numerals, and the explanation will be omitted as appropriate. In this system, the input clock (frequency f+) to the transmitter 11 is directly input to one of the inputs of the phase comparator 25. The other input of this phase comparator 25 is connected via a frequency dividing circuit 81 to a second pulse generator 28 to which the common clock 17 of frequency f5 is input. The other configurations are similar to the first embodiment (FIG. 1).

In addition, in the receiving device 13, the common clock 1 with the frequency f
The fourth pulse generator 17 to which 7 is input is connected to the frequency dividing circuit 5
2 and the PL via the clock destuff control circuit 51.
It is connected to the L circuit 53. The other configurations are similar to the first embodiment (FIG. 1).

Next, the operation of the asynchronous data transmission system configured as above will be explained. However, the stuffing control of the input data 21, that is, the part related to the data stuffing control, is the same as in the first embodiment, so the explanation will be omitted here.

The second pulse generator 28 of the transmitter 11 has a frequency f2
Based on the common clock 17 of , a clock 67 is output whose number of clocks per frame is n more than the number of clocks per frame having a frequency N times that of the input clock 19. That is, the number P of clocks 67 per frame is as shown in equation (3), which will be reproduced below. However, n is a positive integer.

P, =N f+ Tr +n --(3)
This clock 67 is frequency-divided by a factor of N by a frequency dividing circuit 81 and input to the phase comparator 25 . The number of clocks per frame of this frequency-divided clock 82 is a value shown in the following equation (13).

Sushi T r + n / N...
・(13) As a result, the input clock 19 and the frequency divider circuit 8
The phase difference between the output clock 82 and the output clock 82 gradually increases by (n/N) every l frames.

In other words, this is the average staffing rate.

The second phase comparator 25 compares the phases of the clocks 19 and 82, and outputs a clock stuff request signal 68 when the phase difference is greater than or equal to IUI. Upon receiving this, the clock stuff information generation circuit 38 outputs 1 bit of clock stuff information indicating that clock stuffing is to be performed, and inputs it to the clock stuff multiplexing circuit 35.

Thereafter, multiplexed data is sent onto the synchronous network 12 by the same operation as in the first embodiment.

In the receiving device 13 as well, channel data 71 separated by the same operation as in the embodiment is input to the data stuff information termination circuit 43, the elastic store 42, and the clock stuff information termination circuit 44. Here, a description of operations related to data stuff control will be omitted.

When the clock stuff information termination circuit 44 detects clock stuff information from the input channel data 71, it outputs a clock destuff request signal 75 and supplies it to the clock destuff control circuit 51.

The fourth pulse generator 47 is configured such that the number of clocks per frame is the second pulse generator of the transmitting device 11, as shown in equation (3).
It outputs a clock 76 which is identical to the pulse generator 28 of. This clock 76 is frequency-divided by N/N by the frequency dividing circuit 52, and is inputted to the clock destuff control circuit 51 as a tally 84 whose number of clocks per frame is shown in equation (13>). , the clock destuff control circuit 51 receives the clock destuff request signal 75.
The clock 84 is destuffed at the received timing. Therefore, the number of clocks per frame of the clock 85 output from the clock destuff control circuit 51 is as shown in equation 5 below.

flTr ・・・・・・(5
) That is, a clock with an average frequency f, is input to the PLL circuit 53.

In the PLL circuit 53, the first embodiment (FIGS. 1 and 2)
The same control as in the case of 1 is performed, and an output clock 55 having the same frequency f1 as the input clock 19 and with less latency jitter is output.

This output clock 55 is output as is to the outside of the device and is also input to the elastic store 42 . Then, data is read from the elastic store 42 in synchronization with this output clock 55 and is output as output data 56.

In this way, asynchronous network transmission of asynchronous data with less stuff jitter is achieved.

〔Effect of the invention〕

As explained above, according to the invention as claimed in claim 1, since clock stuffing control is performed separately from data stuffing control, asynchronous data transmission using a synchronous network, which has been difficult in the past, can be performed with less waiting time jitter. The effect is that it can be realized.

Further, according to the inventions recited in claims 2 and 3, since the average stuffing rate in clock stuffing of asynchronous data can be selected to a certain extent, the effect is that the design of a circuit for reducing latency jitter is facilitated. There is.

[Brief explanation of drawings]

1 to 3 are for explaining the present invention in detail, of which FIG. 1 is a block diagram showing the asynchronous data transmission system in the first embodiment, and FIG. 2 is the main part of FIG. 1. FIG. 3 is a block diagram showing an asynchronous data transmission system in the second embodiment, and FIG. 4 is a block diagram showing a conventional staff synchronous data transmission system. 11... Transmission device, 12... Synchronization network,
13... Receiving device, 14... Data clock source, 15.16.
... Clock generator, 17 ... Common clock, 19 ... ° ... Input clock, 21 ... Input data, 24 ... PLL circuit,・25...
... Phase comparator, 28.47 ... Pulse generator, 38 ... Clock stuff information generation circuit,
51... Clock destuff control circuit, 52.
81... Frequency divider circuit, 53... PLL circuit, 55... Output clock, 56... Output data.

Claims (1)

[Claims] 1. Based on a common clock in a synchronous communication network in which communication is performed by synchronizing the entire network to one common clock frequency,
a first pulse generating means for generating a clock such that the number of clocks per frame of a predetermined period is coprime to the number of clocks per frame of an input clock synchronized with input data; When the phase difference between the clock output from the input clock and the input clock exceeds a predetermined threshold,
Clock stuff information multiplexing means for multiplexing clock stuff information to output data to notify that effect; a transmission path for transmitting multiplexed data sent from the clock stuff information multiplexing means; and the first pulse. a second pulse generating means for generating a clock having the same frequency as the clock outputted by the generating means; and when the clock stuff information is detected in data separated from multiplexed data received from the transmission line, An asynchronous data transmission system comprising clock destuffing means for destuffing a clock output from the pulse generation means. 2. A data read circuit that reads input data written in a buffer in synchronization with an input clock using a read clock synchronized with a network synchronization signal that is a common clock for the entire synchronization network, and data read out by this data read circuit. and a data phase comparison circuit that compares the number of data written in the buffer with the number of data written in the buffer for each frame of a predetermined cycle; and when the data phase comparison circuit detects a phase difference of one clock or more, the data a data stuff control circuit that performs data stuff control to shift the read timing of the read circuit by one clock; and when a phase difference of one clock or more is detected by the data phase comparator circuit, the data stuff control circuit performs data stuff control. a data stuff information multiplexing circuit that multiplexes data stuff information for notifying that the input clock has been performed on the data read out by the data reading circuit; and a data stuff information multiplexing circuit that generates a clock having a frequency that is an integral multiple of the input clock frequency. Synchronized with a phase-locked loop circuit and a basic clock that counts the number of bytes accommodated in one frame, the number of clocks per frame is a constant number than the number per frame at a clock frequency that is an integral multiple of the input clock frequency. A pulse generation circuit that generates as many clock pulses as a transmitting device comprising a clock stuff information multiplexing circuit that multiplexes clock stuff information for notifying the fact on the data read out by the data reading circuit when a phase difference equal to or greater than a predetermined threshold is detected; The original received data of the channel data separated from the multiplexed data sent from this transmitter via the synchronous network is buffered using a write clock having the same frequency as the read clock in the data read circuit of the transmitter. a data write circuit for writing; a data stuff information detection circuit for detecting the data stuff information from the channel data;
a data destuffing control circuit that performs data destuffing control to shift the timing of writing by the data writing circuit by one clock when data stuffing information is detected by the data stuffing information detection circuit; a clock stuff information detection circuit that detects information; a pulse generation circuit that generates a clock pulse having the same frequency as the clock pulse generated by the pulse generation circuit of the transmitter; and a clock destuff for the clock output from the pulse generation circuit. a clock destuffing control circuit that performs control when the clock stuffing information detection circuit detects clock stuffing information; and a frequency dividing circuit that divides the clock output from the clock destuffing control circuit into the integer fraction. and a receiving device comprising a phase-locked loop circuit that follows the clock output from the frequency dividing circuit and generates a read clock for reading data written in the buffer. data transmission system. 3. A data read circuit that reads input data written in a buffer in synchronization with an input clock using a read clock synchronized with a network synchronization signal that is a common clock for the entire synchronization network, and data read out by this data read circuit. and a data phase comparison circuit that compares the number of data written in the buffer with the number of data written in the buffer for each frame of a predetermined cycle; and when the data phase comparison circuit detects a phase difference of one clock or more, the data a data stuff control circuit that performs data stuff control to shift the read timing of the read circuit by one clock; and when a phase difference of one clock or more is detected by the data phase comparator circuit, the data stuff control circuit performs data stuff control. a data stuff information multiplexing circuit that multiplexes data stuff information to notify that the data has been read out with the data read out by the data reading circuit; and a data stuff information multiplexing circuit that is synchronized with a basic clock that counts the number of bytes accommodated in one frame. a pulse generation circuit that generates clock pulses whose number of clock pulses per frame is a certain number more than the number of clock pulses per frame of a clock having a frequency that is an integral multiple of the input clock; and a frequency dividing circuit that divides the frequency of the clock to be divided by the integer; a clock phase comparison circuit that compares the phase of the clock output from the frequency division circuit with the input signal clock; a transmitting device comprising a clock stuff information multiplexing circuit that multiplexes clock stuff information for notifying the data read out by the data reading circuit when a phase difference of more than minutes is detected; Data for writing the original received data of the channel data separated from the multiplexed data sent from the device via the synchronous network into the buffer using a write clock having the same frequency as the read clock in the data read circuit of the transmitting device. a write circuit; a data stuff information detection circuit that detects the data stuff information from the channel data; and when data stuff information is detected by the data stuff information detection circuit, the write timing by the data write circuit is set to 1. a data destuffing control circuit that performs data destuffing control to shift the clock by a clock; a clock stuffing information detection circuit that detects the clock stuffing information from the channel data; a pulse generation circuit that generates a clock pulse; a frequency division circuit that divides the clock output from the pulse generation circuit into a fraction of the integer; and when clock stuff information is detected by the clock stuff information detection circuit, a clock destuffing control circuit that performs clock destuffing control to shift the output clock from the frequency dividing circuit by one clock; and a clock destuffing control circuit that follows the destuffed clock by the clock destuffing control circuit and reads the data written in the buffer. 1. An asynchronous data transmission system comprising: a receiving device comprising a phase-locked loop circuit that generates a read clock for reading.