JPS5811781B2 - Digital Kaisenmouno Ketsugoubunkisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved apparatus for coupling or dropping low speed digital signals to high speed digital lines in a multiplex digital line network.

Multiple digital lines require that low speed digital signals be coupled to and dropped from high speed digital lines.

In this case, if the low-speed and high-speed digital signals are completely synchronized, they can be combined or branched smoothly, but constructing such a completely synchronous system is expensive due to the stability and reliability of the oscillator. Become something.

For this reason, a so-called stuff synchronization method has been developed and is widely known, in which a high-speed signal is controlled by a clock that is relatively faster than a low-speed signal, and waste information pulses are inserted in the remaining positions.

However, when this staff synchronization is performed, jitter occurs due to the waiting time.

The temporary storage circuit of the multiplexer is configured to absorb various types of jitter, but since the jitter due to the waiting time extends to zero frequency, it cannot be completely eliminated.

Therefore, when stuff synchronization is performed, low frequency jitter is essentially added to the digital signal.

Conventionally, this low-frequency jitter has been suppressed to a negligible level by taking into account the design of the synchronization system, but it tends to accumulate when a line is configured in a chain through a large number of multiplexers.

Since this low frequency jitter is not removed by another stuffing operation, a phase lock loop, a digital repeater, etc., it affects the decoded baseband analog signal, especially the image signal and color signal.

The present invention provides a high-speed digital line network that has clock stability and reliability comparable to that of the normal stuff synchronization method, and is configured so that the cumulative phase jitter caused by branching or coupling as described above is not generated. The purpose of the present invention is to provide a coupling/branching device.

The present invention uses the clock signal induced by the clock signal of the branched low-speed digital signal as the clock signal of the signal to be combined, and uses the same stuff synchronization control signal as the branched signal as the stuff synchronization control signal of the signal to be combined. In order to maintain the phase of the signal to be combined and the high-speed clock required for multiplexing, the present invention is characterized by comprising a transmission storage circuit for temporarily storing the signal to be combined.

The principle of the present invention is to achieve synchronization between low-speed signals and high-speed signals by using a stuff synchronization method for low-speed signals at the beginning of the first stage in each high-order group coupling/branching device, and to use a dependent synchronization method between high-order groups. This method achieves synchronization of the high-speed digital line network, and then for the low-speed signals that are branched and combined by the combining and branching equipment at intermediate stations, the signals are stuffed by the previous combining and branching equipment. If the signal is synchronized to a high-speed signal by operation, as long as there is no speed change between the signal to be branched and the signal to be combined, the information will be synchronized without re-synchronizing the stuff during the combination. This means replacing the .

Therefore, by configuring a digital backbone line using such equipment, re-stuffing can be omitted when combining and branching low-speed signals at intermediate stations, and the stuffing jitter that occurs when connecting multiple links can be avoided. This can be expected to have the effect of making it possible to replace low-speed signals while preventing the accumulation of signals.

In addition, when using this method, the low-speed signal can be independent from the high-speed signal, so compared to the fully synchronous method, the precision of the clock used is relatively inexpensive for both high-order and low-order groups. (about 10-5) can be used.

This will be explained in detail below using the drawings.

FIG. 1 is a side view of the configuration of a high-speed digital line in which the present invention is implemented.

In the figure, 1 is a low-speed signal coupling circuit, 2 is a high-speed transmitting device, 3 is a transmission line, 4 is a regenerative repeater, 5 is a high-speed receiving device, 6 is a voltage-controlled oscillator, and 7 is a low-speed branching and coupling circuit.

The low-speed signal combining circuit 1 has a low-speed signal input, and its output is combined with the high-speed signal by a high-speed transmitter 2 using a stuff synchronization method.

The output of the transmitting device 2 is sent to a transmission line 3 and input to a high-speed receiving device 5 via an intermediate regenerative repeater 4.

Here, a part of the low-speed signal is branched, a new low-speed signal is combined into that time slot, and the new low-speed signal is provided to the high-speed transmitter 2.

Here, the voltage controlled oscillator e is for bit synchronizing the high speed transmitting device 2 with the preceding device.

When bit synchronization is thereby achieved between the received and transmitted signals, the frame structure of the high-speed signal can be made the same before and after this, so the low-speed signal that does not need to be branched can be passed through as is.

The high-speed signal is sent from the high-speed transmitter 2 to the transmission line 3 at the next stage.

This operation is repeated every time branching and coupling is necessary, and a chain line is constructed.

FIG. 2 is a configuration diagram of the low-speed signal branching and coupling circuit 7.

8 represents an output circuit, 9 represents a clock circuit, and 10 represents an input circuit.

A clock signal is regenerated from the branched signal output circuit 8 by a clock circuit 9 and used as a clock signal for the combined signal.

FIGS. 3 and 4 are signal frame configuration diagrams of the above-described embodiment.

FIG. 3 shows a frame configuration in which four series of low-speed signals shown in sets ① to ① are multiplexed into one series of high-speed signals (848 bits).

FIG. 4 shows the configuration of each set I to (2) in more detail.

In the figure, F is a frame alignment signal, A is an alarm transmission bit, N is a surplus bit, C1, C2 and C3 are stuff command bits, V is a variable bit during stuffing, and #1 to #105 are information transmission bits.

The stuffing command bits C1, C2, and C3 and the stuffing variable bit V are stuffing synchronization control signals.

It is now assumed that the information of the first tributary low-speed signal, shown by the shaded bit in FIG. 4, is branched and a new signal is coupled to the same position.

If bit synchronization is established between the slow signal being branched and the slow signal being combined, then upon branching, stuff command bits C11 and C2 are included in the pulse stream of the high speed signal.
1, C31 and the wasteful information in the variable bit V are left together with the passing signal, and only the low speed signal information part is extracted.

Furthermore, when combining, the low-speed signal to be combined can be written into the empty time slot by omitting the stuff operation.

In this way, even if branching and combining are performed, the stuffing command bits and stuffing variable bits on the input side of the high-speed receiving device 5 remain unchanged as the stuffing command bits and the stuffing variable bits on the output side of the high-speed transmitting device 2. Since the clock of the newly combined low-speed digital signal is synchronized with the branched low-speed digital signal, no new jitter is added by this combination/drop device.

That is, no accumulation of jitter occurs even if the signal passes through such a coupling/branching device repeatedly.

The operation and configuration of the device will be explained in more detail.

FIG. 5 is a block diagram of the high-speed receiving device 5 and the high-speed transmitting device 2 of the embodiment of the present invention.

The received signal from the transmission line 3 is level-adjusted via an amplifier 21 and is provided to a clock counter 22 and a synchronization circuit 23.

Bit synchronization and frame synchronization are established here.

Furthermore, the high speed signal is supplied to a separation circuit 24.

Here, the signals are branched into low-speed signal units and sent to the respective assigned reception storage circuits 25.

At the same time, the stuff command bit for each low-speed signal is extracted and sent to the distuff control circuit 26.

Here, the branched signal in each reception storage circuit 25 is controlled by the distuff control signal sent from the distuff control circuit 26, so that only the information part of the low-speed signal is stored in the storage circuit 25.
will be written to.

The distuffed signal is regenerated into the original low-speed signal and sent to the low-speed coupling branch circuit 7.

Here, the necessary signals are branched, new signals are combined, and the signals are sent to the high-speed transmitter again.

On the other hand, the output of the clock counter 22 is branched and sent to the voltage controlled oscillator 6, and the voltage controlled oscillator 6 and the clock generation circuit 27 cause the clock frequency of the high speed transmitter to follow the receiving side frequency, that is, the frequency of the previous stage.

Next, the frame configuration of the transmitter 2 is synchronized using a frame alignment control signal (FA-8IG) which is also branched from the output of the clock counter 22.

Next, among the high-speed signals sent from the receiving side through the passing signal, the passing signal is passed through the gate 28 and written into the coupling circuit 29 .

In this device, the determination as to whether the signal is a pass signal or a branch signal is made depending on whether or not the transmission storage circuit 30 is loaded with content.

Since the new low-speed signal is combined in synchronization with the signal branched by the branch/combine circuit 7, no stuffing operation is performed, and the stuffing command bit and waste pulse are simply left in the passing signal and combined into the time slot. The combined signal may be written in the circuit 29.

If the combined signals cannot be synchronized, as with the conventional method, all signals related to the low-speed signal among the high-speed signals sent through the passing signal path are prohibited from passing, and a new staff operation is performed. Then, the combined signal will be written.

The low-speed signals to be combined are once written into the transmission storage circuit 30 in order to match their phases, and after a short period of time, are read out by the read clock sent from the clock generation circuit 27, sent to the combination circuit, and sequentially written. It will be done.

The read clock sent from the clock generation circuit 27 is controlled by the stuffing control signal (STF-C) coming from the distuffing control circuit 26 if the combined signal is synchronous, but if the combined signal is asynchronous, the readout clock is not transmitted. The stuff control signal (STF) from the stuff control circuit 31 of
- controlled by C).

In this embodiment, this determination of synchronization or non-synchronization is performed by the low-speed coupling and branching circuit 7 for convenience, but there is no problem with the side stages even if the determination is performed by the high-speed device.

Furthermore, unnecessary signals of the high-speed signals sent from the receiving side are inhibited by the gate 28, and only necessary signals are sent to the coupling circuit 29.

As mentioned above, bit synchronization of the high-speed signals is achieved before and after branching and combining, and when the synchronized low-speed signals are combined, the frame structure completely matches the previous frame.
A device is obtained in which jitter from the previous stage is simply carried over as is, and no new jitter is accumulated.

Note that the input and output synchronization means described in the above embodiments do not limit the scope of the present invention, and the present invention can be implemented with other configurations.

Furthermore, the present invention can be implemented using other methods than those described in the above example regarding means for deriving a clock signal from a branched low-speed signal.

The means for determining the passing signal described in the above example may also be performed using other methods.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of multiple lines according to an embodiment of the present invention. FIG. 2 is a configuration diagram of a low-speed branching and coupling circuit. FIG. 3 is a signal frame configuration diagram of the above embodiment. FIG. 4 is a signal bit configuration diagram of the above embodiment. FIG. 5 is a block diagram of a high-speed reception and transmission device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Low-speed signal coupling circuit, 2...High-speed transmitter, 3...Transmission line, 4...Regenerative repeater, 5...・High-speed receiving device, 6...
Voltage controlled oscillator, 7...Low speed branch coupling circuit, 8
...Output circuit, 9...Clock circuit,
10...Input circuit, 21...Amplifier,
22...Clock counter, 23...
Synchronous circuit, 24... Separation circuit, 25...
- Reception storage circuit, 26...Distuff control circuit, 27...Clock generation circuit, 28...
...gate, 29...coupling circuit, 30...
...Transmission storage circuit, 31...Stuff control circuit, 32...Frame pulse generation circuit, 33...
····amplifier.

Claims (1)

[Claims] 1. Branching means for branching a part of the low-speed digital signal from a high-speed digital signal obtained by time-division multiplexing of a large number of low-speed digital signals together with a stuffing synchronous control signal, and controlling the inputted low-speed digital signal under stuffing synchronous control. a multiplexer, comprising coupling means for coupling the high-speed digital signal with the signal by a stuffing synchronization method, and configured such that the high-speed digital signal on the output side of the coupling means is slave-synchronized with the high-speed digital signal on the input side of the branching means. A coupling/branching device for a digital line network, comprising means for separating a clock signal from a low-speed digital signal branched by the branch output, the coupling means comprising a transmission storage circuit for temporarily storing the input low-speed digital signal, The combining means reads a low-speed digital signal to be combined in synchronization with the clock signal induced by the clock signal from the transmission storage circuit, and combines the stuff synchronous control signal included in the low-speed digital signal branched by the branching means. A coupling/branching device for a multiplex digital line network, characterized in that the coupling/branching device is configured to use a low-speed digital signal as a stuffing synchronization control signal.