JPH07202868A - Data rate converter - Google Patents

Abstract

PURPOSE:To solve a problem that jitter of a recovered low order group clock is increased when low order group data excluding an overhead from a high order group data including the overhead in plural consecutive bytes are recovered. CONSTITUTION:An intermittent clock generating circuit 105 generates an intermittent clock by using a distributed pulse equivalent to consecutive overhead bytes and adjusts the presence of stuff bytes by increasing/decreasing number of distributes pulses by each byte per frame. A phase locked loop is controlled by using a reference signal for phase locked loop obtained by applying 1/N frequency division to the intermittent clock at a 1/N frequency divider circuit 106 and a signal obtained by applying 1/N frequency division to a signal from a voltage controlled oscillator 110 at a 1/N frequency divider circuit 107. The data in FIFO 101 are read by using a clock signal generated from the phase locked loop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data rate conversion device.

[0002]

2. Description of the Related Art In implementing data transmission by SDH (Synchronous Digital Hierarchy), which is a new synchronous network standardized in CCITT, there are a plurality of rates in an overhead multiplexing process and a demultiplexing process. Basic multiplexing units include containers (hereinafter C), virtual containers (VC), and STM (see CCITT Recommendations G.707 to 709).

FIG. 4 shows the STM-1 frame structure. In FIG. 4, 401 is a C-4 frame and 402 is a POH.
(Path overhead), 403 is a VC-4 frame,
404 is SOH (section overhead), 405
Is an AU pointer, and 406 is an STM-1 frame.

As shown in FIG. 4, P is added to the C-4 frame 401.
The VC-4 frame 403 is a multiplex of OH402.
Then, the SOH 404 and AU are added to the VC-4 frame 403.
Multiplexed pointer 405 is STM-1 frame 4
It is 06. The VC-4 frame 403 is STM-
Since it is asynchronous with respect to one frame 406, the VC-4 frame 403 is changed to STM-1 by the AU pointer 405.
VC-4 frame 40 when multiplexed into frame 406
3 shows the top phase.

Here, the signal rates are different,
In the 8-bit parallel state, the C-4 frame is 18.7.
2 Mbps, VC-4 frame is 18.792 Mbps
Since the s and STM-1 frames have 19.44 Mbps, a method of performing data rate conversion using a buffer memory is usually used at the time of multiplexing and demultiplexing.

[0006] Usually, when performing rate conversion of STM-1 data, the overhead of the STM-1 data (SOH + P
The portion excluding the (OH + AU pointer) is written in the FIFO, and the data is read by the continuous clock of C-4 rate. If there is positive / negative stuffing, destuffing processing is performed to control the write clock of the FIFO. A phase locked loop is used to recover the C-4 rate continuous clock.

FIG. 3 shows an example of a conventional data rate converter, and FIG. 6 shows an output timing chart of the reference signal generating clock in FIG.

In FIG. 3, reference numeral 301 denotes a FIFO and 302
Is a timing generation circuit, 303 is an AND gate, 304
Is a staff decision circuit, 305 is an AND gate, 306,
307 is a 1 / N frequency dividing circuit, 308 is a phase comparator, 309
Is a low pass filter, 310 is a voltage controlled oscillator, 311
Is a pointer processing circuit, 312 is an STM-1 data input terminal, 313 is an STM-1 clock input terminal, 314 is C
-4 data output terminal, 315 is C-4 clock input terminal, 316 is STM-1 frame pulse input terminal, 31
7 is a data rate conversion device.

As shown in FIG. 3, this device has an STM-
The STM-1 data input from the 1-data input terminal 312 is written in the FIFO 301, and the voltage controlled oscillator 310
In this configuration, C-4 data is read from the FIFO 301 and data rate conversion is performed by the C-4 clock generated by.

The phase locked loop will be described below.
In the timing generating circuit 302, based on the STM-1 frame pulse input from the STM-1 frame pulse input terminal 316, the SO of the received STM-1 data is SO.
The timings of the H and AU pointers are detected, the POH timing included in the STM-1 data is detected based on the VC-4 frame pulse indicating the head position of the VC-4 frame generated by the pointer processing circuit 311, and C is detected. A pulse corresponding to -4 data is generated (see FIG. 6 (k)). When the stuffing process is performed, the stuffing determination circuit 304 detects the presence or absence of the stuffing from the reception pointer value and generates a pulse corresponding to the C-4 data after destuffing (FIG. 6 (m)). (o)).

Then, with this pulse and the STM-1 clock input from the STM-1 clock input terminal 313, the AND gate 305 generates a clock corresponding to the C-4 data portion in the received STM-1 data ( Figure 6
(see (l) (n) (p)), this is used as the write clock (WCK) of the FIFO 301, and the C-
Write only the data that corresponds to the data.

Further, a pulse (C enable, see FIG. 6 (k) (m) (o)) corresponding to the C-4 data generated by the timing generation circuit 302 and the STM-1 clock input terminal 313 are input to the STM. AND with -1 clock
A clock corresponding to C-4 data is generated by the gate 305, and 1 / N frequency dividing circuit 306 outputs 1 by the clock.
/ N frequency division is performed, and the output is input to the reference input (R) of the phase comparator 308.

The C-4 clock generated by the voltage controlled oscillator 310 is 1 / N by the 1 / N frequency dividing circuit 307.
The frequency-divided output is input to the variable input (V) of the phase comparator 308. The phase comparison result of the output from the 1 / N frequency dividing circuit 306 and the output from the 1 / N frequency dividing circuit 307 is input as a control voltage of the voltage controlled oscillator 310 through the low pass filter 309 to form a phase locked loop.

[0014]

However, in the above conventional configuration, when positive / negative stuffing occurs, the reference signal (R) of the phase comparator corresponds to the width of SOH (AU pointer) + stuff byte. Up to 600 ns
Since it has a jitter of about ec, it causes an increase in the jitter of the reproduction C clock, and causes a deterioration in image quality and sound quality when transmitting an image or voice.

In view of the above point, the present invention provides a data rate conversion apparatus for reducing the jitter of a reproduced low-order group clock when reproducing low-order group data in which overhead is removed from high-order group data including continuous multiple bytes of overhead. The purpose is to provide.

[0016]

In order to achieve the above object, the data rate conversion apparatus of the present invention disperses clocks corresponding to continuous 9 bytes × 9 rows (81 bytes in total) of the SOH portion, and further divides the clock into 4 frames. In this configuration, a PLL reference signal is generated from a clock obtained by dispersing a clock corresponding to 3 bytes of stuffing that occurs in a plurality of frames and thinning it out.

[0017]

According to the present invention, since the PLL reference signal having a small amount of jitter can be generated by the above configuration, the jitter of the C clock reproduced by the phase locked loop or the like can be greatly improved.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a data rate conversion apparatus showing an embodiment of the present invention, FIG. 2 shows an example of the intermittent clock generation circuit in FIG. 1, and FIG. 5 is an output timing chart of the intermittent clock in FIG. It is a thing.

In FIG. 1, 101 is a FIFO and 102
Is a timing generation circuit, 103 is an AND gate, 104
Is a stuff determination circuit, 105 is an intermittent clock generation circuit,
106 and 107 are 1 / N frequency dividing circuits, 108 is a phase comparator, 109 is a low pass filter, 110 is a voltage controlled oscillator, 111 is a pointer processing circuit, 112 is an STM-1 data input terminal, and 113 is an STM-1 clock. Input terminal,
114 is a C-4 data output terminal, 115 is a C-4 clock output terminal, 116 is an STM-1 frame pulse input terminal, and 117 is a data rate converter.

In FIG. 2, 201 is a 1/30 frequency divider, 202 is an AND gate, 203 is a D flip-flop, 204 is an OR gate, 205 is a 1/261 frequency divider, 206 is an OR gate, and 208 to 210 are. D flip-flop with enable, 211 is an OR gate, 212
Is a NAND gate, 213 is a JK flip-flop, 2
14 is an AND gate, 215 is an inverter, 216-2
18 is a D flip-flop with enable, 219 is O
R gate, 220 AND gate, 221 AND gate, 222 D flip-flop, 223 AND gate, 224 JK flip-flop, 225 STM-
1 clock input terminal, 226 positive stuff signal input terminal, 227 negative stuff signal input terminal, 228 STM
-1 frame pulse input terminal, 229 is an intermittent clock output terminal, and 230 is an intermittent clock generation circuit.

The operation of the data rate conversion apparatus configured as described above will be described below with reference to FIGS. 1, 2 and 5.

As shown in FIG. 1, this device has an STM-
Only the portion corresponding to the C-4 data of the STM-1 data input from the 1-data input terminal 112 is stored in the FIFO 101.
C-generated by the voltage-controlled oscillator 110.
The configuration is such that C-4 data is read from the FIFO 101 by four clocks and data rate conversion is performed.

In the timing generation circuit 102, ST
S input from the M-1 frame pulse input terminal 116
Received STM-1 based on TM-1 frame pulse
Detect the timing of data SOH and AU pointers,
S based on the VC-4 frame pulse indicating the head position of the VC-4 data generated in the pointer processing circuit 111.
The POH timing included in TM-1 data is detected,
Further, the stuff determination circuit 104 detects the presence or absence of stuff from the reception pointer value, and the reception S
A clock corresponding to the C-4 data portion in the TM-1 data is generated, and this is used as a write clock (WCK) of the FIFO 101, and only the data corresponding to the C-4 data is written in the FIFO 101.

Further, the clock (GCKC) generated in the intermittent clock generating circuit 105 is divided into 1 / N frequency dividing circuit 10
The frequency is divided by 1 / N at 6, and this signal is divided by the phase comparator 108.
Input to the reference input (R). Then, an output obtained by dividing the C-4 clock generated by the voltage controlled oscillator 110 by 1 / N in the 1 / N frequency divider 107 is input to the variable input (V) of the phase comparator 108. The phase comparison result of the output from the 1 / N frequency dividing circuit 106 and the output from the 1 / N frequency dividing circuit 107 is input as a control voltage of the voltage controlled oscillator 110 through the low pass filter 109 to form a phase locked loop.

Here, the intermittent clock generation circuit of FIG. 2 will be described in detail with reference to FIG. First, the operation in the non-stuff state will be described.

Since one byte (270 bytes) of STM-1 frame has 9 bytes of SOH, the 1/30 frequency dividing circuit 201 generates a pulse (first pulse) in which 9 bytes of SOH are evenly distributed. (See FIG. 5 (c)). This pulse is latched by the D flip-flop 203 via the AND gate 202. A in non-stuff state
The other end of the ND gate 202 is HIGH.

In the non-stuff state, AND gate 2
Since 20 is LOW, the outputs of the AND gate 221 and the D flip-flop 222 are LOW, and the OR gate 2
04, STM-1 clock (CKSTM) and the above 1
OR of 30 pulses. This becomes the VC clock (see FIG. 5 (d)).

Further, since 1 line of POH exists for each line (261 bytes) of the VC frame, 1/261
By generating a pulse once every 261 clocks by the frequency dividing circuit 205 and ORing it with the VC clock by the OR gate 206, it is possible to generate an intermittent clock (GCKC) in which overhead bytes are dispersed and decimated.

Next, the operation in the stuff state will be described.
When the negative stuffing occurs, the data amount of the VC frame in the STM-1 frame increases by 3 bytes (only the frame in which the stuffing is detected).
It is necessary to kill the first pulse generated by 1 for 3 bytes. Also, since the stuffing occurs only once in four frames in the STM-1 frame, the above three bytes are killed one byte at a time over three frames.

First, the negative stuff signal input from the negative stuff input terminal 227 is latched by the enable D flip-flops 208 to 210 with the frame pulse FP, and extended by the OR gate 211 to the width of 3 frames. S
When a frame pulse (FP) is input from the TM-1 frame pulse input terminal 228, the JK flip-flop 2
13 outputs HIGH, and NAND gate 212 is LO
W is output (see FIG. 5 (e)) and the 1/30 frequency divider circuit 20 is output.
Even if the first pulse of 1 is output, it will not pass (see FIG. 5 (f)).

At the same time, the AND gate 214 is set to H level.
It becomes IGH and the K terminal of the JK flip-flop 213 becomes H.
The IGH and J terminals become LOW, the output of the JK flip-flop 213 becomes LOW, the output of the NAND gate 212 becomes HIGH, and the operation returns to the non-stuffing state.
The same operation is performed in the next frame and the next frame, but after that, the OR gate 211 returns to LOW and returns to the operation in the non-stuff state. Thus, one in one frame
The number of VC clocks at the time of negative stuffing is adjusted three times in succession to generate an intermittent clock as described above.

When the normal stuffing occurs, the data amount of the VC frame in the STM-1 frame decreases by 3 bytes (only the frame in which the stuffing is detected).
It is necessary to add a pulse for 3 bytes in addition to the first pulse generated by the frequency dividing circuit 201. In addition, since the stuffing occurs only once in four frames in the STM-1 frame, the above-mentioned three bytes are dispersed and added one byte at a time over three frames.

First, the positive stuff signal input from the positive stuff signal input terminal 226 is supplied to the frame pulse FP input from the STM-1 frame pulse input terminal 228 by the enable D flip-flops 216 to 218.
Latched by, and extended by OR gate 219 to 3 frame width. When the frame pulse FP is input, the JK flip-flop 224 outputs HIGH, and the AND gate 22
0 outputs HIGH (see FIG. 5 (g)), so that the second pulse (≠ 1st pulse, see FIG. 5 (h)) by the 1/30 frequency divider circuit 201 passes through the AND gate 221. (See FIG. 5 (i)).

At the same time, the AND gate 223 becomes H level.
The output of the JK flip-flop 224 becomes LOW, the output of the AND gate 220 becomes LOW, and the operation returns to the non-stuffing state. The same operation is performed in the next frame and the next frame, but after that, the OR gate 219 returns to LOW and returns to the operation in the non-stuffing state. In this way, once per frame,
The intermittent clock is generated as described above by adjusting the number of VC clocks in the positive stuffing for three consecutive frames.

In this embodiment, the STM-1 clock obtained by dividing the transmission clock by ⅛ is used as the basis of the 8-bit parallel processing. However, in the same processing, a clock obtained by thinning the transmission clock itself is used. It is also possible to generate and thereby generate a reference signal.

The present invention is not limited to the above-mentioned embodiments, but various modifications can be made based on the gist of the present invention, and these modifications are not excluded from the scope of the present invention.

[0037]

As described above, according to the present invention, 9 bytes of the SOH (including the AU pointer) portion and 3 bytes by the stuff are dispersed and thinned to generate the phase locked loop reference signal, thereby reducing the jitter. The C clock can be regenerated.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a data rate conversion device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an intermittent clock generation circuit in FIG.

FIG. 3 is a schematic configuration diagram of a conventional data rate conversion device.

FIG. 4 is a block diagram of an STM-1 frame.

5 is a timing chart showing a reference clock generation process in FIG.

FIG. 6 is a timing chart showing a reference clock generation process in FIG.

[Explanation of symbols]

 101 FIFO 102 Timing Generation Circuit 103 AND Gate 104 Stuff Judgment Circuit 105 Intermittent Clock Generation Circuit 106 1 / N Frequency Division Circuit 107 1 / N Frequency Division Circuit 108 Phase Comparator 109 Low Pass Filter 110 Voltage Control Oscillator 111 Pointer Processing Circuit 112 STM -1 Data Input Terminal 113 STM-1 Clock Input Terminal 114 C-4 Data Output Terminal 115 C-4 Clock Output Terminal 116 STM-1 Frame Pulse Input Terminal 117 Data Rate Converter 201 1/30 Frequency Divider 202 AND Gate 203 D flip-flop 204 OR gate 205 1/261 divider circuit 206 OR gate 208 to 210 D flip-flop with enable 211 OR gate 212 NAND gate 213 JK flip-flop 214 AND gate 215 Inverters 216 to 218 D flip-flop with enable 219 OR gate 220,221 AND gate 222 D flip-flop 223 AND gate 224 JK flip-flop 225 STM-1 clock 226 Positive stuff signal input terminal 227 Negative stuff signal input terminal 228 STM-1 frame pulse input terminal 229 intermittent clock output terminal 230 intermittent clock generation circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Ryozo Kishimoto 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. A buffer memory is used to reproduce low order group data multiplexed with consecutive N bytes (M and N are integers, M> N) of overhead and consecutive L bytes of stuff bytes in M bytes. A data rate conversion device, comprising: a phase locked loop control means for controlling a read clock of the buffer memory by a phase locked loop; and an intermittent clock generation means for generating an intermittent clock of a high order group clock corresponding to the number of low order group clocks. And a reference signal generating means for generating a reference signal of the phase locked loop from the intermittent clock. 2. The data rate converter according to claim 1, wherein the intermittent clock generating circuit comprises a first distributed pulse generating means for generating a distributed pulse corresponding to an overhead of N consecutive bytes. 3. The data rate conversion apparatus according to claim 2, wherein the first dispersed pulse generation circuit comprises N / M frequency dividing means for performing N / M frequency division. 4. An intermittent clock generating circuit is provided with a second dispersed pulse generating means for receiving the N / M frequency division output as an input and generating a dispersed pulse corresponding to a stuff byte of continuous L bytes. The data rate conversion device according to claim 3. 5. A stuff control signal input terminal and a frame pulse input terminal for high-order group data are provided, and the stuff control signal input from the stuff control signal input terminal is held for K frames (K is an integer, K> 1). The data rate conversion apparatus according to claim 4, further comprising a stuff control signal holding unit.