JP3140285B2 - Data rate converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data rate converter for reproducing a low-order group signal multiplexed with a high-order group signal using a buffer memory.

[0002]

2. Description of the Related Art When realizing data transmission by SDH (Synchronous Digital Hierarchy), which is a new synchronous network standardized in CCITT, there are a plurality of rates in the overhead multiplexing process and the demultiplexing process.
Basic multiplexing units include containers (hereinafter C), virtual containers (hereinafter VC), and STM (CCIT
T Recommendation G. 707-709).

FIG. 8 shows an STM-1 frame configuration. 8, 701 is a C-4 frame, 702 is a POH
(Path overhead), 703 is a VC-4 frame,
704 is an SOH (section overhead), 705
Is an AU pointer, and 706 is an STM-1 frame.

[0004] As shown in FIG.
A multiplexed version of H702 is a VC-4 frame 703,
The STM-1 frame 706 is obtained by multiplexing the SOH 704 and the AU pointer 705 on the VC-4 frame 703.
It is. Since the VC-4 frame 703 is asynchronous with respect to the STM-1 frame 706, the AU pointer 7
05 indicates the leading phase of the VC-4 frame 703 when multiplexing the VC-4 frame 703 into the STM-1 frame 706.

Here, the signal rates are different from each other,
In an 8-bit parallel state, the C-4 frame is 18.7.
2 Mbps, VC-frame is 18.792 Mbps
Since the s, STM-1 frame is at 19.44 Mbps, a method of performing data rate conversion using a buffer memory is usually used during multiplexing and demultiplexing.

Normally, when performing the rate conversion of the STM-1 data, the overhead of the STM-1 data (SOH + P
OH + AU pointer) is written into the FIFO, and data is read out at a C-4 rate continuous clock. If there is positive / negative stuff, destuff processing is performed to control the FIFO write clock. This C-
A phase-locked loop is used to reproduce a 4-rate continuous clock.

Hereinafter, a conventional example will be described in detail with reference to the drawings. FIG. 5 shows a conventional data rate converter, and FIG.
5 shows an example of the intermittent clock generation circuit in FIG. 5, and FIG. 7 shows an output timing chart of the intermittent clock in FIG.

In FIG. 5, reference numeral 401 denotes a FIFO;
Is a timing generation circuit, 403 is a NOR gate, 404
Is an AND gate, 405 is a stuff determination circuit, 406 is an intermittent clock generation circuit, 407 to 408 are 1 / N frequency divider circuits, 409 is a phase comparator, 410 is a low-pass filter,
411 is a voltage controlled oscillator, 412 is a pointer processing circuit,
413 is an STM-1 data input terminal, 414 is an STM- data input terminal.
1 clock input terminal, 415 is a C-4 data output terminal,
416 is a C-4 clock output terminal, 417 is STM-1
Frame pulse input terminals 418 are data rate converters.

In FIG. 6, 501 is a 1/30 frequency divider, 502 is an AND gate, 503 is a D flip-flop, 504 is an OR gate, 505 is a 1/261 frequency divider, 506 is an OR gate, and 508 to 510 are D flip-flop with enable, 511 is an OR gate, 512
Is a NAND gate, 513 is a JK flip-flop,
14 is an AND gate, 515 is an inverter, and 516-5
18 is a D flip-flop with enable, 519 is O
R gate, 520: AND gate, 521: AND gate, 522: D flip-flop, 523: AND gate, 524: JK flip-flop, 525: STM-
1 clock input terminal, 526 is a positive stuff signal input terminal, 527 is a negative stuff signal input terminal, 528 is an STM
-1 frame pulse input terminal, 529 is an intermittent clock output terminal, and 530 is an intermittent clock generation circuit.

The operation of the data rate conversion device configured as described above will be described below with reference to FIGS. 5, 6 and 7.

[0011] As shown in FIG.
Only the portion corresponding to the C-4 data of the STM-1 data input from one data input terminal 413 is
, And C− generated by the voltage controlled oscillator 411.
In this configuration, C-4 data is read from the FIFO 401 by four clocks and data rate conversion is performed.

In timing generation circuit 402, ST
S input from the M-1 frame pulse input terminal 417
Based on the TM-1 frame pulse, the received STM-1
Detects the SOH of the data and the timing of the AU pointer,
S based on a VC-4 frame pulse indicating the head position of the VC-4 data generated by the pointer processing circuit 412
The POH timing included in the TM-1 data is detected. Further, in the stuff determination circuit 405, the presence or absence of stuff is detected from the received pointer value, and a clock corresponding to the C-4 data portion in the received STM-1 data is generated based on the detected stuff, and this is written into the FIFO 401 write clock (WCK). And writes only data corresponding to the C-4 data into the FIFO 401.

The clock (GCKC) generated by the intermittent clock generation circuit 406 is divided by a 1 / N frequency dividing circuit 40.
7, the signal is divided by 1 / N, and this signal is
To the reference input (R). Then, an output obtained by dividing the C-4 clock generated by the voltage controlled oscillator 411 by 1 / N in the 1 / N dividing circuit 408 is input to the variable input (V) of the phase comparator 409. A phase comparison result of the output of the 1 / N frequency dividing circuit 407 and the output of the 1 / N frequency dividing circuit 408 is input as a control voltage of the voltage controlled oscillator 411 through the low pass filter 410 to form a phase locked loop.

Here, the intermittent clock generation circuit in FIG. 6 will be described in detail with reference to FIG. First, the operation in the non-stuff state will be described.

Since there are 9 bytes of SOH per row (270 bytes) of the STM-1 frame, the 1/30 frequency dividing circuit 501 generates a pulse (first pulse) in which 9 bytes of SOH are evenly dispersed. (See FIG. 7C). This pulse is latched by the D flip-flop 503 via the AND gate 502. A in non-staff state
The other end of the ND gate 502 is HIGH. In the non-stuffing state, the output of the AND gate 521 and the output of the D flip-flop 522 become LOW because the AND gate 520 is LOW, and the OR gate 504 takes OR of the STM-1 clock (CKSTM) and the 1/30 pulse. This becomes the VC clock (see FIG. 7D).

Further, since there is one byte of POH per row (261 bytes) of the VC frame,
By generating a pulse once every 261 clocks by the frequency dividing circuit 505 and ORing with the VC clock by the OR gate 506, it is possible to generate an intermittent clock (GCKC) in which overhead bytes are dispersed and thinned out.

Next, the operation in the stuff state will be described.
When a negative stuff occurs, the data amount of the VC frame in the STM-1 frame increases by 3 bytes (only the frame in which the stuff is detected).
The first pulse generated by 1 needs to be killed by 3 bytes. Further, since the stuff occurs only once in four frames in the STM-1 frame, the above-mentioned three bytes are killed one by one over three frames. First, the negative stuff signal input from the negative stuff input terminal 527 is latched with the frame pulse FP by the D flip-flops 508 to 510 with enable, and is extended to three frame width by the OR gate 511.

STM-1 frame pulse input terminal 528
When the frame pulse (FP) is input, the JK flip-flop 513 outputs HIGH and the NAND gate 512 outputs LOW (see FIG. 7E), and
Even if the first pulse is output by the 0 frequency dividing circuit 501, the first pulse is not passed (see FIG. 7 (f)). At the same time,
The AND gate 514 becomes HIGH, the K terminal of the JK flip-flop 513 becomes HIGH, the J terminal becomes LOW, and the output of the JK flip-flop 513 becomes LOW.
The output of NAND gate 512 goes high and returns to non-stuffed operation. The same operation is performed in the next frame and the next frame.
1 returns to LOW and returns to the operation in the non-stuff state. In this way, the number of VC clocks at the time of negative stuff is adjusted once per frame and for three consecutive frames to generate an intermittent clock as described above.

When the correct stuff occurs, the data amount of the VC frame in the STM-1 frame is reduced by 3 bytes (only the frame in which the stuff is detected), so that it is 1/30.
It is necessary to add a 3-byte pulse in addition to the first pulse generated by the frequency dividing circuit 501. Further, since the stuff occurs only once in four frames in the STM-1 frame, the above-mentioned three bytes are dispersedly added one by one over three frames. First, the positive stuff signal input from the positive stuff signal input terminal 526 is input to the S flip-flops 516 to 518 to enable the positive stuff signal.
The signal is latched by the frame pulse FP input from the TM-1 frame pulse input terminal 528, and is extended to three frame widths by the OR gate 519.

When the frame pulse FP is input, the JK flip-flop 524 outputs HIGH and the AND gate 520 outputs HIGH (see FIG. 7 (g)).
The second pulse (≠ first pulse, see FIG. 7 (h)) from the 30-divider circuit 501 passes through the AND gate 521 (see FIG. 7 (i)). At the same time, the AND gate 523 becomes HIGH, and the JK flip-flop 5
24 K terminal is HIGH, J terminal is LOW and JK
The output of the flip-flop 524 becomes LOW, and AND
The output of gate 520 goes LOW and returns to non-stuff operation. The same operation is performed in the next frame and the next frame, but after that, the OR gate 519 becomes LOW.
Return to the operation in the non-stuff state. As described above, once in one frame, for three consecutive frames, VC at the time of normal stuff
The number of clocks is adjusted to generate an intermittent clock as described above.

[0021]

However, the NDF
Or, when the same pointer is received for three consecutive frames, the rule that the POH byte exists once every 261 bytes is broken. In such a case, in the above configuration, the operating point of the FIFO is shifted, and if the above operation occurs plural times, FIF
O is underflowed and data is lost.
Alternatively, there has been a problem in that when the main stuff occurs during the operation just before the underflow, the FIFO underflows and the data is lost.

The present invention has been made in view of the above problems, and in the above-mentioned state, the operating point of the FIFO is fixed substantially at the center.
An object of the present invention is to provide a data rate conversion device that generates a PLL phase comparator reference signal with little jitter and generates a highly accurate C clock.

[0023]

In order to achieve the above object,
The data rate conversion device of the present invention comprises a phase locked loop control means for controlling a read clock of a buffer memory by a phase locked loop, and a first distributed pulse generation for generating a dispersed pulse corresponding to the number of continuous J bytes of overhead clocks. Means, second dispersed pulse generating means for generating a dispersed pulse corresponding to the number of stuff clocks of continuous K bytes, and a POH pulse corresponding to the number of M-th group overhead clocks as input with the M-th group overhead pulse as an input. A pulse generating means, a third dispersed pulse for generating a pulse to be inserted when the position of the Mth-order group overhead pulse and the dispersed pulse position generated by the first or second dispersed pulse generating means overlap each other. Generating means, the M-th group overhead pulse position, and the third dispersed pulse generating means. A fourth dispersed pulse generating means for generating a pulse to be inserted when the generated dispersed pulse positions overlap each other; and a distributed pulse generated by the first, second, third and fourth dispersed pulse generating means and a POH. Intermittent clock generating means for synthesizing pulses to generate an intermittent clock of an L-order group clock corresponding to the number of N-order group clocks;
A reference signal generating unit configured to generate a reference signal of the phase locked loop from the intermittent clock generated by the intermittent clock generating unit.

[0024]

According to the present invention, by inserting the POH pulse at a position different from the SOH dispersion pulse according to the above configuration, the L-order group intermittent clock corresponding to the N-order group clock number can be generated. Even if the same pointer is received a plurality of times consecutively, the operating point of the FIFO can always be fixed at almost the center.
Data loss due to underflow can be prevented, and a phase-locked loop reference signal with less jitter and a highly accurate C clock can be generated.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a data rate converter according to an embodiment of the present invention, FIG. 2 shows an example of an intermittent clock generation circuit in FIG. 1, and FIGS. 3 and 4 show output timings of the intermittent clock in FIG. It shows a chart.

In FIG. 1, reference numeral 101 denotes a FIFO;
Is a timing generation circuit, 103 is a NOR gate, 104
Is an AND gate, 105 is a stuff determination circuit, 106 is an intermittent clock generation circuit, 107 and 108 are 1 / N frequency divider circuits, 109 is a phase comparator, 110 is a low-pass filter,
111 is a voltage controlled oscillator, 112 is a pointer processing circuit,
113 is an STM-1 data input terminal, 114 is an STM-
1 clock input terminal, 115 is a C-4 data output terminal,
116 is a C-4 clock output terminal, 117 is STM-1
A frame pulse input terminal 118 is a data rate converter.

In FIG. 2, 201 is a 1/30 frequency dividing circuit, 202 is an AND gate, 203 and 204 are OR gates, 205 is a D flip-flop, 206 is an OR gate, 208 to 210 are D flip-flops with enable, 211 Is an OR gate, 212 is a NAND gate, 2
13 is a JK flip-flop, 214 is an AND gate,
215 is an inverter, 216 to 218 are D flip-flops with enable, 219 is an OR gate, 220 is A
ND gate, 221 AND gate, 222 AND gate, 223 JK flip-flop, 224 AND gate
Gates, 225 are JK flip-flops, 226-22
8 is an AND gate, 229 is a JK flip-flop, 2
30, 231 are AND gates; 232, an STM-1 clock input terminal; 233, an intermittent clock output terminal;
Is a POH pulse input terminal, 235 is a positive stuff signal input terminal, 236 is a negative stuff signal input terminal, and 237 is ST
An M-1 frame pulse input terminal 238 is an intermittent clock generation circuit.

The operation of the data rate converter configured as described above will be described below with reference to FIGS. 1, 2, 3 and 4.

As shown in FIG. 1, this apparatus uses an STM-
Only the portion corresponding to the C-4 data of the STM-1 data input from one data input terminal 113 is
And C− generated by the voltage controlled oscillator 111.
In this configuration, C-4 data is read from the FIFO 101 by four clocks and data rate conversion is performed.

In the timing generation circuit 102, ST
S input from the M-1 frame pulse input terminal 117
Based on the TM-1 frame pulse, the received STM-1
The SOH timing of the data is detected, and the stuff determination circuit 105 detects the timing of the AU pointer based on the presence or absence of the stuff from the received pointer value, and
Generate P. Further, based on a VC-4 frame pulse (FPVC) indicating the head position of the VC-4 data generated by the pointer processing circuit 112, a POH timing included in the STM-1 data is detected to generate a POHP.
Using these SOHP and POHP, a NOR gate 10 is used.
3. A clock corresponding to the C-4 data portion in the received STM-1 data is generated by the AND gate 104 and is used as a write clock (WCK) for the FIFO 101, and only the data corresponding to the C-4 data is stored in the FIFO 101. Write.

The clock (GCKC) generated in the intermittent clock generating circuit 106 is divided by a 1 / N frequency dividing circuit 10.
7, the signal is divided by 1 / N.
To the reference input (R). Then, an output obtained by dividing the C-4 clock generated from the voltage controlled oscillator 111 by 1 / N in the 1 / N dividing circuit 108 is input to the variable input (V) of the phase comparator 109. The result of the phase comparison between the output of the 1 / N frequency dividing circuit 107 and the output of the 1 / N frequency dividing circuit 108 is input as the control voltage of the voltage controlled oscillator 111 through the low-pass filter 110 to form a phase locked loop.

Here, the intermittent clock generation circuit of FIG. 2 will be described in detail with reference to FIGS. First, the operation in the non-stuff state will be described. Basically, an STM-1 clock (CKSTM) is gated by an OR gate 206 to generate an intermittent clock (GCKC).

Since there are 9 bytes of SOH per row (270 bytes) of the STM-1 frame, the 1/30 frequency dividing circuit 201 generates a pulse (first pulse) in which 9 bytes of SOH are evenly dispersed. (See FIG. 3 (c)). This pulse is supplied to the AND gate 202 and the OR gate 2
POH pulse input from the POH pulse input terminal 234 as an input to the OR 204 via the input terminal 03 (see FIG. 3D)
Is input to the OR 204, a gate pulse for (SOH + POH) clocks can be generated at the output of the OR 204, and this is latched in the D flip-flop 205, and then ORed with the STM-1 clock (CKSTM) by the OR gate 206. Thus, the intermittent clock (GCK) in which overhead bytes are dispersed and thinned out
C) is generated (see FIG. 3E).

Next, the operation in the stuff state will be described.
When the negative stuff occurs, the data amount of the VC frame in the STM-1 frame increases by 3 bytes (only the frame in which the stuff is detected).
The first pulse generated by 1 needs to be killed by 3 bytes. Further, since the stuff occurs only once in four frames in the STM-1 frame, the above-mentioned three bytes are killed one by one over three frames.

First, the negative stuff signal input from the negative stuff input terminal 236 is latched by the STM-1 frame pulse FPSTM input from the STM-1 frame pulse input terminal 237 by the D flip-flops 208 to 210 with enable, and ORed. The width is extended to three frames by the gate 211. STM-1 frame pulse (FPST
M), the JK flip-flop 213 goes high.
IGH is output, the NAND gate 212 outputs LOW (see FIG. 3 (f)), and the 1/30 frequency dividing circuit 201 does not pass even if the first pulse is output (FIG. 3).
(g)).

At the same time, the AND gate 214 goes high.
It becomes IGH and the K terminal of the JK flip-flop 213 becomes H
The IGH and J terminals become LOW, the output of the JK flip-flop 213 becomes LOW, the output of the NAND gate 212 becomes HIGH, and the operation returns to the non-stuff state.
The same operation is performed in the next frame and the next frame, and thereafter, the OR gate 211 returns to LOW and returns to the operation in the non-stuff state. Thus, once per frame,
The number of VC clocks at the time of negative stuff is adjusted for three consecutive frames to generate the intermittent clock (GCKC) as described above (see FIG. 3 (h)).

When the correct stuff occurs, the data amount of the VC frame in the STM-1 frame is reduced by 3 bytes (only the frame in which the stuff is detected), so that it is 1/30.
It is necessary to add a 3-byte pulse in addition to the first pulse generated by the frequency dividing circuit 201. Further, since the stuff occurs only once in four frames in the STM-1 frame, the above-mentioned three bytes are dispersedly added one by one over three frames.

First, the positive stuff signal inputted from the positive stuff signal input terminal 235 is latched by the D flip-flops 216 to 218 with enable with the STM-1 frame pulse FPSTM inputted from the STM-1 frame pulse input terminal 237. , OR gate 219 to extend the width to three frames. STM-1 frame pulse FP
When the STM is input, the JK flip-flop 223 goes high.
The output of IGH, the AND gate 220 outputs HIGH (see FIG. 3 (i)), and the second pulse (≠ first pulse, see FIG. 3 (j)) by the 1/30 frequency dividing circuit 201 is output. AN
It passes through the D gate 221.

At the same time, the AND gate 222 goes high.
It becomes IGH, the K terminal of the JK flip-flop 223 becomes HIGH, the J terminal becomes LOW, the output of the JK flip-flop 223 becomes LOW, the output of the AND gate 220 becomes LOW, and the operation returns to the non-stuff state. The same operation is performed in the next frame and the next frame, but after that, the OR gate 219 returns to LOW and returns to the operation in the non-stuff state. As described above, one frame
The intermittent clock (GCKC) is generated as described above by adjusting the number of VC clocks at the time of normal stuff for three consecutive frames (see FIG. 3 (k)).

Next, the operation under special conditions will be described. 1 /
The first pulse generated by the divide-by-30 circuit 201 and P
The POH pulse input from the OH pulse input terminal 234 is asynchronous, and both pulse positions may overlap (see FIG. 4 (l, m)). At this time, both inputs of the AND gate 227 become HIGH, and the JK flip-flop 225
Becomes HIGH (see FIG. 4 (n)), and becomes 1/30
A third pulse (≠ first and second pulses, see FIG. 4 (o)) generated by the frequency dividing circuit 201 is an AND gate 226.
, And input to the OR gate 204 to generate the intermittent clock (GCKC) as described above (see FIG. 4 (p)). After the third pulse is generated, the output of the AND gate 224 becomes HIGH, and the output of the JK flip-flop 225 returns to LOW.

The above state (1/30 frequency dividing circuit 20)
1 and the POH pulse position overlaps), and when receiving the NDF or receiving the same pointer value for three consecutive frames (see FIG. 4 (q)), the POH pulse position is changed to the third pulse. It may overlap with the position (see FIG. 4 (q, r, s)). At this time, the AND gate 230
Becomes HIGH at both ends of the JK flip-flop 229.
Becomes HIGH (see FIG. 4 (t)),
The fourth pulse (≠ first, second, third pulse, see FIG. 4 (u)) generated by the frequency dividing circuit 201 is the AND gate 2
31 and is input to the OR gate 204 to generate an intermittent clock (GCKC) as described above (FIG. 4 (v)).
reference). After the fourth pulse is generated, the output of the AND gate 228 becomes HIGH, and the output of the JK flip-flop 229 returns to LOW.

In this embodiment, the STM-1 clock obtained by dividing the transmission clock by ８ has been described on the basis of the 8-bit parallel processing, but a clock obtained by thinning the transmission clock itself by the same processing. It can also generate and thereby generate a reference signal. Further, the present invention is not limited to the above embodiments, and various modifications are possible based on the gist of the present invention, and these are not excluded from the scope of the present invention.

[0043]

As described above, according to the present invention, a pulse corresponding to the number of POH pulses is inserted at a position always different from the SOH byte dispersion pulse position, and an intermittent clock (GCKC) equal to the actual number of C data is generated. Since it can be generated, the operating point of the buffer memory can be fixed substantially at the center, and a phase-locked loop reference signal with less jitter can be generated by the clock, so that a highly accurate C clock can be reproduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a data rate conversion device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an intermittent clock generation circuit in FIG. 1;

FIG. 3 is a timing chart showing a reference clock generation process in FIG. 2;

FIG. 4 is a timing chart showing a reference clock generation process in FIG. 2;

FIG. 5 is a schematic configuration diagram of a conventional data rate conversion device.

FIG. 6 is a configuration diagram of an intermittent clock generation circuit in FIG. 5;

FIG. 7 is a timing chart showing a reference clock generation process in FIG. 6;

FIG. 8 is a configuration diagram of an STM-1 frame.

[Explanation of symbols]

 101 FIFO 102 Timing Generator 103 NOR Gate 104 AND Gate 105 Stuff Judgment Circuit 106 Intermittent Clock Generator 107 1 / N Divider 108/1 / N Divider 109 Phase Comparator 110 Low Pass Filter 111 Voltage Controlled Oscillator 112 Pointer Processing Circuit 113 STM-1 data input terminal 114 STM-1 clock input terminal 115 C-4 data output terminal 116 C-4 clock output terminal 117 STM-1 frame pulse input terminal 118 Data rate converter 201 1/30 frequency dividing circuit 202 AND gate 203, 204 OR gate 205 D flip-flop 206 OR gate 208-210 D flip-flop with enable 211 OR gate 212 NAND gate 213 JK flip-flop 214 AND gate 215 Inverter 216-218 D flip-flop with enable 219 OR gate 220-222 AND gate 223 JK flip-flop 224 AND gate 225 JK flip-flop 226-228 AND gate 229 JK flip-flop 230,231 AND gate 232 STM-1 Clock input terminal 233 Intermittent clock output terminal 234 POH pulse input terminal 235 Positive stuff signal input terminal 236 Negative stuff signal input terminal 237 STM-1 frame pulse input terminal 238 Intermittent clock generation circuit

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Ryozo Kishimoto 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-6-326694 (JP, A) JP-A-7-202868 (JP, A) JP-A-4-196937 (JP, A) JP-A-5-48561 (JP, A) JP-A-3-173233 (JP, A) JP-A-4-132345 (JP) , A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00-3/26 H04L ^7/ 00-7/10

Claims (3)

(57) [Claims] An N frame is composed of Nh × Nv bytes.
M-th group data in which one frame composed of multiplexed next-group data and 1-byte overhead inserted every Nh-byte data of the N-th group data is (Nh + 1) × Nv bytes; One frame is Lh ×
An L-th order multiplexed by multiplexing a continuous K-byte stuff byte for absorbing a frequency difference generated when multiplexing into an L-th order frame composed of Nv bytes and a continuous J-byte overhead inserted for each Lh byte From the group data, the N-th group data (Nh, Nv, Lh, N, M, and L) is obtained using one buffer memory for performing data rate conversion.
Is a data rate conversion device for reproducing an integer, N <M <L), a phase locked loop control means for controlling a read clock of the buffer memory by a phase locked loop, and a number corresponding to the number of overhead clocks of continuous J bytes. A first dispersed pulse generating means for generating a dispersed pulse to be generated, a second dispersed pulse generating means for generating a dispersed pulse corresponding to the number of stuff clocks of continuous K bytes, Pulse generating means for generating a POH pulse corresponding to the number of group overhead clocks; and when the M-th group overhead pulse position and the dispersed pulse position generated by the first or second dispersed pulse generating means overlap each other. Third dispersed pulse generating means for generating a pulse to be inserted into the M-th group overhead pulse Fourth pulse generating means for generating a pulse to be inserted when the position and the dispersed pulse position generated by the third distributed pulse generating means overlap each other; and the first, second, third and fourth dispersed pulses An intermittent clock generating means for generating an intermittent clock of the Lth order clock corresponding to the number of Nth order clocks by combining the dispersed pulse and the POH pulse generated by the generating means, and an intermittent clock generated by the intermittent clock generating means And a reference signal generating means for generating a reference signal of the phase locked loop from the reference signal. 2. The data rate conversion device according to claim 1, wherein the first dispersion pulse generating means includes a J / Lh frequency dividing means for dividing the frequency by J / Lh. 3. The stuff control signal input terminal and a frame pulse input terminal of L-order group data, the second distributed pulse generating means comprising: a stuff control signal input from the stuff control signal input terminal; H is an integer, H>
2. The data rate conversion device according to claim 1, further comprising a stuff control signal holding means for holding the data during 0).