JP3380907B2 - Speed conversion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed conversion circuit, and more particularly to a speed conversion circuit used in an SDH digital signal transmission device.

[0002]

2. Description of the Related Art As is well known, an SDH digital signal transmission device is a synchronous digital multiplexing structure (SDH: Synchronous Digital Hierarchy) recommended by the international standard ITU-T.
STM-1 (Synchronous Transport Module) is a device used in the wireless transmission system of
dule-1) signal transmission, overhead (OH: Overhe
ad) Bit insertion / termination, signal switching, auxiliary signal transmission, modulation / demodulation, etc.

The STM-1 signal overhead (O
In the H) processing, a speed conversion circuit for parallel-converting the OH signal received as serial data into data of each byte is required.

FIG. 10 shows a conventional speed conversion circuit. The illustrated speed conversion circuit has a high-speed bit width TH and a frame period T.
High-speed data DH of F, high-speed clock CH, and frame pulse PF are input, and low-speed bit width TL1 = TH × M
(M is an integer of 2 or more) is a circuit that outputs low-speed data DL and low-speed clock CL, and is a data extraction circuit 10 '.
And a M dividing circuit 20 'for dividing the high speed clock CH having the bit width Ts by M to make a low speed clock after speed conversion.
It consists of and.

FIG. 11 shows a circuit example when M = 3.
The data extraction circuit 10 'includes a timing circuit 11' and two-stage flip-flop circuits (F / F) 12 'and 13'.
It consists of and. The timing circuit 11 'generates the timing signal ST from the high speed clock CH and the frame pulse PF. The first stage flip-flop circuit 12 'holds the high speed data DH' in synchronization with the timing signal ST. The next-stage flip-flop circuit 13 'holds the output of the first-stage flip-flop circuit 12' in synchronization with the low-speed clock CL 'supplied from the divide-by-3 circuit 20'.

FIG. 12 shows a time chart for explaining the operation of the speed conversion circuit shown in FIG. As the high-speed data DH, as shown in the third line of FIG. 12, 9-bit data A1, B1, C during one serial frame period TF.
It is assumed that 1, A2, B2, C2, A3, B3 and C3 are supplied. The speed conversion circuit uses one serial frame TF
Is a circuit for extracting 3 bits A1, A2, A3 from the data of and converting it into a signal of low speed bit width TL1 = TH × 3.

The high-speed data DH having the high-speed bit width Ts and the frame period TF is input to the data extraction circuit 10 'and written in the first stage flip-flop circuit 12' by the timing signal ST generated by the timing circuit circuit 11 '. The contents of the first-stage flip-flop circuit 12 'are read out to the next-stage flop-flop circuit 13' with a low-speed clock CL 'having a low-speed bit width TL1 = TH × 3 obtained by dividing the high-speed clock CH having the high-speed bit width TH by three. Then, the low speed data DL 'is output.

Various prior arts related to the present invention are known. For example, Japanese Unexamined Patent Publication No. 5-336170 discloses a "parallel speed conversion circuit" in which N series data is speed-converted by N speed conversion circuits and the delay amount of each data is constant. There is. Further, Japanese Patent Laid-Open No. 5-336088 discloses a "speed conversion bit separation device" in which the circuit configuration for reproducing a secondary clock signal is simplified, the device scale is reduced, and the cost is reduced. There is. Further, Japanese Patent Laid-Open No. 5-327782 discloses a "speed conversion circuit" in which a phase margin is increased with respect to jitter generated in a clock of a PLL circuit.

In each of these prior arts, the low speed clock (output clock) is obtained by dividing the high speed clock (input clock) as in the prior art described above.

[0010]

In the conventional speed conversion circuit described above, the output is always TL1 = TH × M (M is an integer of 2 or more) between the high speed bit width TH and the low speed bit width TL1. If the condition is not satisfied, the low speed clock CL 'cannot be obtained.

For example, the low speed bit width T of the low speed data DL '
If you want to convert L1 to low-speed data that is not an integer multiple of the high-speed bit width TH of high-speed data DH, such as TL1 = TH × 4.5, simply dividing the high-speed clock CH will produce a low-speed clock for low-speed data. Can't get

An object of the present invention is to provide a speed conversion circuit capable of obtaining a low speed clock of low speed data even when the low speed bit width of low speed data is not an integral multiple of the high speed bit width of high speed data.

[0013]

A speed conversion circuit according to the present invention inputs a high-speed clock defining a high-speed bit width, a frame pulse defining a frame cycle, and high-speed data having a frame cycle TF with a high-speed bit width, and outputs a high-speed data. A speed conversion circuit for outputting a low-speed clock defining a low-speed bit width wider than the bit width and low-speed data of the low-speed bit width, wherein the low-speed bit width TL2 is T based on the frame pulse.
Based on the low speed clock generating means for generating a low speed clock represented by L2 = TF / N (N is an integer of 2 or more), the high speed clock, the frame pulse, and the low speed clock,
A data extraction circuit for extracting predetermined data from high speed data and outputting the extracted data as low speed data together with a low speed clock.

[0014]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a speed conversion circuit according to an embodiment of the present invention. The speed conversion circuit shown is
A frame pulse PF that defines the frame period TF, a high-speed clock CH that defines the high-speed bit width TH, and high-speed data DH of the frame period TF with the high-speed bit width TH are input, and a low-speed bit width TL2 = TF / N (N is 2 Is a circuit for outputting a low-speed clock CL that defines the above integer) and low-speed data DL having a low-speed bit width TL2, and is composed of a data extraction circuit 10 and a PLL circuit 20 for creating a low-speed clock CL after speed conversion. Has been done. The PLL circuit 20 generates a low speed clock CL by multiplying the frame pulse PF by N.

With such a structure, if the low-speed bit width TL2 of the low-speed data DL satisfies the condition of TL2 = TF / N (N is an integer of 2 or more), that is, the frame pulse period TF of the low-speed data DL. A PLL provided with a voltage controlled oscillator (VCO) (described later) that outputs a clock with a clock cycle of TL2 if it is an integer multiple of the low-speed bit width TL2.
A low-speed clock C with a low-speed bit width TL2 can be easily created using a circuit.
Can produce L.

FIG. 2 shows the PLL circuit 20. The PLL circuit 20 includes a phase comparison circuit 21 and a low-pass filter (LP
F) 22, a voltage controlled oscillator (VCO) 23, and an N divider circuit 24. The PLL circuit 20 includes a frame pulse PF having a frame period TF and a clock period T.
The low-speed clock CL of L2 is divided by N by the N divider 24 to obtain N.
The phase comparison circuit 20 compares the phases of the divided clock CL / N with each other, and the phase comparison result is passed through the LPF 22 to the VCO 23.
By controlling the low speed clock CL with a low speed bit width TL2.

[0018]

FIG. 3 shows a speed conversion circuit according to a first embodiment of the present invention. In the illustrated speed conversion circuit, the data extraction circuit 10 includes a timing circuit 11 and a pair of first-stage flip-flop circuits (F / F) 12-1 and 12-2.
, A pair of next-stage flip-flop circuits 13-1 and 13-2, a selector circuit 14, and a final-stage flip-flop circuit 15, and the PLL circuit 20.
A is a phase comparison circuit 21, an LPF 22, and a VCO 23.
It is composed of a frequency dividing circuit 24A and a phase adjusting circuit 25.

The timing circuit 11 generates the first and second timing signals ST1 and ST2 based on the high speed clock CH and the frame pulse PF. The pair of first-stage flip-flop circuits 12-1 and 12-2 hold the high speed data DH in response to the first and second timing signals ST1 and ST2, respectively, and hold the high speed data DH. It outputs parallel data DP1 and DP2. The pair of next-stage flip-flop circuits 13-1 and 13-2 have P
Clock divided by two CL / 2 supplied from the LL circuit 20
The first and second parallel data DP1 and DP2 are held in synchronization with (a clock obtained by dividing the low-speed clock CL by two), and the first and second retimed data are output. The selector circuit 14 selects one of the first and second retimed data in response to the divided clock CL / 2 and selects the selected data D.
Output S. The final stage flip-flop circuit 15 is
The selected data DS is held in response to the low speed clock CL and the low speed data DL is output.

In the PLL circuit 20A, the low speed bit width TL2
Is provided with a VCO 23 that outputs a low-speed clock CL of TF / 2, and the phase comparator 21 compares the phase of the frame pulse PF with the divide-by-2 clock CL / 2 supplied from the divide-by-two circuit 24A to oscillate the VCO 23. It controls the frequency and phase. As a result, the frame pulse PF and the frequency-divided clock CL / 2 can always maintain a constant phase relationship. In the example shown in FIG. 3, since the data extraction circuit 10 retimes the output data of the selector circuit 16 by the output of the VCO 23, the two-divided clock CL / 2 and the low-speed clock CL are used as the retiming margin. The phase adjustment circuit 25 is included to make the phase difference (half bit of the low speed clock).

FIG. 4 is a time chart showing the operation of the speed conversion circuit shown in FIG. The speed conversion circuit extracts the data of A1 and A2 from the high speed data DH of the high speed bit width TH having the frame period TF, and extracts the low speed bit width TL2.
A circuit for converting low speed data DL of = TF / 2.

The high speed data DH is input to the data extraction circuit 10 and is generated by the timing circuit 11 using the frame pulse PF and the high speed clock CH.
Timing signals ST1 and ST2 are read by a pair of first stage flip-flop circuits 12-1 and 12-2,
The first and second parallel data DP1 and DP2 having a bit width TF composed of only the bits A1 and A2 in the high speed data DH are output. These parallel data DP1 and DP2 are retimed by the pair of next-stage flip-flop circuits 13-1 and 13-1 by the frequency-divided clock CL / 2, and converted by the selector circuit 14 into 2 columns-1 columns and selected. It becomes the data DS. After that, the output clock (low-speed clock) CL of the VCO 23 is retimed by the flop-flop circuit 15 at the final stage to obtain the low-speed data DL.
Becomes

In the case where the other bits of A1 and A2 are extracted and converted into the low speed data DL, the first and second bits are also used.
This can be dealt with only by shifting the phases of the timing signals ST1 and ST2.

In the first embodiment, TL2 = TF
Since the case of / 2 has been described, the selector signal of the selector circuit 16 matches the output of the divide-by-two frequency circuit 24, but in other cases, the phase of the selector signal is changed by using the low-speed clock CL and the divided output. It can be handled if controlled.

As described above, the circuit of the present invention enables speed conversion into low-speed data such as TL2 ≠ TH × M, which is impossible with the conventional speed conversion circuit.

Next, as a second embodiment of the present invention, ST
The speed conversion circuit in the OH processing of the M-1 signal will be described.

FIG. 5 shows the STM-1 signal (155.52 Mb).
ps). OH signal of STM-1 signal is RSOH
(Regenerator Section Overhead Bit) and MSOH (Mu
Ltiplexer Section Overhead Bit), which are frame synchronization bits A1, A2 bytes, and BIP-8.
B1 as a result of B1 and B2 as a result of BIP-24
In addition to E1, F1, E2, which has a transmission capacity of 64 Kbps
D1-D3 with transmission capacity of Z1, Z2, 192Kbps
It is composed of D4 to D12 having a transmission capacity of 576 Kbps and other undefined bytes, and each is multiplexed in 1-byte units in one STM-1 signal frame.

FIG. 6 shows a block diagram of the OH processing section. O
The H processing section includes an OH signal insertion / separation panel 30, an OH processing panel 40, and a plurality of OH interface panels 5.
It is composed of 0 and. OH signal insertion / separation panel 30
Has a function of separating the OH signal from the main signal STM-1 signal or inserting the OH signal into the STM-1 signal. O
The H signal insertion / separation panel 30 does not input / output each byte in parallel, but the OH processing panel 40 shown in FIG. 7 as serial data having a bit rate of 6.48 Mbps and one frame of 8 kHz, which is configured only by the OH signal. I am handing over. In the OH processing panel 40, the speed conversion circuit performs speed conversion from 6.48 Mbps serial data to parallel data matching the transmission capacity of each byte, and transmits / receives each signal to / from the OH interface panel 50.

At this time, the clock of parallel data is 6
Serial data 6.48M such as 4kHz, 192kHz
It is not obtained by dividing the Hz clock. Therefore, a PLL circuit is used to set the parallel data clock to V
The VCO is generated by CO, and the VCO output clock 64 kHz is divided by 8 to create an 8 kHz clock, and the VCO is controlled by performing a phase comparison with the frame pulse.

FIG. 8 shows a speed conversion circuit according to the second embodiment of the present invention. In the illustrated speed conversion circuit, the data extraction circuit 10A includes a timing circuit 11A, a first-stage flip-flop circuit group including eight flip-flop circuits (F / F) 12-1 to 12-8, and eight flip-flop circuits. And a selector circuit 14A, a final-stage flip-flop circuit 15, and a delay circuit 16, and the PLL circuit 20B is a phase circuit. Comparison circuit 21
, LPF 22, VCO 23, and divide-by-8 circuit 24B
And a phase adjustment circuit 25.

The timing circuit 11A uses the high-speed clock CH
And the first to eighth timing signals ST1 to ST8 based on the frame pulse PF and the frame pulse PF. The first-stage flip-flop circuit groups 12-1 to 12-8 respectively hold the high-speed data DH in response to the first to second timing signals ST1 to ST8, and hold the first to eighth parallel signals. Data DP1〜
Output DP8. Next-stage flip-flop circuit group 13-
1 to 13-8 are synchronized with the divide-by-8 clock CL / 8 (clock obtained by dividing the low-speed clock CL by 8) supplied from the PLL circuit 20 and are respectively the first to eighth parallel data DP1 to DP8. Hold, and output the first to eighth retimed data. The selector circuit 14A selects one of the first to eighth retimed data in response to a selector signal described later, and selects the selected data D
Output S. The final stage flip-flop circuit 15 is
The selected data DS is held in response to the low speed clock CL and the low speed data DL is output. The delay circuit 16 generates the selector signal from the divide-by-8 clock CL / 8 and the low speed clock CL.

In the PLL circuit 20B, the low speed bit width TL2
The phase comparator 21 includes a VCO 23 for outputting a low-speed clock CL of TF / 8, and the phase comparator 21 compares the phase of the frame pulse PF with the divide-by-8 clock CL / 8 supplied from the divide-by-8 circuit 24B to perform oscillation of the VCO 23. It controls the frequency and phase. As a result, the frame pulse PF and the divide-by-8 clock CL / 8 can always maintain a constant phase relationship. Further, in order to obtain a retiming margin in the flip-flop circuit 15 at the final stage of the data extraction circuit 10A, a phase adjustment circuit 25 is provided between the VCO 23 and the 8 frequency divider circuit 24B.

FIG. 9 is a time chart showing the operation of the speed conversion circuit shown in FIG. The speed conversion circuit is a circuit that performs speed conversion from high-speed data DH having a high-speed bit width TH having a frame period TF, which is an OH signal, to low-speed data DL having a low-speed bit width TL2 = TF / 8, which is an E1 signal having a bit rate of 64 kbps. is there.

The high-speed data DH is input to the data extraction circuit 10A and written in the eight flip-flop circuits 12-1 to 12-8 forming the first-stage flip-flop circuit group. The write clock at this time is the 1st to 8th timings which were generated by the timing circuit 11A and were at the bit positions of 1 bit to 8 bits (indicated as E1-1 to E1-8 in FIG. 9) of the E1 byte. The signals ST1 to ST8 are used.

On the other hand, in the PLL circuit 20B, the low frequency clock CL of 64 kHz, which is the output of the VCO 23, is divided into eight.
The frequency is divided by 8 by 4B and the 8 kHz divided clock CL
/ 8 and the frame pulse PF are compared in phase by the phase comparator 21, and the output frequency and phase of the VCO 23 are controlled by the result of the phase comparison. As a result, the phase relationship between the 8 kHz divided clock CL / 8 and the frame pulse PF is always constant.

First stage flip-flop groups 12-1 to 12
The first to eighth parallel data DP1 to DP8, which are signals of 1 to 8 bits and 8 columns of E1 written in -8, use the frequency-divided clock CL / 8 as a clock and the flip-flop group 13-1 in the next stage. ~ 13-8 retimed, 8 rows-
It is input to the selector circuit 14A for one-column conversion. The selector circuit 14A performs column conversion based on the selector signal supplied from the delay circuit 16 and selects the selected data DS.
Is output. The selected data DS is retimed by the flop circuit 15 at the final stage, and the low speed data D
Output as L.

In the above embodiment, the case where N = 2 and 8 is described, but it is needless to say that the same can be applied to other cases where N is 2 or more.

[0038]

As described above, according to the present invention, as a low speed clock for a data extraction circuit for extracting arbitrary data from high speed data and converting it into low speed data, a low speed bit width of (1 / N) times the frame period is used. Since I am using the one of the following, even if the slow data width is not an integer multiple of the fast data width,
The desired slow data can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a speed conversion circuit according to an embodiment of the present invention.

FIG. 2 is a PLL used in the speed conversion circuit shown in FIG.
It is a block diagram showing a circuit.

FIG. 3 is a block diagram showing a speed conversion circuit according to a first embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the speed conversion circuit shown in FIG.

FIG. 5 is a frame diagram of an STM-1 signal.

FIG. 6 is a block diagram of OH processing.

FIG. 7 is a diagram showing OH serial data.

FIG. 8 is a block diagram showing a speed conversion circuit according to a seventh embodiment of the present invention.

9 is a time chart for explaining the operation of the speed conversion circuit shown in FIG.

FIG. 10 is a block diagram showing a conventional speed conversion circuit.

11 is a block diagram showing a specific example of the speed conversion circuit shown in FIG.

12 is a time chart for explaining the operation of the speed conversion circuit shown in FIG.

[Explanation of symbols]

10, 10A data extraction circuit 20, 20A, 20B PLL circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-3-149928 (JP, A) JP-A-8-56211 (JP, A) JP-A-5-336170 (JP, A) JP-A-5- 336088 (JP, A) JP 5-327782 (JP, A) JP 8-125641 (JP, A) JP 4-326635 (JP, A) JP 8-298503 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/00 H04J 3/06 H04L 7/033

Claims (7)

(57) [Claims] 1. A high-speed clock (CH) defining a high-speed bit width (TH), a frame pulse (PF) defining a frame period (TF), and the high-speed bit width (TH).
Of the low-speed clock (CL) and the low-speed bit width (TL2) for inputting high-speed data (DH) of the frame period (TF) and defining a low-speed bit width (TL2) wider than the high-speed bit width (TH). In a speed conversion circuit for outputting low speed data (DL), the low speed bit width (TL2) is represented by TL2 = TF / N (N is an integer of 2 or more) based on the frame pulse (PF). Low-speed clock generation means (20, 20A, 20B) for generating a low-speed clock (CL), the high-speed clock (CH), and the frame pulse (PF)
) And the low-speed clock (CL), predetermined data is extracted from the high-speed data (DH), and the extracted data is output as the low-speed data (DL) together with the low-speed clock (CL). Circuit (1
0, 10A), and a speed conversion circuit. 2. The low-speed clock generation means (20, 20)
The speed conversion circuit according to claim 1, wherein A, 20B) is a PLL circuit. 3. The PLL circuit (20, 20A, 20)
B) is the frame pulse (PF) and the divided clock (CL /
N) and a phase comparator (21) that outputs a phase comparison result, a low-pass filter (22) that removes a high frequency component of the phase comparison result to generate a control voltage, and the control voltage. In response to the voltage control oscillator (23) that oscillates the low speed clock (CL), and an N frequency dividing circuit that frequency-divides the low speed clock (CL) by N and outputs the frequency-divided clock (CL / N). 24, 24A,
24B) is included, The speed conversion circuit of Claim 2 characterized by the above-mentioned. 4. The PLL circuit (20A, 20B),
The voltage controlled oscillator (23) and the N frequency dividing circuit (24
A, 24B) and a phase adjustment circuit (25) inserted between
The speed conversion circuit according to claim 3, further comprising: 5. The data extraction circuit (10, 10A)
Is the high-speed clock (CH) and the frame pulse (PF)
) And N timing signals (ST1 to ST
Timing circuit (11, 11A) for generating N), and N flip-flops for holding N data among the high speed data (DH) in response to the N timing signals (ST1 to STN). A first stage flip-flop circuit group (12-1 to 12-N) which outputs N parallel data (DP1 to DPN), and the N number of flip-flop circuits in response to the divided clock (CL / N). Parallel data (DP1 to DPN) of N flip-flop circuits, and the next-stage flip-flop circuit group (13-1 to 13-1 to output N renumbered data).
13-N), and a selector circuit (14, 14) for selecting one of the N renumbered data and outputting the selected data.
14A) and a final stage flip-flop (15) for holding the selected data and outputting the low speed data (DL) in response to the low speed clock (CL). The speed conversion circuit according to 3 or 4. 6. The selector circuit (14) inputs the divided clock (CL / 2) as a selector signal as it is when the N is equal to 2. 5.
The speed conversion circuit described in. 7. When the N is 3 or more, the data extraction circuit (10A) generates a selector signal based on the divided clock (CL / N) and the low speed clock (CL). The speed conversion circuit according to claim 5, further comprising means (16) for supplying the selector signal to the selector circuit (14A).