JP3044853B2 - Destuff circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used in digital transmission and switching systems used in transmission systems. In particular, it relates to a destuff circuit.

[0002]

2. Description of the Related Art There is a stuff multiplex system as a system for performing synchronous transmission in a digital transmission system. For example, SONET
(Synchronous Optical NETw
In (ork), synchronous transmission is enabled by stuff multiplexing in byte units. FIG. 2 shows a configuration of a reception circuit and a destuff processing circuit of a conventional stuff multiplexer. In the figure, 201 is a reception data line, 202 is a reception clock line,
203 is a destuff control line, 204 is a write address generation circuit, 207 is a buffer memory, 208 is a phase comparator, 209 is a low-pass filter, 210 is a voltage controlled oscillator, 211 is a read address generation circuit, and 212 is an output data line. . Here, the reception data 201 and the reception clock 202 are signals synchronized in frequency and phase, and the destuff control signal 203 is “1” when the transmission side receives the stuff information inserted into the reception data 201 at the time of stuffing at the reception side. If there is no staff, it shall be "0". The stuffing method includes a positive stuff (P stuff) that inserts dummy data into transmission data to delay a data signal and a negative stuff (N stuff) that advances transmission data.
A description will be given by taking staff control as an example. The P destuffing process is achieved by writing the received data 201 excluding the dummy data inserted in the P stuffing process on the transmission side to the buffer memory 207 and reading out the buffer memory 207 at the net clock frequency included in the received data 201. You. In FIG. 2, when the destuff control signal 203 is “0”, the reception data 201 is written into the write address generation circuit 20.
4, sequentially writing to the buffer memory 207,
When the destuff control signal 203 is “1”, one P
In order to delete the 1-byte dummy data inserted by the stuff, the reception clock 202 is continuously omitted for eight clocks, and the writing of the dummy data to the buffer memory 207 is prohibited. The voltage controlled oscillator 210 is an oscillator for generating a clock signal having a net frequency of the received data 201. The read address generation circuit 211 generates a read timing of the buffer memory 207 based on an output clock signal of the voltage controlled oscillator 210. The phase comparator 208 outputs 8
After comparing the phase of the output of the write address generation circuit 204 and the output of the read address generation circuit 211 including the continuous clock missing component, the high-frequency component is cut by the low-pass filter 209 and then the oscillation frequency of the voltage-controlled oscillator 210 is controlled. Then, the oscillation frequency of the voltage controlled oscillator 210 is locked to the net data frequency of the received data 201. With this control, the write frequency and the read frequency to and from the buffer memory 207 become equal, so that byte-wise destuffing processing is realized. Further, even when destuffing occurs continuously, for example, when the destuffing control signal 203 becomes “1” for N consecutive times, destuffing processing can be performed by continuously skipping N × 8 clocks. It is possible.

[0003]

In the byte destuff processing circuit shown in FIG. 2, the reception clock signal 202 is used to delete the dummy data inserted by the stuff.
Is generated continuously, and the frequency control of the read clock is performed by the continuous toothless clock signal and the voltage controlled oscillator 2.
Since the output is performed based on the phase comparison with the ten outputs, the frequency of the output clock of the voltage controlled oscillator 210 fluctuates greatly during continuous omission, and the temporal fluctuation amount of the output data 212, that is, the jitter increases rapidly.

An object of the present invention is to provide a destuffing circuit which eliminates such a drawback and suppresses destuffing jitter and can cope with continuously occurring destuffing processing. .

[0005]

SUMMARY OF THE INVENTION The present invention provides a buffer memory for storing received data from which dummy data has been removed,
A write address generation circuit for continuously omitting the reception clock in accordance with the destuff control signal corresponding to the dummy data and inhibiting writing of the dummy data into the buffer memory; and an oscillation clock in response to the applied voltage signal And a read-address generation circuit for generating a read timing signal for reading data from the buffer memory according to an oscillation clock from the voltage-controlled oscillator. And a destuff holding counter for increasing the count in accordance with a destuff control signal corresponding to the clock signal, and a toothlessness for generating a toothlessness in a clock signal synchronized with the received signal when the count value of the destuffing counter is other than the initial value. Generate a clock and decrement the destuff holding counter. A random omission generating circuit for randomly setting the time distribution of the omission occurrence in the omission generating circuit; a phase of a read timing signal from the read address generating circuit; A phase comparator for comparing the phase of the missing clock signal from the generation circuit with the phase of the voltage signal applied to the voltage-controlled oscillator according to a result of the comparison.

[0006]

The write address generation circuit for generating the timing for writing the received data to the memory removes the stuff information by performing the continuous omission of eight clocks with one stuff. For the phase comparator that generates the control signal of the voltage-controlled oscillator, the output of the dispersion missing generation circuit that generates the clock missing is used. In order to hold the number of times of destuffing, a destuffing holding counter is provided to count the number of times of destuffing. The destuffing of the destuff holding counter is performed in response to the start of the operation of the omission generating circuit. The operation of the dispersion omission generation circuit starts under the condition that the internal value of the destuff holding counter is other than “0”. And
A random generating section for randomly delaying the tooth missing generation position is connected to the destuff holding counter and the distributed tooth missing generation circuit.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a receiving circuit and a destuffing processing circuit of a stuff multiplexing apparatus according to this embodiment. In the figure,
101 is a reception data line, 102 is a reception clock line, 10
3 is a destuff control line, 104 is a write address generation circuit, 105 is a destuff holding counter, 106 is a dispersion omission generation circuit, 107 is a buffer memory, 108 is a phase comparator, 109 is a low-pass filter, 110 is a voltage controlled oscillator , 111 are read address generation circuits, 112
Is an output data line.

In this embodiment, as shown in FIG. 1, a buffer memory 107 in which received data from which dummy data has been removed is stored, and a reception clock 202 is continuously output according to a destuff control signal corresponding to the dummy data. Let the teeth fall
A write address generation circuit 104 for inhibiting the writing of dummy data to the buffer memory 107, a voltage-controlled oscillator 110 for controlling the phase of the oscillation clock according to the applied voltage signal, and a clock for the oscillation clock from the voltage-controlled oscillator 110 Read address generating circuit 111 for generating a read timing signal for reading data from the buffer memory 107 according to the present invention. Destuff holding counter 10
5 and when the count value of the destuff holding counter 105 is other than the initial value, a dispersion clock for generating a missing clock in the clock signal synchronized with the received signal and causing the destuff holding counter 105 to count down. Tooth omission generation circuit 106, random generation section 113 for randomly setting the time distribution of omission occurrence at distributed omission generation circuit 106, phase of read timing signal from read address generation circuit 111, and generation of distributed omission Circuit 10
And a phase comparator 108 for comparing the phase of the missing clock signal from Step 6 with the phase of the voltage signal applied to the voltage controlled oscillator 110 in accordance with the comparison result.

Here, the reception data 101 and the reception clock 102 are signals synchronized in frequency and phase, and the destuff control signal 103 is transmitted when the reception side receives the stuff information inserted into the reception data 101 at the time of the stuff by the transmission unit. 1 ", and" 0 "when there is no staff. Here, the P stuff control in byte units will be described as an example. The P destuffing process is achieved by writing the received data 101 excluding the dummy data inserted in the P stuffing process on the transmitting side to the buffer memory 107 and reading the buffer memory 107 at the net clock frequency included in the received data 101. You. In FIG. 1, when the destuff control signal 103 is “0”, the received data 101 is sequentially written into the buffer memory 107 according to the write address generation circuit 104, while the destuff control signal 103 is
Is "1", the reception clock 10 is used to delete 1-byte dummy data inserted by one P stuff.
2 is skipped continuously for 8 clocks, and writing of dummy data to the buffer memory 107 is prohibited.
Writing of data signals excluding the dummy data inserted in 01 is performed. On the other hand, in addition to the write clock of the buffer memory 107 which is continuously missing due to the generation of the read clock from the buffer memory 107, the clock signal in which the missing teeth generated by the dispersion missing generation circuit 106 are dispersed is generated. Achieved by using

When the destuff control signal 103 is "0", the received data 101 is written to the address generation circuit 104.
And the destuff control signal 103 is "1", the reception clock 102 is continuously transmitted for eight clocks in order to delete one byte of dummy data inserted by one P stuff. And writing of dummy data to the buffer memory 107 is prohibited.

On the other hand, the destuff holding counter 105 is a counter for counting the destuff information supplied from the destuff control line 103, and is a random number for randomly generating a time delay of the missing tooth of the distributed missing clock generation circuit 106. Connected to generator 113. When the internal value of the destuff holding counter 105 is “0”, the random generation unit 113 does not operate and the operation of the dispersion tooth omission generation circuit 106 is stopped. When the internal value is “1” or more, the operation of the dispersion omission generating circuit 106 is started, and the internal value is decremented by “1”. Here, the random generator 11
In step 3, the information for delaying the time position of the toothless clock is provided to the distributed toothlessness generation circuit 106 only when information equal to or more than the internal value "1" of the destuff holding counter 105 is obtained. In addition, the delay time is generated randomly. The phase comparator 108 is the read address generation circuit 1
11 is compared with the output of the dispersion omission generating circuit 106, and the output of the voltage controlled oscillator 110 is
, And the read address generation circuit 111 generates the read timing of the buffer memory 107 based on the output of the voltage controlled oscillator 110 and sets it as the read output data signal 112 of the buffer memory 107.
The dispersion period of the dispersion omission of the dispersion omission generation circuit 106 is 1
It is not limited to frames, but is determined by the stuff rate, buffer size, and amount of jitter suppression.

[0012]

According to the present invention, as described above, since the lack of clocks is dispersed and rearranged at random, there is an effect that jitter and wander can be suppressed.
The effect is remarkable when used in a plurality of transmission systems.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Receive data line 102 Receive clock line 103 Destuff control line 104 Write address generation circuit 105 Destuff holding counter 106 Dispersion missing generation circuit 107 Buffer memory 108 Phase comparator 109 Low pass filter 110 Voltage controlled oscillator 111 Read address generation circuit 112 Output Data line 113 Random generator 201 Receive data line 202 Receive clock line 203 Destuff control line 204 Write address generation circuit 207 Buffer memory 208 Phase comparator 209 Low pass filter 210 Voltage controlled oscillator 211 Read address generation circuit 212 Output data line

Continuation of front page (56) References JP-A-1-188127 (JP, A) JP-A-61-224740 (JP, A) JP-A-3-173233 (JP, A) JP-A-4-177932 (JP, A) JP-A-4-177933 (JP, A) JP-A-4-257133 (JP, A) JP-A-4-360432 (JP, A) JP-A-5-75563 (JP, A) 5-130064 (JP, A) JP-A-5-175930 (JP, A) JP-A-5-308352 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00 -3/26 H04L 7/00-7/10

Claims (1)

(57) [Claims] A buffer memory for storing received data from which the dummy data has been removed; and a receiving clock that is continuously dropped in accordance with a destuff control signal corresponding to the dummy data. A write address generation circuit for inhibiting writing of data, a voltage controlled oscillator for controlling the phase of an oscillation clock according to a given voltage signal, and reading data from the buffer memory according to an oscillation clock from the voltage controlled oscillator In a destuff circuit having a read address generation circuit for generating a read timing signal, a destuff holding counter for increasing the count in accordance with a destuff control signal corresponding to dummy data, and a count value of the destuff holding counter are initialized. If the value is other than the value, skip the clock signal synchronized with the received signal. A distributed omission generation circuit that generates a tooth omission clock to be generated and counts down the destuff holding counter, and a random generation section that randomly sets a time distribution of omission occurrence in the distributed omission generation circuit, The phase of the read timing signal from the read address generation circuit is compared with the phase of the missing clock signal from the dispersion missing generation circuit, and the voltage signal applied to the voltage controlled oscillator is adjusted according to the comparison result. A destuff circuit comprising a phase comparator.